CN114283755B

CN114283755B - Display control module, display control method and display device

Info

Publication number: CN114283755B
Application number: CN202111598714.3A
Authority: CN
Inventors: 韩鹏; 何惠东; 姜倩文; 石娟娟; 杜伟华; 张�浩; 陈丽莉
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2021-12-24
Filing date: 2021-12-24
Publication date: 2023-09-05
Anticipated expiration: 2041-12-24
Also published as: CN114283755A

Abstract

The invention provides a display control module, a display control method and a display device. The display control module comprises a fixation point calculation module, a high-definition display area calculation module, an image low-definition processing module, a time sequence control module, a grid scanning module, a data voltage supply circuit and a gating circuit; the gaze point calculation module calculates gaze location information; the high-definition display area calculation module is used for calculating the high-definition display area of the display panel; the time sequence control module generates a grid line driving time sequence, a data line gating control signal and a data voltage providing control signal according to the high-definition display area; the data voltage supply circuit controls to supply high-definition data voltage or low-definition data voltage to the corresponding column data line; the gating circuit controls communication between the corresponding column data line and the data voltage receiving terminal of the corresponding column pixel circuit to supply the data voltage to the corresponding column pixel circuit through the corresponding column data line. The invention can reduce the power consumption while ensuring the display effect.

Description

Display control module, display control method and display device

Technical Field

The present invention relates to the technical field of display control modules, and particularly to a display control method and a display device.

Background

In the display industry, in order to meet the needs of people, along with continuous innovation of technology, the display definition and refresh rate are broken through continuously, but high definition inevitably brings about a large increase in energy consumption, and higher energy support is needed, so that the frequency and the number of components are multiplied, and the power support is needed to be larger. However, in view of the demands of human eyes, the human eyes only pay attention to the focused area, and the focused area is very small for the whole display screen, while the other large part is only acquired by the human eyes by utilizing the residual light, and the image information acquired by the residual light is only approximate image information, so that the image information is high in definition or not, and the focused area is not influenced, so that the resource waste is caused.

Disclosure of Invention

The invention mainly aims to provide a display control module, a display control method and a display device, which solve the problem that the power consumption cannot be reduced while the display effect is ensured in the prior art.

In order to achieve the above-mentioned objective, an embodiment of the present invention provides a display control module, which is applied to a display device, wherein the display device includes a display panel and a gate scanning module, and the display panel includes a plurality of rows and columns of pixel circuits, a plurality of rows and columns of gate lines, and a plurality of columns of data lines; the display control module comprises a fixation point calculation module, a high-definition display area calculation module, an image low-definition processing module, a time sequence control module, a grid scanning module, a data voltage supply circuit and a gating circuit;

The gazing point calculating module is used for calculating gazing position information according to the acquired eyeball images;

the high-definition display area calculation module is used for calculating a high-definition display area of the display panel according to the gazing azimuth information;

the image low-definition processing module is used for acquiring image information to be displayed, and performing low-definition processing on the image information to be displayed in other display areas except the high-definition display area of the display panel to acquire low-definition image information;

the time sequence control module is used for generating a grid line driving time sequence, a data line gating control signal and a data voltage providing control signal according to the high-definition display area, providing the grid line driving time sequence to the grid scanning module, providing the data line gating control signal to the gating circuit and providing the data providing control signal to the data voltage providing circuit;

the grid scanning module is used for providing corresponding grid driving signals for the multiple rows of grid lines according to the grid scanning time sequence;

the data voltage providing circuit is used for receiving the low-definition image information and the high-definition image information corresponding to the high-definition display area in the image information to be displayed, processing the high-definition image information to obtain high-definition data voltage, processing the low-definition image information to obtain low-definition data voltage, and controlling to provide the high-definition data voltage or the low-definition data voltage to the corresponding column data line under the control of the data providing control signal;

The gating circuit is used for controlling the communication between the corresponding column data line and the data voltage receiving end of the corresponding column pixel circuit according to the data line gating control signal so as to provide data voltage for the corresponding column pixel circuit through the corresponding column data line.

Optionally, the display control module according to at least one embodiment of the present invention further includes a data decoding module;

the data decoding module is used for carrying out data decoding on the eyeball image to obtain a decoded eyeball image and carrying out data decoding on the image information to obtain decoded image information;

the gazing point calculating module is used for calculating gazing position information according to the decoded eyeball image;

the image information to be displayed is the decoded image information.

Optionally, the display control module according to at least one embodiment of the present invention further includes a processor and a data driving module; the data voltage supply circuit and the gate circuit are included in the data driving module;

the processor, the data decoding module, the gaze point calculation module, the high-definition area calculation module, the image low-definition processing module, the time sequence control module, the grid scanning module and the data driving module are connected through buses;

The processor is used for controlling the data decoding module to transmit the decoded image information to the gazing point calculating module, controlling the gazing point calculating module to provide gazing direction information to the high-definition display area calculating module, controlling the high-definition display area calculating module to provide the high-definition display area to the image low-definition processing module and the time sequence control module, controlling the image low-definition processing module to provide the low-definition image information to a data voltage providing circuit in the data driving module, controlling the time sequence control module to provide the grid line driving time sequence to the grid scanning module, controlling the time sequence control module to provide the data line gating control signal to a gating circuit in the data driving module, and controlling the time sequence control module to provide the data providing control signal to the data voltage providing circuit in the data driving module.

Optionally, the processor, the data decoding module, the gaze point calculation module, the high definition region calculation module, the image low definition processing module, the timing control module, the gate scanning module, and the data driving module are all included in a display driving integrated circuit;

The display driving integrated circuit is a control processing chip based on RISC-V architecture.

Optionally, the gating circuit includes a shift register, a level reading circuit and a gating switching circuit;

the shift register is used for providing a plurality of digital control levels for the level reading circuit through a plurality of output ends according to the data line gating control signal;

the level reading circuit is used for reading the digital control level, converting the digital control level into corresponding analog control level and providing a plurality of analog control levels to the gating switch circuit;

the gating switch circuit is used for controlling the communication between the data lines of the corresponding columns and the data voltage receiving ends of the pixel circuits of the corresponding columns under the control of the analog control level.

Optionally, the shift register includes N flip-flops sequentially cascaded; the trigger access of the trigger is connected with a trigger clock signal; the input end of the first trigger is connected with the data line gating control signal; n is an integer greater than 1;

the non-inverting output end of the n-th trigger is electrically connected with the input end of the n+1th trigger; the positive phase output end of the nth trigger is used for outputting an nth digital control level; n is a positive integer, and n+1 is less than or equal to N;

The level reading circuit is respectively and electrically connected with the positive phase output ends of the N triggers and is used for reading the digital control level from the positive phase output ends.

Optionally, the gating switching circuit includes N switching transistors; n is an integer greater than 1; n is a positive integer, and n+1 is less than or equal to N;

the control electrode of the nth switching transistor is electrically connected with the nth analog control level output end of the level reading circuit, the first electrode of the nth switching transistor is electrically connected with the nth column data line, and the second electrode of the nth switching transistor is electrically connected with the data voltage receiving end of the nth column pixel circuit;

the level reading circuit is used for providing an nth analog control level through the nth analog control level output terminal.

Optionally, the data voltage providing circuit includes a conversion circuit, an output buffer circuit, and an output circuit;

the conversion circuit is used for receiving the low-definition image information and high-definition image information corresponding to a high-definition display area in the image information to be displayed, processing the high-definition image information to obtain high-definition data voltage, and processing the low-definition image information to obtain low-definition data voltage;

The output buffer circuit is used for buffering the high-definition data voltage and the low-definition data voltage;

the output circuit is used for controlling to provide high-definition data voltage or low-definition data voltage to the corresponding column data line under the control of the data providing control signal.

Optionally, the display control module according to at least one embodiment of the present invention further includes an eyeball image acquisition module, an image signal processing module, and an image information acquisition module;

the eyeball image acquisition module is used for acquiring eyeball images;

the image signal processing module is used for processing the eyeball image to obtain a processed eyeball image, and sending the processed eyeball image to the data decoding module so that the data decoding module decodes the processed eyeball image to obtain the decoded eyeball image;

the image information acquisition module is used for acquiring the image information to be displayed from a display data source.

The embodiment of the invention also provides a display control method which is applied to the display control module and comprises the following steps:

the gaze point calculation module calculates gaze location information according to the acquired eyeball image;

The high-definition display area calculation module calculates a high-definition display area of the display panel according to the gazing azimuth information;

the image low-definition processing module acquires image information to be displayed, and performs low-definition processing on the image information to be displayed of other display areas except the high-definition display area of the display panel to acquire low-definition image information;

the time sequence control module generates a gate line driving time sequence, a data line gating control signal and a data voltage providing control signal according to the high-definition display area, provides the gate line driving time sequence to the gate scanning module, provides the data line gating control signal to the gating circuit, and provides the data providing control signal to the data voltage providing circuit;

the grid scanning module provides corresponding grid driving signals for at least part of grid lines in a plurality of rows of grid lines according to the grid scanning time sequence;

the data voltage providing circuit receives low-definition image information and high-definition image information corresponding to a high-definition display area in the image information to be displayed, processes the high-definition image information to obtain high-definition data voltage, processes the low-definition image information to obtain low-definition data voltage, and controls the data voltage providing circuit to provide the high-definition data voltage or the low-definition data voltage to corresponding column data lines under the control of the data providing control signal;

The gating circuit controls the communication between the corresponding column data line and the data voltage receiving end of the corresponding column pixel circuit according to the data line gating control signal so as to provide data voltage for the corresponding column pixel circuit through the corresponding column data line.

Optionally, the gaze point calculation module calculates a time period between two adjacent time points of different gaze location information according to the acquired eyeball image as the adjustment time period; the conditioning time period includes at least one conditioning phase; each adjusting stage comprises a fusion image output stage and a high-definition image output stage;

the step of providing the corresponding gate driving signals to at least part of the plurality of rows of gate lines by the gate scanning module according to the gate scanning time sequence comprises the following steps:

in the fused image output stage, the grid scanning module provides a grid driving signal for grid lines included in a display panel according to the grid scanning time sequence so as to control the grid lines included in the display panel to be opened in sequence;

in the high-definition image output stage, the gate scanning module provides corresponding gate driving signals for high-definition control gate lines according to the gate scanning time sequence so as to control the high-definition control gate lines to be opened in sequence;

The high-definition control grid line is a grid line electrically connected with the pixel circuit in the high-definition display area.

the step of controlling the data voltage supply circuit to supply the high-definition data voltage or the low-definition data voltage to the corresponding column data line under the control of the data supply control signal includes:

in the fused image output stage, under the control of the data providing control signal, the data voltage providing circuit writes the high-definition data voltage into the high-definition control data line when the high-definition control gate line is opened, writes the low-definition data voltage into the low-definition control data line, and writes the low-definition data voltage into the corresponding column data line when the low-definition control gate line is opened;

in the high-definition image output stage, the data voltage supply circuit writes high-definition data voltage into a high-definition control data line under the control of the data supply control signal;

The high-definition control grid line is a grid line electrically connected with the pixel circuit in the high-definition display area, the low-definition control grid line is a grid line except the high-definition control grid line, which is included in the display panel, the high-definition control data line is a data line electrically connected with the pixel circuit in the high-definition display area, and the low-definition control data line is a data line except the high-definition control data line, which is included in the display panel.

the step of controlling the communication between the data lines of the corresponding columns and the data voltage receiving ends of the pixel circuits of the corresponding columns by the gating circuit according to the data line gating control signal comprises the following steps:

in the fused image output stage, the gating circuit controls the data lines included in the display panel to be communicated with the data voltage receiving ends of the corresponding column pixel circuits respectively according to the data line gating control signals;

In the high-definition image output stage, the gating circuit controls the communication between the high-definition control data line and the data voltage receiving end of the corresponding column pixel circuit according to the data line gating control signal;

the high-definition control data line is a data line electrically connected with the pixel circuit in the high-definition display area.

The embodiment of the invention also provides a display device which comprises the display control module.

The display control module, the display control method and the display device can control the refresh rate of the high-definition display area to be larger than that of the low-definition display area so as to reduce power consumption while ensuring the display effect.

Drawings

FIG. 1 is a block diagram of a display control module according to at least one embodiment of the invention;

FIG. 2 is a block diagram of a display control module according to at least one embodiment of the invention;

FIG. 3 is a micro-architecture diagram of a processor in a display control module according to at least one embodiment of the invention;

FIG. 4 is a schematic view of a high definition display area;

FIG. 5 is a block diagram of at least one embodiment of a gating circuit in a display control module according to the present invention;

FIG. 6 is a block diagram of at least one embodiment of the gating circuit;

FIG. 7 is a block diagram of at least one embodiment of the gating circuit;

FIG. 8 is a diagram showing waveforms of gate driving signals and data line gate control signals X1 outputted from one row of gate lines during a fused image output stage, and waveforms of gate driving signals and data line gate control signals outputted from one row of gate lines during a high definition image output stage, when at least one embodiment of the gate circuit shown in FIG. 7 is in operation;

FIG. 9 is a block diagram of at least one embodiment of a data voltage providing circuit in a display control module according to the present invention;

fig. 10 is a schematic workflow diagram of a display control module according to at least one embodiment of the invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The transistors used in all embodiments of the present invention may be transistors, thin film transistors or field effect transistors or other devices having the same characteristics. In the embodiment of the invention, in order to distinguish the two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.

In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the first pole may be a source and the second pole may be a drain.

The display control module is applied to a display device, and the display device comprises a display panel and a grid scanning module, wherein the display panel comprises a plurality of rows and columns of pixel circuits, a plurality of rows of grid lines and a plurality of columns of data lines; the display control module comprises a fixation point calculation module, a high-definition display area calculation module, an image low-definition processing module, a time sequence control module, a grid scanning module, a data voltage supply circuit and a gating circuit;

When the display control module disclosed by the embodiment of the invention works, the gazing point calculation module carries out recognition calculation on eyeball images to calculate the gazing direction of eyes; the high-definition area calculation module calculates an area needing high-definition display according to the gazing direction of the eyes; the time sequence control module generates a control time sequence according to the high-definition display area, and the control time sequence is used for controlling grid scanning and data scanning.

In a specific implementation, the high-definition display area calculation module may calculate the high-definition display area of the display panel according to the gaze location information in combination with the resolution of the display panel.

When the display control module provided by the embodiment of the invention works, after the gaze point calculation module calculates different gaze direction information according to the acquired eyeball images, the adjustment time period can comprise at least one adjustment stage, and the adjustment stage can comprise a fusion image output stage and a high-definition image output stage;

in the fused image output stage, the grid scanning module provides grid driving signals for grid lines included in a display panel according to the grid scanning time sequence so as to control the grid lines included in the display panel to be sequentially opened, the data voltage providing circuit writes the high-definition data voltage into the high-definition control data line when the high-definition control grid lines are opened and writes the low-definition data voltage into the low-definition control data line when the low-definition control grid lines are opened under the control of the data providing control signals, and the gating circuit controls the data lines included in the display panel to be respectively communicated with data voltage receiving ends of the corresponding column pixel circuits according to the data line gating control signals so as to output fused images (the fused images comprise high-definition images and low-definition images);

In the high-definition image output stage, the gate scanning module provides corresponding gate driving signals for the high-definition control gate lines according to the gate scanning time sequence so as to control the high-definition control gate lines to be opened in sequence, and the data voltage providing circuit writes high-definition data voltages into the high-definition control data lines under the control of the data providing control signals; the gating circuit controls communication between the high-definition control data line and the data voltage receiving end of the corresponding column pixel circuit according to the data line gating control signal so as to only provide high-definition images for the high-definition display area.

The embodiment of the invention can control the refresh rate of the high-definition display area to be larger than that of the low-definition display area so as to reduce the power consumption while ensuring the display effect.

In a specific implementation, the low-definition display area may be an area other than the high-definition display area included in the display area of the display panel.

In at least one embodiment of the present invention, the duration of the fused image output stage may be a frame time, the duration of the high-definition image output stage may be a frame time, and in one frame time, the fused image is sent out, and a plurality of rows of grid lines included in the display panel are normally opened in sequence to display the fused image; at another frame time, only the high-definition image is sent out, and the high-definition display area is controlled to display the high-definition image, and the low-definition display area still keeps displaying the original picture due to the characteristic of liquid crystal; operating in this manner, the refresh rate of the high definition region may be 2 times the refresh rate of the low definition region. For example, the refresh rate of the high definition display area may be 120Hz and the refresh rate of the low definition display area may be 60Hz.

In at least one embodiment of the present invention, the duration of the fused image output stage may be at least one frame time, and the duration of the high-definition image output stage may be at least one frame time, but is not limited thereto.

In a specific implementation, the high-definition control gate line may be a gate line electrically connected to a pixel circuit in the high-definition display area, the low-definition control gate line may be a gate line included in the display panel except for the high-definition control gate line, the high-definition control data line may be a data line electrically connected to the pixel circuit in the high-definition display area, and the low-definition control data line may be a data line included in the display panel except for the high-definition control data line.

In at least one embodiment of the present invention, the adjustment period may be a period between two adjacent time points of different gaze location information calculated by the gaze point calculation module according to the acquired eyeball image, but is not limited thereto. That is, the mth adjustment period may be a time point when the gaze point calculation module calculates gaze location information according to the mth time of the eyeball image, and a time point when the gaze point calculation module calculates gaze location information according to the mth+1th time of the eyeball image, where m is a positive integer.

The display control module according to at least one embodiment of the present invention may further include a data decoding module;

the image information to be displayed is the decoded image information.

In a specific implementation, the display control module may include a data decoding module, configured to parse the image information and the eyeball image to obtain a decoded eyeball image and decoded image information, and the gaze point calculation module calculates gaze location information according to the decoded eyeball image.

In at least one embodiment of the present invention, the display control module further includes a processor and a data driving module; the data voltage supply circuit and the gate circuit are included in the data driving module;

In an implementation, the processor, the data decoding module, the gaze point calculation module, the high definition region calculation module, the image low definition processing module, the timing control module, the gate scanning module, and the data driving module may all be included in a display driving integrated circuit.

In an implementation, the data voltage supply circuit and the gate circuit are included in the data driving module, and the processor, the data decoding module, the gaze point calculation module, the high definition region calculation module, the image low definition processing module, the timing control module, the gate scanning module, and the data driving module may be all included in a display driving integrated circuit. The processor is used for allocating resources in the display driving integrated circuit, and the processor can adopt a 5-stage pipeline architecture and can perform calculation and data processing. The processor may be configured to control resource allocation among the data decoding module, the gaze point calculation module, the high definition region calculation module, the image low definition processing module, the timing control module, the gate scanning module, and the data driving module.

The display control module of at least one embodiment of the invention is applied to a display device, and the display device comprises a display panel and a grid scanning module, wherein the display panel comprises a plurality of rows and columns of pixel circuits, a plurality of rows of grid lines and a plurality of columns of data lines; as shown in fig. 1, the display control module includes a gaze point calculating module 11, a high definition display area calculating module 12, an image low definition processing module 13, a timing control module 14, a gate scanning module 15, a data voltage providing circuit, a gate circuit, a data decoding module 17, and a processor 10;

The data voltage supply circuit and the strobe circuit are included in the data driving module 16;

the processor 10, the data decoding module 17, the gaze point calculation module 11, the high definition region calculation module 12, the image low definition processing module 13, the timing control module 14, the gate scanning module 15 and the data driving module 16 are connected through a bus B1;

the processor 10, the data decoding module 17, the gaze point calculation module 11, the high definition region calculation module 12, the image low definition processing module 13, the timing control module 14, the gate scanning module 15, and the data driving module 16 are all included in a display driving integrated circuit DI.

In at least one embodiment of the present invention, the display driver integrated circuit DI may be, but is not limited to, a control processing chip based on RISC-V (RISC-V is an open source Instruction Set Architecture (ISA) based on the Reduced Instruction Set (RISC) principle.

In at least one embodiment of the present invention, the processor 10 may be a CPU (central processing unit) micro-core of RISC-V architecture, but is not limited thereto.

As shown in fig. 2, based on at least one embodiment of the display control module shown in fig. 1, the display control module according to at least one embodiment of the present invention further includes a system clock K1, a first interface M1, a second interface M2, and a third interface C1, a first memory R1, a second memory R2, and an ISP (Image Signal Processing ) module 20;

The system clock K1, the first interface M1, the second interface M2, and the third interface C1, the first memory R1, the second memory R2, and the ISP module 20 may be included in the display driving integrated circuit DI;

the first interface M1 may be an MIPI (Mobile Industry Processor Interface mobile industry processor interface) (Display Serial Interface ) interface;

the first interface M1 is electrically connected to a display data source (not shown in fig. 2, which is disposed outside the display driving integrated circuit DI) for receiving the image information to be displayed from the display data source 101 and providing the image information to be displayed to the data decoding module 17 through the bus B1;

the second interface M2 may be an MIPI CSI interface (CSI interface is a Camera serial interface), and the third interface C1 may be a Camera Link (connection) interface;

the second interface M2 and the third interface C1 may be electrically connected to a camera sensor (not shown in fig. 2, which is disposed outside the display driving integrated circuit DI) for transmitting an eyeball image provided by the camera sensor, respectively;

The ISP module 20 is electrically connected to the second interface M2, the third node C1, and the bus B1, and is configured to receive the eyeball image, perform image processing on the eyeball image, obtain a processed eyeball image, and provide the processed eyeball image to the data decoding module 17 through the bus B1; the data decoding module 17 is configured to decode the processed eyeball image to obtain a decoded eyeball image.

In at least one embodiment of the present invention, the ISP module may process the eyeball image as follows: black level compensation, lens correction, bad pixel correction, color interpolation, bayer (Bayer is an original picture inside a camera, commonly referred to as a. Raw) noise removal, white balance (AWB) correction, color correction, gamma correction, color space conversion (RGB to YUV), color-dysphoria removal and edge enhancement in YUV (Y is gray, U, V represents chromaticity of color) color space, color and contrast enhancement, automatic exposure control, and the like; but is not limited thereto.

In at least one embodiment shown in fig. 2, the first memory R1 may be a ROM (read only memory), and the second memory R2 may be a RAM (random access memory); the first memory R1 and the second memory R2 may be electrically connected to the bus B1, respectively;

The system clock K1 is used for providing a clock signal.

In at least one embodiment of the present invention, the display data source is disposed outside the display driving integrated circuit, and the display data source may be a high-definition data source, and the display data source may be used to provide high-definition image information. In an implementation, the display data source may be a processor, for example, but not limited to, a motherboard of a mobile phone.

In at least one embodiment shown in fig. 2, the first memory R1 and the second memory R2 are included in a storage unit, where the storage unit is a memory of the processor 10, and the first buffer, the second buffer, and the third buffer are memory spaces in the storage unit;

storing the low-definition image information in the first buffer;

and storing high-definition image information corresponding to the high-definition display area in the second buffer.

And storing fused image information in the third buffer, wherein the fused image information comprises the low-definition image information and the high-definition image information corresponding to the high-definition display area.

In operation of at least one embodiment of the present invention as shown in fig. 2, in a fused image output stage, the third buffer sends out the fused image information, and the data driving module 16 converts the high-definition image information into a high-definition data voltage and converts the low-definition image information into a low-definition data voltage; in the high-definition image output stage, the second buffer sends the high-definition image information to the data driving module 16, and the data driving module 16 converts the high-definition image information into a high-definition data voltage.

In at least one embodiment shown in fig. 2, a data transmission module 21 may be further disposed in the display driving integrated circuit, where the data transmission module 21 is configured to transmit display data to a display panel, and the internal structure of the data transmission module is the same as that of the existing data transmission module, and may include a DAC (digital-to-analog converter), a buffer, and the like. When the display data is normally supplied to the pixel circuits, that is, when the high-definition display area and the low-definition display area are not distinguished, the high-definition display data is supplied to all the pixel circuits included in the display panel, the corresponding display data may be supplied to each data line through the data transmission module 21.

Fig. 3 is a micro-architecture diagram of the processor.

In fig. 3, IF is a first stage pipeline, ID is a second stage pipeline, EX is a third stage pipeline, MEM is a fourth stage pipeline, WB is a fifth stage pipeline.

In fig. 3, the ALU is an arithmetic logic unit, the RAM is a random access memory, and the ROM is a read only memory.

In fig. 4, reference numeral 40 denotes a high definition display region, the a-th, a+1-th, a+2-th, and a+3-th row gate lines are electrically connected to pixel circuits located in the high definition display region, and the b-th, b+1-th, b+2-th, b+3-th, and b+4-th column data lines db+2, db+3, and db+4 are electrically connected to pixel circuits located in the high definition display region; a and b are positive integers;

In the display control module according to at least one embodiment of the present invention, the gate scan module may provide corresponding gate driving signals to Ga, ga+1, ga+2 and ga+3 in sequence only during one frame time to control Ga, ga+1, ga+2 and ga+3 to be turned on in sequence, and may provide corresponding data voltages to Db, db+1, db+2, db+3 and db+4 in one frame time only to control to provide corresponding data voltages to the high definition display area A0 only during a predetermined period of time.

In a specific implementation, the gating circuit may include a shift register, a level reading circuit and a gating switch circuit, where the shift register provides a plurality of digital control levels according to a data line gating control signal, the level reading circuit reads the digital control levels and converts the digital control levels into analog control levels, and the gating switch circuit controls communication between a corresponding column data line and a data voltage receiving terminal of a corresponding column pixel circuit under control of the analog control levels.

As shown in fig. 5, the gate circuit may include a shift register 51, a level reading circuit 52, and a gate switching circuit 53;

the shift register 51 is configured to provide 480 digital control levels to the level reading circuit 52 through 480 output terminals according to the data line strobe control signal X1;

the level reading circuit 52 is electrically connected to the 480 output terminals, and is configured to convert the digital control level into a corresponding analog control level, and provide a plurality of analog control levels to the gate switch circuit 53;

the gate switch circuit 53 is electrically connected to the data lines of the columns, the output terminals of the analog control levels of the level reading circuit 52, and the data voltage receiving terminals of the pixel circuits of the columns, respectively, and is used for controlling the communication between the data lines of the corresponding columns and the data voltage receiving terminals of the pixel circuits of the corresponding columns under the control of the analog control levels.

In fig. 5, a first column of data lines denoted by S1, a second column of data lines denoted by S2, a third column of data lines denoted by S3, a fourth hundred seventy-eight column of data lines denoted by S478, a fourth hundred seventy-nine column of data lines denoted by S479, and a fourth hundred eighty-column of data lines denoted by S480;

a first analog control level output terminal denoted by O1, a second analog control level output terminal denoted by O2, a third analog control level output terminal denoted by O3, a fourth hundred seventy-eight analog control level output terminal denoted by O478, a fourth hundred seventy-nine analog control level output terminal denoted by O479, and a fourth hundred eighty-analog control level output terminal denoted by O480;

the data voltage receiving terminal of the pixel circuit of the first column is marked with F1, the data voltage receiving terminal of the pixel circuit of the second column is marked with F2, the data voltage receiving terminal of the pixel circuit of the third column is marked with F3, the data voltage receiving terminal of the pixel circuit of the fourth hundred seventy-eight columns is marked with F478, the data voltage receiving terminal of the pixel circuit of the fourth hundred seventy-nine columns is marked with F479, and the data voltage receiving terminal of the pixel circuit of the fourth hundred eighty-eight columns is marked with F480.

In at least one embodiment of the present invention, the shift register may include N flip-flops that are sequentially cascaded; the trigger access of the trigger is connected with a trigger clock signal; the input end of the first trigger is connected with the data line gating control signal; n is an integer greater than 1;

In a specific implementation, the shift register may include a plurality of flip-flops sequentially cascaded, the plurality of flip-flops outputting a plurality of digital control levels according to the data line strobe control signal, and the level reading circuit reads the digital control levels from the non-inverting output terminals of the flip-flops.

Alternatively, the flip-flop may be a D flip-flop, a JK flip-flop, or other type of flip-flop. In at least one embodiment of the present invention, the flip-flop is exemplified as a D flip-flop.

In a specific implementation, the gating switch circuit may include a plurality of switch transistors, and the nth switch transistor may control on/off between the nth column data line and the data voltage receiving terminal of the nth column pixel circuit.

As shown in fig. 6, based on at least one embodiment of the gating circuit shown in fig. 5,

the shift register 51 may include 480D flip-flops cascaded in sequence; the trigger end of the D trigger is connected with a trigger clock signal X0; the input end of the first D trigger D1 is connected with the data line gating control signal X1;

the non-inverting output end of the first D trigger D1 is electrically connected with the input end of the second D trigger D2; the non-inverting output end of the first D trigger D1 is used for outputting a first digital control level;

The non-inverting output end of the second D trigger D2 is electrically connected with the input end of the third D trigger D3; the positive phase output end of the second D trigger D2 is used for outputting a second digital control level;

the non-inverting output of the third D flip-flop D3 is electrically connected to the input of a fourth D flip-flop (not shown in fig. 6); the non-inverting output end of the third D trigger D3 is used for outputting a third digital control level;

the non-inverting output of the fourth hundred seventy-eight D flip-flops D478 is electrically connected to the input of the fourth hundred seventy-nine D flip-flops D479; the non-inverting output end of the fourth hundred seventy-eight D flip-flops D478 is configured to output a fourth hundred seventy-eight digital control level;

the non-inverting output end of the fourth hundred seventy-nine D flip-flops D479 is electrically connected with the input end of the fourth hundred eighty-eight D flip-flops D480; the non-inverting output end of the fourth hundred seventy-nine D flip-flops D479 is used for outputting a fourth hundred seventy-nine digital control level;

the non-inverting output ends of the fourth hundred-eighty D flip-flops are used for outputting a fourth hundred-eighty digital control level;

the level reading circuit 52 is electrically connected to the positive output terminals of the 480D flip-flops, and is configured to read the digital control levels from the positive output terminals, convert the digital control levels into corresponding analog control levels, and provide a plurality of the analog control levels to the gate switch circuit 53.

In operation, at least one embodiment of the gating circuit shown in fig. 6, the data line gating control signal X1 sequentially shifts right in the shift register at each upward pulse of the trigger clock signal X0, for example, after passing 480 upward pulses of the trigger control signal X0, when the potential of the data line gating control signal is a high voltage at the first upward pulse of the trigger clock signal X0, the 480 th D flip-flop D480 outputs a digital control level corresponding to the high voltage through its non-inverting output terminal; when the potential of the data line strobe control signal is a low voltage at the second upward pulse of the trigger clock signal X0, the 479 th D flip-flop D479 outputs a digital control level corresponding to the low voltage through its non-inverting output terminal; when the potential of the data line gating control signal is high voltage in the third upward pulse of the trigger clock signal X0, the 478 th D trigger D478 outputs a digital control level corresponding to the high voltage through the non-inverting output terminal thereof; when the potential of the data line strobe control signal is a low voltage at the fourth hundred seventy-eight upward pulses of the trigger clock signal X0, the third D flip-flop D3 outputs a digital control level corresponding to the low voltage through its non-inverting output terminal; when the potential of the data line gating control signal is a high voltage at the fourth hundred seventy-nine upward pulses of the trigger clock signal X0, the second D flip-flop D2 outputs a digital control level corresponding to the high voltage through its non-inverting output terminal; when the potential of the data line gating control signal is a low voltage at the fourth hundred eighty upward pulses of the trigger clock signal X0, the first D flip-flop D1 outputs a digital control level corresponding to the low voltage through its non-inverting output terminal; and so on.

the gate switching circuit 53 includes N switching transistors; the control electrode of the nth switching transistor is electrically connected with the nth analog control level output end of the level reading circuit, the first electrode of the nth switching transistor is electrically connected with the nth column data line, and the second electrode of the nth switching transistor is electrically connected with the data voltage receiving end of the nth column pixel circuit.

In fig. 6, a first switching transistor denoted by T1 and included in the gate switching circuit 53, a second switching transistor denoted by T2 and included in the gate switching circuit 53, a third switching transistor denoted by T3 and included in the gate switching circuit 53, a fourth hundred seventy-eight switching transistor denoted by T478 and included in the gate switching circuit 53, a fourth hundred seventy-nine switching transistor denoted by T479 and included in the gate switching circuit 53, and a fourth hundred eighty-switching transistor denoted by T480 and included in the gate switching circuit 53;

the grid electrode of the T1 is electrically connected with the first analog control level output end O1, the source electrode of the T1 is electrically connected with the first column data line S1, and the drain electrode of the T1 is electrically connected with the data voltage receiving end F1 of the first column pixel circuit;

The grid electrode of the T2 is electrically connected with the second analog control level output end O2, the source electrode of the T2 is electrically connected with the second column data line S2, and the drain electrode of the T2 is electrically connected with the data voltage receiving end F2 of the second column pixel circuit;

the grid electrode of the T3 is electrically connected with the third analog control level output end O3, the source electrode of the T3 is electrically connected with the third column data line S3, and the drain electrode of the T3 is electrically connected with the data voltage receiving end F3 of the third column pixel circuit;

the grid electrode of the T478 is electrically connected with the fourth hundred seventy-eight analog control level output end O478, the source electrode of the T478 is electrically connected with the fourth hundred seventy-eight column data line S478, and the drain electrode of the T478 is electrically connected with the data voltage receiving end F478 of the fourth hundred seventy-eight column pixel circuit;

a gate of the T479 is electrically connected to the fourth hundred seventy-nine analog control level output terminal O479, a source of the T479 is electrically connected to the fourth hundred seventy-nine column data line S479, and a drain of the T479 is electrically connected to the data voltage receiving terminal F479 of the fourth hundred seventy-nine column pixel circuit;

the gate of the T480 is electrically connected to the fourth hundred-eighty analog control level output terminal O480, the source of the T480 is electrically connected to the fourth hundred-eighty column data line S480, and the drain of the T480 is electrically connected to the data voltage receiving terminal F480 of the fourth hundred-eighty column pixel circuit.

In at least one embodiment of the gating circuit shown in fig. 6, each of the switching transistors may be an n-type thin film transistor, but is not limited thereto.

At least one embodiment of the gating circuit shown in fig. 6 is operative in which each switching transistor may be turned on or off under control of each analog control level to control whether a data voltage is supplied to a corresponding column data line.

As shown in fig. 7, a pixel circuit and a gate driving circuit G1 are added on the basis of at least one embodiment of the gate circuit shown in fig. 6;

in fig. 7, a first row and first column pixel circuit denoted by reference numeral P11, a first row and second column pixel circuit denoted by reference numeral P12, a first row and third column pixel circuit denoted by reference numeral P13, a first row and fourth hundred seventy-eight column pixel circuit denoted by reference numerals P1 to 478, a first row and fourth hundred seventy-nine column pixel circuit denoted by reference numerals P1 to 479, and a first row and fourth hundred eighty-column pixel circuit denoted by reference numerals P1 to 480;

a first row and a first column of pixel circuits denoted by PA1, a second row and a second column of pixel circuits denoted by PA2, a third row and a fourth hundred seventy-eight column of pixel circuits denoted by PA3, a fourth row and seventy-nine column of pixel circuits denoted by PA-479, and a fourth row and eighty column of pixel circuits denoted by PA-480; a is an integer greater than 1;

P11 and PA1 are electrically connected with a data voltage receiving end F1 of the first column pixel circuit; p12 and PA2 are electrically connected with a data voltage receiving end F2 of the second column pixel circuit; p13 and PA3 are electrically connected to the data voltage receiving terminal F3 of the third column pixel circuit; p1-478 and PA-478 are electrically connected to a data voltage receiving terminal F478 of a fourth hundred seventy-eight column pixel circuit; p1-479 and PA-479 are all electrically connected to the data voltage receiving terminal F479 of the fourth hundred seventy-nine columns of pixel circuits; p1-480 and PA-480 are electrically connected with a data voltage receiving end F480 of a fourth hundred eighty columns of pixel circuits;

the gate drive circuit G1 is used for providing first row gate drive signals for P11, P12, P13, P1-478, P1-479, and P1-480, and for providing A-th row gate drive signals for PA1, PA2, PA3, PA-478, PA-479, and PA-480.

In at least one embodiment shown in fig. 7, the gate scanning module is the gate driving circuit G1, but not limited thereto.

In operation, at least one embodiment of the gating circuit shown in fig. 7 is operated, in the fused image output stage, the waveform G01 of the gate driving signal output by one row of gate lines and the waveform X11 of the data line gating control signal X1 are as shown in fig. 8;

In the high definition image output stage, the waveform G02 of the gate driving signal and the waveform X12 of the data line gate control signal X1 outputted from one row of gate lines are as shown in fig. 8;

alternatively, the data voltage supply circuit may include a conversion circuit, an output buffer circuit, and an output circuit;

In an implementation, the data voltage providing circuit may include a conversion circuit, an output buffer circuit, and an output circuit; the conversion circuit is used for converting high-definition image information into high-definition data voltage and converting low-definition image information into low-definition data voltage, wherein the high-definition image information and the low-definition image information can be digital signals, and the high-definition data voltage and the low-definition data voltage can be analog voltage signals; the output buffer circuit is used for buffering the high-definition data voltage and the low-definition data voltage, and the output circuit is used for controlling the high-definition data voltage or the low-definition data voltage to be provided to corresponding column data lines under the control of the data providing control signal.

As shown in fig. 9, at least one embodiment of the data voltage supply circuit may include a conversion circuit, an output buffer circuit 81, and an output circuit 82;

the output buffer circuit 81 is configured to buffer the high-definition data voltage and the low-definition data voltage;

the output circuit 82 is electrically connected to the output buffer circuit 81, the output circuit 82 is connected to a data providing control signal S0, and the output circuit 82 is configured to control providing a high-definition data voltage or a low-definition data voltage to a corresponding column data line under the control of the data providing control signal S0;

the output circuits 82 are also electrically connected to 480 column data lines, respectively;

in fig. 9, a first column of data lines denoted by S1, a second column of data lines denoted by S2, a third column of data lines denoted by S3, a fourth hundred seventy-eight column of data lines denoted by S478, a fourth hundred seventy-nine column of data lines denoted by S479, and a fourth hundred eighty-column of data lines denoted by S480;

the conversion circuit may include an input register 91, a data latch 92, a level shifter 93, and a digital-to-analog converter 94;

the input register 91 and the data latch 92 are used for temporarily storing image information and transmitting the image information to the level shifter 93; the image information comprises the low-definition image information and high-definition image information corresponding to a high-definition display area in the image information to be displayed;

The level shifter 93 is electrically connected to the data latch 92, and is configured to convert a 3.3V low voltage outputted from the data latch 92 into a high voltage of about 15V, so as to convert the image information into output image information; the output image information comprises output low-definition image information and output high-definition image information corresponding to a high-definition display area;

the digital-to-analog converter 94 is electrically connected to the level shifter 93, and the digital-to-analog converter 94 is configured to convert the output low-definition image information output by the level shifter 93 to obtain a low-definition data voltage, and is configured to convert the output high-definition image information output by the level shifter 93 to obtain a high-definition data voltage.

As shown in fig. 10, when the display control module according to at least one embodiment of the present invention works, firstly, image information and an eyeball image are obtained; then decoding the image information and the eyeball image; calculating gazing azimuth according to the decoded eyeball image, and caching decoded image information; then, according to the resolution and gazing direction information of the display panel, a high-definition area is calculated, and according to the calculated high-definition area, a grid line driving time sequence, a data line gating control signal and a data voltage providing control signal are generated, and low-definition processing is carried out on image information to be displayed (namely decoded image information) of other display areas except the high-definition display area of the display panel, so as to obtain low-definition image information; storing low-definition image information in a first buffer, storing high-definition image information in a second buffer, and storing fused image information (the fused image information comprises the low-definition image information and the high-definition image information corresponding to a high-definition display area) in a third buffer; converting the low-definition image information and the high-definition image information in the image information to be displayed to obtain low-definition data voltage and high-definition data voltage; in the fusion image output stage, all row grid lines included in the display panel are sequentially opened, and all column data lines included in the display panel respectively receive corresponding data voltages; and in the high-definition image output stage, the high-definition control grid line is opened, and the high-definition control data line receives high-definition data voltage.

The display control module according to at least one embodiment of the present invention may further include an eyeball image acquisition module, an image signal processing module, and an image information acquisition module;

the eyeball image acquisition module is used for acquiring eyeball images;

In an implementation, the eyeball image acquisition module may be a Camera sensor, but is not limited thereto.

The display control method of the embodiment of the invention is applied to the display control module, and comprises the following steps:

In specific implementation, the gaze point calculation module calculates a time period between two adjacent time points of different gaze location information as an adjustment time period according to the acquired eyeball image; the conditioning time period includes at least one conditioning phase; each adjusting stage comprises a fusion image output stage and a high-definition image output stage;

In at least one embodiment of the present invention, in the high-definition image output stage, the high-definition control gate lines are sequentially opened, so that only the pixel circuits in the high-definition area can receive new high-definition data voltages, and the refresh rate of the high-definition area is improved, so that the display area of the display panel except for the high-definition area still displays the original picture.

In at least one embodiment of the present invention, in the high-definition image output stage, the data voltage providing circuit only writes the high-definition data voltage into the high-definition control data line, so that only the pixel circuits in the high-definition area can receive the new high-definition data voltage, and the display area of the display panel except the high-definition area still displays the original picture.

In at least one embodiment of the present invention, in the high-definition image output stage, the gate circuit controls the communication between the high-definition control data line and the data voltage receiving terminals of the pixel circuits in the corresponding columns, so that only the pixel circuits in the high-definition area can receive the new high-definition data voltage, and the display area of the display panel except the high-definition area still displays the original picture.

The display device provided by the embodiment of the invention comprises the display control module.

The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the present invention.

Claims

1. The display control module is applied to a display device, and the display device comprises a display panel and a grid scanning module, wherein the display panel comprises a plurality of rows and columns of pixel circuits, a plurality of rows of grid lines and a plurality of columns of data lines; the display control module is characterized by comprising a fixation point calculation module, a high-definition display area calculation module, an image low-definition processing module, a time sequence control module, a grid scanning module, a data voltage supply circuit and a gating circuit;

The gating circuit is used for controlling the communication between the corresponding column data line and the data voltage receiving end of the corresponding column pixel circuit according to the data line gating control signal so as to provide data voltage for the corresponding column pixel circuit through the corresponding column data line;

the fixation point calculating module calculates a time period between two adjacent time points of different fixation position information as an adjusting time period according to the acquired eyeball image; the conditioning time period includes at least one conditioning phase; each adjusting stage comprises a fusion image output stage and a high-definition image output stage;

the grid scanning module is used for providing grid driving signals for grid lines included in the display panel according to the grid scanning time sequence in the fused image output stage so as to control the grid lines included in the display panel to be opened in sequence, and is also used for providing corresponding grid driving signals for high-definition control grid lines according to the grid scanning time sequence in the high-definition image output stage so as to control the high-definition control grid lines to be opened in sequence;

2. The display control module of claim 1, further comprising a data decoding module;

the image information to be displayed is the decoded image information.

3. The display control module of claim 2, further comprising a processor and a data driving module; the data voltage supply circuit and the gate circuit are included in the data driving module;

the processor, the data decoding module, the gaze point calculation module, the high-definition display area calculation module, the image low-definition processing module, the time sequence control module, the grid scanning module and the data driving module are connected through buses;

4. The display control module of claim 3, wherein the processor, the data decoding module, the gaze point calculation module, the high definition display area calculation module, the image low definition processing module, the timing control module, the gate scan module, and the data driving module are all included in a display driving integrated circuit;

5. The display control module according to any one of claims 1 to 4, wherein the gate circuit includes a shift register, a level reading circuit, and a gate switching circuit;

6. The display control module of claim 5, wherein the shift register comprises N flip-flops that are cascaded in sequence; the trigger access of the trigger is connected with a trigger clock signal; the input end of the first trigger is connected with the data line gating control signal; n is an integer greater than 1;

7. The display control module of claim 5, wherein the gating switching circuit comprises N switching transistors; n is an integer greater than 1; n is a positive integer, and n+1 is less than or equal to N;

8. The display control module according to any one of claims 1 to 4, wherein the data voltage supply circuit includes a conversion circuit, an output buffer circuit, and an output circuit;

9. The display control module according to any one of claims 2 to 4, further comprising an eyeball image acquisition module, an image signal processing module, and an image information acquisition module;

the eyeball image acquisition module is used for acquiring eyeball images;

10. A display control method applied to the display control module according to any one of claims 1 to 9, characterized in that the display control method comprises:

the gating circuit controls the communication between the corresponding column data line and the data voltage receiving end of the corresponding column pixel circuit according to the data line gating control signal so as to provide data voltage for the corresponding column pixel circuit through the corresponding column data line;

11. The display control method according to claim 10, wherein the gaze point calculation module calculates a time period between two adjacent time points of different gaze location information from the acquired eyeball image as the adjustment time period; the conditioning time period includes at least one conditioning phase; each adjusting stage comprises a fusion image output stage and a high-definition image output stage;

12. The display control method according to claim 10, wherein the gaze point calculation module calculates a time period between two adjacent time points of different gaze location information from the acquired eyeball image as the adjustment time period; the conditioning time period includes at least one conditioning phase; each adjusting stage comprises a fusion image output stage and a high-definition image output stage;

13. A display device comprising a display control module according to any one of claims 1 to 9.