CN114284390B - Vertical incidence ultra-wideband integrated photoelectric detector chip and manufacturing method thereof - Google Patents
Vertical incidence ultra-wideband integrated photoelectric detector chip and manufacturing method thereof Download PDFInfo
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Abstract
The invention relates to a vertical incidence ultra-wideband integrated photoelectric detector chip and a manufacturing method thereof, comprising the following steps: manufacturing a capacitor lower electrode and a bias network transmission line on a carrier; manufacturing a capacitor dielectric layer; forming a matching resistor, an impedance matching network transmission line and a capacitor upper electrode on the capacitor dielectric layer; forming metal bumps; manufacturing a micro lens on a substrate on the back of a diode chip; the diode chip is soldered to the carrier by flip-chip bonding. In the invention, the control of parasitic parameters is realized through the monolithic integration of the bias network and the impedance matching network, and the bandwidth of the detector is improved; coupling redundancy and responsiveness are improved by integrating micro lenses on the back surface, and the influence of polarization loss is avoided; all indexes can reach or exceed the performance index level of the currently mainstream waveguide type detector, and the method has positive significance for the design and manufacture of ultra-wideband photoelectric detectors.
Description
Technical Field
The invention belongs to the technical field of semiconductor photodiodes, and relates to a vertical incidence ultra-wideband integrated photoelectric detector chip and a manufacturing method thereof.
Background
In fiber optic communication systems, photodetector chips are used to convert information-carrying optical signals into information-carrying electrical signals for subsequent circuitry to process the information. The incident light modes can be classified into a vertical incidence type and a side-illuminated type.
With the continuous improvement of the requirements of high-speed optical fiber communication systems, ultra-fast pulse measurement, millimeter wave systems, THz technology and the like on the speed of photoelectric detector chips (more than or equal to 50 GHz), in order to solve the problem of mutual restriction between speed and efficiency, all high-speed detectors above 50GHz at present adopt a side incidence and evanescent wave coupling mode, and the indexes of the high-speed detectors can reach the level that the bandwidth is more than or equal to 67GHz and the responsivity is more than or equal to 0.6A/W. However, compared with the conventional P-I-N type photoelectric detector with vertical incidence, the side incidence type photoelectric detector has the advantages of complex manufacturing process, high difficulty, low optical fiber coupling efficiency, high polarization influence and high manufacturing cost. On the other hand, the side-incident structure does not allow a two-dimensional detector array, thereby limiting the application space of the photodiode chip.
The vertical incidence P-I-N type photoelectric detector is the simplest and reliable detector structure, but the detector is difficult to simultaneously combine high efficiency and high bandwidth. How to manufacture a high-performance detector by using a simple structure and a manufacturing process is a basis for further optimizing the detector and is a requirement for more practical development. The performance of a detector chip of a conventional normal incidence structure is limited by several factors, and the requirements of high speed, high responsivity and high saturation cannot be met at the same time:
1) Bandwidth: discrete elements such as capacitors and resistors bring larger parasitic parameters to affect the bandwidth of the device.
2) Responsivity: ultra-high speed detectors require very small active areas, typically less than or equal to 10 μm in diameter, less than the diameter of the optical spot (16 μm) of the outgoing light from the fiber, and therefore cannot achieve complete coupling, resulting in lower chip responsivity.
3) Saturated optical power: the active area is very small, the dissipated power is very large (hundreds of milliwatts), and thermal failure of the chip is easily caused.
Disclosure of Invention
In view of the above, the present invention aims to solve the problems of complex process, high difficulty, low optical fiber coupling efficiency, high polarization influence, and poor bandwidth, responsivity, saturated light power and other performances of the vertical incidence ultra-wideband integrated photoelectric detector chip for solving the defects of the prior high-speed photoelectric detector in practical application, and provides a vertical incidence ultra-wideband integrated photoelectric detector chip and a manufacturing method thereof.
In order to achieve the above purpose, the present invention provides the following technical solutions:
a manufacturing method of a vertical incidence ultra-wideband integrated photoelectric detector chip comprises the following steps:
s1, manufacturing two capacitance lower electrodes on a carrier, and forming a first bias network transmission line and a second bias network transmission line at two ends of each capacitance lower electrode respectively;
s2, manufacturing a capacitance medium layer on the carrier;
s3, defining a first contact hole at the position of the capacitor medium layer corresponding to each first bias network transmission line through a photoetching process, and defining a second contact hole at the position of the capacitor medium layer corresponding to each second bias network transmission line through a photoetching process;
s4, forming a matching resistor, an impedance matching network transmission line and two capacitor upper electrodes on the capacitor dielectric layer; the matching resistor is respectively connected with the upper electrodes of the two capacitors through an impedance matching network transmission line;
s5, thinning and polishing the carrier to 100-150 mu m;
s6, forming a first metal bump connected with the matching resistor and a second metal bump connected with the first bias network transmission line through the first contact hole;
s7, manufacturing a micro lens corresponding to the active area of the diode chip on the substrate on the back of the diode chip;
and S8, welding the diode chip on the carrier in a flip-chip welding mode, so that the first metal bump is welded and connected with the P electrode of the diode chip, and the second metal bump is welded and connected with the N electrode of the diode chip.
Further, the carrier material is silicon carbide, aluminum nitride, diamond or graphene.
Further, the step S1 includes:
s101, taking a carrier, and depositing the thickness of the carrier by a plasma enhanced chemical vapor deposition methodThe SiNx dielectric film of (2) is used as a dielectric film layer;
s102, evaporating or sputtering by adopting a stripping process to form two capacitance lower electrodes on the dielectric film layer, forming a first bias network transmission line protruding inwards at one end of each capacitance lower electrode, and forming a second bias network transmission line protruding outwards at the other end of each capacitance lower electrode.
Further, in the step S2, PECVD is performed to deposit the carrier with a thickness ofThe silicon nitride SiNx dielectric film is used as a capacitance dielectric layer, and the capacitance dielectric layer covers the capacitance lower electrode, the first bias network transmission line and the second bias network transmission line.
Further, the step S4 includes:
s401, evaporating or sputtering by adopting a stripping process to form a matching resistor on the capacitance dielectric layer;
s402, respectively forming an impedance matching network transmission line and two capacitor upper electrodes by adopting an electroplating process, wherein the two capacitor upper electrodes are respectively positioned above the two capacitor lower electrodes; the impedance matching network transmission line comprises a first impedance matching network transmission line and two second impedance matching network transmission lines symmetrically arranged on two sides of the first impedance matching network transmission line, one end of the first impedance matching network transmission line is connected with the middle of the matching resistor and then stretches into the space between the two first contact holes, the two second impedance matching network transmission lines are respectively connected with one end of the matching resistor, and the two second impedance matching network transmission lines are also respectively connected with an upper electrode of a capacitor.
Further, the step S7 includes:
s71, taking a wafer with a diode chip; thinning and polishing the wafer to 100-200 mu m by adopting a chemical mechanical polishing mode;
s72, defining a micro-lens position on the back surface of the diode chip by adopting a double-sided photoetching mode, so that the micro-lens position is aligned with the active area position of the diode chip;
s73, defining the shape of the micro lens by using a photoetching process, and transferring the shape of the micro lens to a substrate on the back of the diode chip by adopting dry etching;
s74, depositing SiNx, siO2 or SiNxOy on the diode chip by adopting plasma enhanced chemical vapor deposition PECVD as an anti-reflection film;
and S75, dicing the wafer to form single diode chips.
Further, the microlens is a diffraction microlens or a refraction microlens.
The vertical incidence ultra-wideband integrated photoelectric detector chip comprises a carrier and a diode chip which are connected in a flip-chip mode, wherein a dielectric film layer is arranged on the carrier, two capacitance lower electrodes are symmetrically arranged on the dielectric film layer, one end of each capacitance lower electrode is respectively provided with a first bias network transmission line protruding inwards, the other end of each capacitance lower electrode is respectively provided with a second bias network transmission line protruding outwards, and the capacitance lower electrodes, the first bias network transmission lines and the second bias network transmission lines are covered with a capacitance dielectric layer; the capacitor comprises a capacitor dielectric layer, a first bias network transmission line, a second bias network transmission line, a capacitor upper electrode, a matching resistor, a first impedance matching network transmission line, a second impedance matching network transmission line and a second impedance matching network transmission line, wherein the capacitor dielectric layer is provided with a first contact hole corresponding to the position of each first bias network transmission line, a second contact hole corresponding to the position of each second bias network transmission line is respectively arranged in each first contact hole, a second metal bump is respectively arranged in each first contact hole, a capacitor upper electrode is respectively arranged at the position, corresponding to the upper part of each capacitor lower electrode, of the capacitor dielectric layer, one side of the capacitor upper electrode is provided with the matching resistor, the middle part of the matching resistor is connected with the first impedance matching network transmission line, the first impedance matching network transmission line is provided with the first metal bumps, two ends of the matching resistor are respectively connected with the second impedance matching network transmission lines, and the two second impedance matching network transmission lines are respectively connected with the capacitor upper electrode; and a micro lens corresponding to the diode chip active region is manufactured on the substrate on the back of the diode chip, the P electrode of the diode chip is connected with the first metal convex point in a welded manner, and the N electrode of the diode chip is connected with the second metal convex point in a welded manner.
Further, the carrier material is silicon carbide, aluminum nitride, diamond or graphene.
Further, the dielectric film layer is of a thicknessThe SiNx dielectric film of (2) is the thickness of the capacitance dielectric layer>Silicon nitride SiNx dielectric film.
In the invention, the control of parasitic parameters is realized and the bandwidth of the detector is improved through the monolithic integration of the bias network and the impedance matching network; coupling redundancy and responsiveness are improved by integrating micro lenses on the back surface, and the influence of polarization loss is avoided; the heat dissipation of the chip is enhanced by the flip-chip bonding mode, so that large saturated light power is realized, and various indexes can reach or exceed the performance index level of the current mainstream waveguide type detector. The invention adopts a simple vertical incidence structure to manufacture the high-performance photoelectric detector, exploits a new design thought of the high-speed photoelectric detector, and has positive significance for the design and manufacture of the ultra-wideband photoelectric detector; the method can be widely applied to the structural design of backside-Intrinsic-Negative (PIN) and avalanche photodiodes (Avalanche Photo Diode, APD).
Drawings
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in the following preferred detail with reference to the accompanying drawings, in which:
FIG. 1 is a flow chart of a method for fabricating a vertical incidence ultra wideband integrated photodetector chip according to a preferred embodiment of the present invention.
Fig. 2 is a schematic diagram of the capacitor bottom electrode and bias network transmission line fabricated on the carrier.
Fig. 3 is a schematic view of fig. 2 after the first contact hole and the second contact hole are opened.
Fig. 4 is a schematic diagram of the carrier after forming a matching resistor on the capacitive dielectric layer.
Fig. 5 is a schematic diagram of the carrier after forming the impedance matching network transmission line and the upper electrode of the capacitor.
Fig. 6 is a schematic view of the carrier after the first metal bump, the second metal bump and the fifth metal bump are fabricated.
Fig. 7 is a front view of the carrier after the first, second and fifth metal bumps are fabricated.
Fig. 8 is a schematic diagram of a micro-lens fabricated on a substrate on the back side of a diode chip.
Fig. 9 is a schematic diagram of a carrier and diode chip prior to flip-chip bonding.
Fig. 10 is a schematic diagram of the carrier and diode chip after flip-chip bonding.
In the figure: 100. the semiconductor device comprises a carrier, 110, a dielectric film layer, 120, a capacitor lower electrode, 121, a first bias network transmission line, 122, a second bias network transmission line, 130, a capacitor dielectric layer, 131, a first contact hole, 132, a second contact hole, 140, a matching resistor, 150, a capacitor upper electrode, 151, a first impedance matching network transmission line, 152, a second impedance matching network transmission line, 161, a first metal bump, 162, a second metal bump, 163, a third metal bump, 200, a diode chip, 201, a fourth metal bump and 210, and a microlens.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the illustrations provided in the following embodiments merely illustrate the basic idea of the present invention by way of illustration, and the following embodiments and features in the embodiments may be combined with each other without conflict.
As shown in fig. 1, a preferred embodiment of the method for manufacturing a vertical incidence ultra wideband integrated photodetector chip of the present invention comprises the steps of:
as shown in fig. 1, a preferred embodiment of the method for manufacturing a vertical incidence ultra wideband integrated photodetector chip of the present invention comprises the steps of:
s1, as shown in fig. 2, two capacitor bottom electrodes 120 are fabricated on the carrier 100, and a first bias network transmission line 121 and a second bias network transmission line 122 are respectively formed at two ends of each capacitor bottom electrode 120, where the capacitor bottom electrodes 120, the first bias network transmission line 121 and the second bias network transmission line 122 form a bias network. The material of the carrier 100 is preferably silicon carbide, aluminum nitride, diamond or graphene. This step may include the sub-steps of:
s101, taking a carrier 100, and depositing the carrier 100 with the thickness ofAs the dielectric film layer 110;
s102, two capacitance lower electrodes 120 are formed on the dielectric film layer 110 by adopting stripping process evaporation or sputtering, a first bias network transmission line 121 protruding inwards is formed at one end of each capacitance lower electrode 120, and a second bias network transmission line 122 protruding outwards is formed at the other end of each capacitance lower electrode 120. The materials used for the capacitor bottom electrode 120, the first bias network transmission line 121 and the second bias network transmission line 122 are titanium, platinum, chromium, gold, titanium alloy, platinum alloy, chromium alloy or gold alloy. The materials of the capacitor bottom electrode 120, the first bias network transmission line 121 and the second bias network transmission line 122 in this embodiment are preferably titanium/platinum/gold, and the thickness is preferably
S2, manufacturing a capacitance medium layer 130 on the carrier 100. The specific method comprises the following steps:
deposition of thickness on carrier 100 by plasma enhanced chemical vapor deposition PECVD The silicon nitride SiNx dielectric film is used as the capacitance dielectric layer 130, and the capacitance dielectric layer 130 covers the capacitance lower electrode 120, the first bias network transmission line 121 and the second bias network transmission line 122. The thickness of the capacitance dielectric layer 130 in this embodiment is preferably
S3, as shown in FIG. 3, first contact holes 131 are defined on the capacitive medium layer 130 at positions corresponding to each first bias network transmission line 121 through a photolithography process, and the positions of the two first contact holes 131 correspond to the positions of the two N poles of the diode chip 200; the second contact holes 132 are defined by photolithography at positions corresponding to each of the second bias network transmission lines 122.
S4, forming a matching resistor 140, an impedance matching network transmission line and two capacitor upper electrodes 150 on the capacitor dielectric layer 130; the matching resistor 140 is connected to the two upper capacitor electrodes 150 through impedance matching network transmission lines. This step may include the sub-steps of:
s401, as shown in FIG. 4, a stripping process is adopted to evaporate or sputter to form a matching resistor 140 on the capacitance medium layer 130; the material of the matching resistor 140 is preferably titanium, chromium, nickel, a titanium alloy, a chromium alloy, a nickel alloy, or a silicon alloy. The matching resistor 140 material in this embodiment is preferably CrSi, and the thickness is preferably
As shown in fig. 5, an impedance matching network transmission line and two capacitor upper electrodes 150 are formed by electroplating, and the two capacitor upper electrodes 150 are respectively located above the two capacitor lower electrodes 120. The materials used for the impedance matching network transmission line and the two upper capacitor electrodes 150 are gold, copper, tin, gold alloy, copper alloy, tin alloy, etc. In this embodiment, the material used for the impedance matching network transmission line and the two upper capacitor electrodes 150 is preferably Au, and the thickness of the impedance matching network transmission line and the two upper capacitor electrodes 150 is preferably 1 μm to 2.5 μm.
Before the electroplating process of the step is carried out, an electron beam, thermal evaporation or sputtering process can be adopted to form a metal seed layer for electroplating, wherein the material of the metal seed layer is chromium, gold, nickel, chromium alloy, gold alloy or nickel alloy; the material of the metal seed layer in this embodiment is preferably CrAu, and the thickness is preferably And (3) after the electroplating process of the step S6, removing the exposed part of the metal seed layer.
The impedance matching network transmission line comprises a first impedance matching network transmission line 151 and two second impedance matching network transmission lines 152 symmetrically arranged at two sides of the first impedance matching network transmission line 151, one end of the first impedance matching network transmission line 151 is connected with the middle part of the matching resistor 140 and then extends into between the two first contact holes 131, the two second impedance matching network transmission lines 152 are respectively connected with one end of the matching resistor 140, and the two second impedance matching network transmission lines 152 are respectively connected with a capacitor upper electrode 150. The matching resistor 140, the first impedance matching network transmission line 151, and the two second impedance matching network transmission lines 152 form an impedance matching network.
S5, thinning and polishing the carrier 100 to 100-150 mu m by adopting a chemical mechanical polishing mode.
S6, as shown in FIG. 6 and FIG. 7, forming a first metal bump 161 connected with the matching resistor 140 and a second metal bump 162 connected with the first bias network transmission line 121 through the first contact hole 131 by adopting an electroplating process again; the first metal bump 161 is preferably disposed at an end of the first impedance matching network transmission line 151 extending between the two first contact holes 131, so that the first metal bump 161 is located between the two second metal bumps 162, and the position of the first metal bump 161 corresponds to the position of the P-pole of the diode chip 200.
A plurality of third metal bumps 163 are also formed by electroplating in this embodiment to increase the bonding pads for flip-chip bonding. The materials used for the first metal bump 161, the second metal bump 162 and the third metal bump 163 are gold, copper, tin, gold alloy, copper alloy, tin alloy, etc. The materials used for the first, second and third metal bumps 161, 162 and 163 in this embodiment are preferably Au, and the thickness is preferably 5 μm to 10 μm.
At this time, a fourth metal bump 201 may be formed on the diode chip 200 at a position corresponding to each third metal bump 163, so as to facilitate flip-chip connection. The fourth metal bump 201 is made of gold, copper, tin, gold alloy, copper alloy, tin alloy, etc., preferably Au, and has a thickness of preferably 5 μm to 10 μm.
S7, as shown in FIG. 8, a microlens 210 corresponding to the active region of the diode chip 200 is manufactured on the substrate on the back surface of the diode chip 200; the diode chip 200 is a vertical incidence type high-speed photodiode chip 200, and the structure thereof is a prior art and will not be described herein. This step may include the sub-steps of:
s71, taking a wafer with the diode chip 200; and thinning and polishing the wafer to 100-200 μm by adopting a chemical mechanical polishing mode.
S72, defining the position of the micro lens 210 on the back surface of the diode chip 200 by adopting a double-sided photoetching mode, so that the position of the micro lens 210 is strictly aligned with the position of an active region of the diode chip 200, and the error is less than 1 mu m.
S73, defining the shape of the micro lens 210 by a photoetching process, wherein the types of the micro lens 210 comprise a diffraction type micro lens 210 and a refraction type micro lens 210, and transferring the shape of the micro lens 210 to a substrate on the back surface of the diode chip 200 by dry etching. In this embodiment, refractive microlenses 210 are preferably used, and the diameter of the microlenses 210 is 50 μm to 80 μm and the height is 3 μm to 10. Mu.m.
S74, depositing SiNx, siO2 or SiNxOy on the diode chip 200 by adopting plasma enhanced chemical vapor deposition PECVD as an anti-reflection film. In this embodiment, siNx is preferably deposited as an anti-reflection film by PECVD.
And S75, scribing the wafer through scribing lines to form the single diode chip 200.
S8, as shown in fig. 9 and 10, the diode chip 200 is soldered to the carrier 100 by flip-chip bonding, the first metal bump 161 is soldered to the P-electrode of the diode chip 200, and the second metal bump 162 is soldered to the N-electrode of the diode chip 200. When the third metal bump 163 is provided on the carrier 100 and the fourth metal bump 201 is provided on the diode chip 200, the third metal bump 163 and the fourth metal bump 201 at corresponding positions are also soldered.
In the embodiment, the control of parasitic parameters is realized through the monolithic integration of the bias network and the impedance matching network, and the bandwidth of the detector is improved (the bandwidth of the photoelectric detector chip of the embodiment can reach 70 GHz); coupling redundancy and responsiveness are improved by integrating the micro lenses 210 on the back surface, and the influence of polarization loss is avoided; the heat dissipation of the chip is enhanced by the flip-chip bonding mode, so that large saturated light power is realized, and various indexes can reach or exceed the performance index level of the current mainstream waveguide type detector. The embodiment adopts a simple vertical incidence structure to manufacture the high-performance photoelectric detector, exploits a new design thought of the high-speed photoelectric detector, and has positive significance for the design and manufacture of the ultra-wideband photoelectric detector; the method can be widely applied to the structural design of backside-Intrinsic-Negative (PIN) and avalanche photodiodes (Avalanche Photo Dio de, APD).
As shown in fig. 9 and 10, a preferred embodiment of the vertical incidence ultra wideband integrated photodetector chip of the present invention includes a carrier 100 and a diode chip 200 connected by flip-chip bonding; as shown in fig. 6 and 7, the carrier 100 is preferably silicon carbide, aluminum nitride, diamond or graphene. The carrier 100 is provided with a dielectric film layer 110, and the dielectric film layer 110 preferably has a thicknessIs a SiNx dielectric film; two capacitor bottom electrodes 120 are symmetrically arranged on the dielectric film layer 110, one end of each capacitor bottom electrode 120 is respectively formed with a first bias network transmission line 121 protruding inwards, the other end of each capacitor bottom electrode 120 is respectively formed with a second bias network transmission line 122 protruding outwards, the materials of the capacitor bottom electrode 120, the first bias network transmission line 121 and the second bias network transmission line 122 are preferably titanium/platinum/gold, and the thickness is preferably->The capacitor bottom electrode 120, the first bias network transmission line 121 and the second bias network transmission line 122 are covered with a capacitor dielectric layer 130, and the capacitor dielectric layer 130 is preferably a thickness +.>Silicon nitride SiNx dielectric film. The capacitor dielectric layer 130 is provided with first contact holes 131 corresponding to the positions of the first bias network transmission lines 121, second contact holes 132 corresponding to the positions of the second bias network transmission lines 122, and a second metal bump 162 is respectively arranged in each first contact hole 131, wherein the material used for the second metal bump 162 is preferably Au, and the thickness is preferably 5 μm-10 μm. A capacitor upper electrode 150 is disposed on the capacitor dielectric layer 130 at a position corresponding to the upper portion of each capacitor lower electrode 120, a matching resistor 140 is disposed on one side of the capacitor upper electrode 150, the matching resistor 140 is preferably CrSi, and the thickness is preferably +.>The middle part of the matching resistor 140 is connected with a first impedance matching network transmission line 151, the first impedance matching network transmission line 151 is provided with a first metal bump 161, two ends of the matching resistor 140 are respectively connected with a second impedance matching network transmission line 152, and two second impedance matching network transmission lines 152 are respectively connected with oneThe capacitor upper electrode 150 is connected; the first impedance matching network transmission line 151 and the two second impedance matching network transmission lines 152 are used for connecting a radio frequency output end; the material used for the impedance matching network transmission line and the two upper capacitor electrodes 150 is preferably Au, and the thickness is preferably 1 μm to 2.5 μm.
The diode chip 200 is a vertical incidence type high-speed photodiode chip 200, a P-electrode of the diode chip 200 is welded to the first metal bump 161, and an N-electrode of the diode chip 200 is welded to the second metal bump 162. The diode chip 200 is provided with a fourth metal bump 201 corresponding to each third metal bump 163; the third metal bump 163 and the fourth metal bump 201 at the corresponding positions are soldered. As shown in fig. 8, a microlens 210 corresponding to an active region of the diode chip 200 is formed on a substrate on the back surface of the diode chip 200. In this embodiment, refractive microlenses 210 are preferably used, and the diameter of the microlenses 210 is 50 μm to 80 μm and the height is 3 μm to 10. Mu.m. SiNx is deposited as an anti-reflection film on the diode chip 200.
In this embodiment, the carrier 100 of the monolithically integrated impedance matching network and bias network and the normally incident high speed photodiode chip 200 of the monolithically integrated microlens 210 are mixedly integrated by flip chip bonding. Parasitic parameters can be reduced and controlled, the bandwidth of the detector is improved, and the high-performance photoelectric detector is manufactured by adopting a simple vertical incidence structure, and various indexes can reach or exceed the performance index level of the currently mainstream waveguide type detector.
Finally, it is noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the present invention, which is intended to be covered by the claims of the present invention.
Claims (8)
1. The manufacturing method of the vertical incidence ultra-wideband integrated photoelectric detector chip is characterized by comprising the following steps of:
s1, manufacturing two capacitance lower electrodes on a carrier, and forming a first bias network transmission line and a second bias network transmission line at two ends of each capacitance lower electrode respectively; the carrier material is silicon carbide, aluminum nitride, diamond or graphene;
s2, manufacturing a capacitance medium layer on the carrier;
s3, defining a first contact hole at the position of the capacitor medium layer corresponding to each first bias network transmission line through a photoetching process, and defining a second contact hole at the position of the capacitor medium layer corresponding to each second bias network transmission line through a photoetching process;
s4, forming a matching resistor, an impedance matching network transmission line and two capacitor upper electrodes on the capacitor dielectric layer; the matching resistor is respectively connected with the upper electrodes of the two capacitors through an impedance matching network transmission line;
s5, thinning and polishing the carrier to 100-150 mu m;
s6, forming a first metal bump connected with the matching resistor and a second metal bump connected with the first bias network transmission line through the first contact hole;
s7, manufacturing a micro lens corresponding to the active area of the diode chip on the substrate on the back of the diode chip;
and S8, welding the diode chip on the carrier in a flip-chip welding mode, so that the first metal bump is welded and connected with the P electrode of the diode chip, and the second metal bump is welded and connected with the N electrode of the diode chip.
2. The method for manufacturing a normally incident ultra-wideband integrated photodetector chip of claim 1, wherein said S1 step comprises:
s101, taking a carrier, and depositing the thickness of the carrier by a plasma enhanced chemical vapor deposition methodThe SiNx dielectric film of (2) is used as a dielectric film layer;
s102, evaporating or sputtering by adopting a stripping process to form two capacitance lower electrodes on the dielectric film layer, forming a first bias network transmission line protruding inwards at one end of each capacitance lower electrode, and forming a second bias network transmission line protruding outwards at the other end of each capacitance lower electrode.
3. The method of fabricating a normally incident ultra wideband integrated photodetector chip as defined in claim 1, wherein in said step S2, a thickness of a carrier is deposited by plasma enhanced chemical vapor deposition PECVDThe silicon nitride SiNx dielectric film is used as a capacitance dielectric layer, and the capacitance dielectric layer covers the capacitance lower electrode, the first bias network transmission line and the second bias network transmission line.
4. The method for manufacturing a normally incident ultra-wideband integrated photodetector chip of claim 1, wherein said step S4 comprises:
s401, evaporating or sputtering by adopting a stripping process to form a matching resistor on the capacitance dielectric layer;
s402, respectively forming an impedance matching network transmission line and two capacitor upper electrodes by adopting an electroplating process, wherein the two capacitor upper electrodes are respectively positioned above the two capacitor lower electrodes; the impedance matching network transmission line comprises a first impedance matching network transmission line and two second impedance matching network transmission lines symmetrically arranged on two sides of the first impedance matching network transmission line, one end of the first impedance matching network transmission line is connected with the middle of the matching resistor and then stretches into the space between the two first contact holes, the two second impedance matching network transmission lines are respectively connected with one end of the matching resistor, and the two second impedance matching network transmission lines are also respectively connected with an upper electrode of a capacitor.
5. The method for manufacturing a normally incident ultra-wideband integrated photodetector chip of claim 1, wherein said step S7 comprises:
s71, taking a wafer with a diode chip; thinning and polishing the wafer to 100-200 mu m by adopting a chemical mechanical polishing mode;
s72, defining a micro-lens position on the back surface of the diode chip by adopting a double-sided photoetching mode, so that the micro-lens position is aligned with the active area position of the diode chip;
s73, defining the shape of the micro lens by using a photoetching process, and transferring the shape of the micro lens to a substrate on the back of the diode chip by adopting dry etching;
s74, depositing SiNx, siO2 or SiNxOy on the diode chip by adopting plasma enhanced chemical vapor deposition PECVD as an anti-reflection film;
and S75, dicing the wafer to form single diode chips.
6. The method of manufacturing a normally incident ultra-wideband integrated photodetector chip of claim 5, wherein said microlenses are diffractive or refractive microlenses.
7. The vertical incidence ultra-wideband integrated photoelectric detector chip is characterized by comprising a carrier and a diode chip which are connected in a flip-chip mode, wherein the carrier is made of silicon carbide, aluminum nitride, diamond or graphene; the carrier is provided with a dielectric film layer, two capacitance lower electrodes are symmetrically arranged on the dielectric film layer, one end of each capacitance lower electrode is respectively provided with a first bias network transmission line protruding inwards, the other end of each capacitance lower electrode is respectively provided with a second bias network transmission line protruding outwards, and the capacitance lower electrodes, the first bias network transmission lines and the second bias network transmission lines are covered with capacitance dielectric layers; the capacitor comprises a capacitor dielectric layer, a first bias network transmission line, a second bias network transmission line, a capacitor upper electrode, a matching resistor, a first impedance matching network transmission line, a second impedance matching network transmission line and a second impedance matching network transmission line, wherein the capacitor dielectric layer is provided with a first contact hole corresponding to the position of each first bias network transmission line, a second contact hole corresponding to the position of each second bias network transmission line is respectively arranged in each first contact hole, a second metal bump is respectively arranged in each first contact hole, a capacitor upper electrode is respectively arranged at the position, corresponding to the upper part of each capacitor lower electrode, of the capacitor dielectric layer, one side of the capacitor upper electrode is provided with the matching resistor, the middle part of the matching resistor is connected with the first impedance matching network transmission line, the first impedance matching network transmission line is provided with the first metal bumps, two ends of the matching resistor are respectively connected with the second impedance matching network transmission lines, and the two second impedance matching network transmission lines are respectively connected with the capacitor upper electrode; and a micro lens corresponding to the diode chip active region is manufactured on the substrate on the back of the diode chip, the P electrode of the diode chip is connected with the first metal convex point in a welded manner, and the N electrode of the diode chip is connected with the second metal convex point in a welded manner.
8. The normally-incident ultra-wideband integrated photodetector chip of claim 7, wherein said dielectric film layer has a thickness ofThe SiNx dielectric film of (2) is the thickness of the capacitance dielectric layer>Silicon nitride SiNx dielectric film.
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