CN114242776A - LDMOS structure and preparation method thereof - Google Patents
LDMOS structure and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000002347 injection Methods 0.000 claims description 25
- 239000007924 injection Substances 0.000 claims description 25
- 239000007943 implant Substances 0.000 claims description 16
- 238000005468 ion implantation Methods 0.000 claims description 14
- 238000002513 implantation Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
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- 239000000463 material Substances 0.000 abstract description 2
- 230000000295 complement effect Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000005034 decoration Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 206010063385 Intellectualisation Diseases 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
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Abstract
The invention discloses an LDMOS structure and a preparation method thereof.A substrate is provided with a lightly doped epitaxial layer, the lightly doped epitaxial layer is provided with a well region with an A conductive type and a well region with a B conductive type, and a gap is arranged between the well region and the well region; the spacing avoids the situation that the doping concentration of the deep junction is lower than that of the drain region, thereby improving the breakdown voltage. The well region of the B conduction type is provided with an STI structure, and the grid electrode of the LDMOS crosses over the well region of the A conduction type, the well region of the B conduction type and part of the STI structure; the grid electrode is divided into four regions along the crossing direction, and materials doped with different conduction types are respectively injected into the four regions, so that the breakdown voltage of the device is increased, the accidental conduction of current is inhibited, and the reliability of the device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to an LDMOS (laterally-diffused metal-oxide semiconductor field effect transistor) structure and a preparation method thereof.
Background
LDMOS is widely used in power integrated circuits due to its easy compatibility with CMOS (complementary metal oxide semiconductor) processes. The channel structure of the LDMOS device is transverse, and a drain electrode, a source electrode and a grid electrode of the LDMOS device are all arranged on the surface of a chip and can be integrated with a low-voltage circuit on the chip through internal interconnection. Meanwhile, the high-voltage LDMOS has the characteristics of high voltage and high current of discrete devices, also absorbs the advantage of high-density intelligent logic control of a low-voltage integrated circuit, and realizes the functions which can be completed by a plurality of chips originally by a single chip. Therefore, the high-voltage LDMOS greatly reduces the chip area, reduces the cost, improves the energy efficiency, and accords with the development direction of miniaturization, intellectualization and low energy consumption of modern power electronic devices.
As device geometries and minimum feature sizes shrink, new methods of providing relatively higher breakdown voltages, particularly in logic CMOS processes, become increasingly important. As it generally has a low cost and a minimum of process costs. It is therefore of great interest to provide an improved LDMOS.
In a conventional LDMOS structure, as shown in fig. 1, a manufacturing method thereof includes:
i: an N-well region 110 is formed on a semiconductor P-substrate 120, followed by a first P-well region 102 on the left side of N-well region 110 and a second P-well region 103 on the right side of N-well region 110. The two P-well and N-well regions 110 are all overlapped against each other.
II: STI (shallow trench isolation) structures 108A and 108B are formed on the surfaces of the well regions 110, 102, and 103, wherein the STI structure 108A is in the N-well region 110, and the STI structure 108B is between the N-well region 110 and the second P-well region 103.
III: an oxide layer 118 is formed by oxidation of silicon on the surface of the conductive P-type substrate 120, and a gate electrode 104 formed of a polysilicon layer is deposited, wherein the gate electrode 104 bridges the N-type well region 110 and the first P-type well region 102.
IV: ion implantation forms an N-type Lightly Doped Drain (LDD) implant in the left side region of the gate 104, while ion implantation forms an N-type Lightly Doped Drain (LDD) implant between the STI structures 108A and 108B.
V: and continuing to implant heavily-doped ions on the basis of IV to form the source region 114 and the drain region 112 of the N type.
VII: in the region on the right side of the STI structure 108B, a P-type base region 116 is formed by ion implantation, and the implanted region is in the second P-type well region 103.
VII: oxide spacers 116A and 116B are formed on both sides of the gate 104.
In fig. 1, Lc is the channel length from the source region 114 of the device to the STI structure 108A; lw represents the length of the lateral diffusion region under the gate 104; lo is the length of the region covered by the gate 104 and the STI structure 108A; ldp is the length of the STI structure 108A.
The LDMOS structure prepared by the method has the following problems:
1. lateral diffusion of the Lw region under the gate generates a high breakdown voltage for the device, the magnitude of the breakdown voltage is determined by the concentration of the N-well 110 and the concentration of the junction of the first P-well 102 and the N-well 110, the N-well 110 provides complementary electrons for the drain region 112, which results in the deep junction doping concentration of the 134 region in fig. 1 being lower than that of the drain region 112, and eventually the device does not reach the high breakdown voltage.
2. A PN junction may naturally form between first P-well region 102 and N-well region 110, and this PN junction breakdown may occur when a sufficiently large voltage is applied. In addition, breakdown voltage occurs in the overlap region where gate 104 overlaps N-well 110, which eventually causes current to flow from N-well 110 to semiconductor P-substrate 120 rather than to source 114.
Disclosure of Invention
The purpose of the invention is as follows: aiming at the prior art, the LDMOS structure and the preparation method are provided, so that the breakdown voltage and the reliability of the device are improved.
The technical scheme is as follows: an LDMOS structure comprising: the substrate comprises a substrate of A conductivity type, wherein a lightly doped epitaxial layer of the A conductivity type is arranged on the substrate of the A conductivity type; a well region of the first A conductivity type and a well region of the B conductivity type are arranged on the lightly doped epitaxial layer of the A conductivity type, and a gap is arranged between the well regions;
the well region of the B conduction type is provided with an STI structure, the grid electrode of the LDMOS structure crosses over the part of the well region of the first A conduction type to the part of the STI structure in the well region of the B conduction type, the source region of the LDMOS structure is positioned on the well region of the first A conduction type and on the left side of the grid electrode, and the drain region of the LDMOS structure is positioned on the well region of the B conduction type and on the right side of the STI structure;
dividing a grid into a first area, a second area, a third area and a fourth area from one end close to a source area along the crossing direction, wherein the second area is over against an interval area between the first A conductive type well area and the B conductive type well area, and the third area is over against a transverse drift area between the left side of the STI structure and the left side of the B conductive type well area; heavy doping injection is respectively carried out on the four regions on the surface of the grid electrode, and the injection type of each region is as follows: the doping mode of the region I is opposite to that of the first A conductive type well region, the doping mode of the region III is opposite to that of the B conductive type well region, and the region II and the region IV respectively select to carry out A conductive type injection or B conductive type injection or undoped injection.
Further, the value range of the interval length Lsub between the first a conductivity type well region and the B conductivity type well region is 18.2% -49.7% of the gate length.
Further, the conductivity types a and B are specifically: a is P type, B is N type; or A is N type and B is P type.
A preparation method of an LDMOS structure comprises the following steps:
i: epitaxially growing a lightly doped epitaxial layer of the A conductivity type on the substrate of the A conductivity type;
II: forming a well region of a B conductive type by downward ion implantation on the surface of the lightly doped epitaxial layer of the A conductive type, and then forming a well region of a first A conductive type by left side ion implantation of the well region of the B conductive type, wherein a gap exists between the well region of the B conductive type and the well region of the first A conductive type; forming a second A conductive type well region on the right side of the B conductive type well region through ion implantation, wherein the B conductive type well region and the second A conductive type well region are mutually overlapped and leaned;
III: forming a first STI structure and a second STI structure downwards on the surface of the lightly doped epitaxial layer of the A conductivity type, wherein the first STI structure is in the well region of the B conductivity type, and the second STI structure is between the well region of the B conductivity type and the well region of the second A conductivity type;
IV: oxidizing silicon on the surface of the epitaxial layer to form an oxide layer, and then depositing a grid electrode for forming a polycrystalline silicon layer, wherein the grid electrode crosses over the part of the well region of the first A conductivity type to the part of the first STI structure in the well region of the B conductivity type;
v: dividing a grid into a first area, a second area, a third area and a fourth area from one end close to a source area along the crossing direction, wherein the second area is over against an interval area between a first A conductive type well area and a B conductive type well area, and heavily doping injection is respectively carried out on the four areas on the surface of the grid, and the injection type of each area is as follows: the doping mode of the first region is opposite to that of the first A conductive type well region, the doping mode of the third region is opposite to that of the B conductive type well region, and the second region and the fourth region are respectively selected to carry out A conductive type injection or B conductive type injection or undoped injection;
VI: injecting to form a first shallow injection region of the B conductive type lightly doped drain injection at the left side of the grid, and injecting to form a second shallow injection region of the B conductive type lightly doped drain injection between the first STI structure and the second STI structure;
VII: forming side walls on two sides of the grid;
VIII: performing high-dose implantation with the same conductivity type in the first shallow implantation region to form a source region, and performing high-dose implantation with the same conductivity type in the second shallow implantation region to form a drain region;
IX: and forming an A conductive type base region in the right region of the second STI structure by ion implantation, wherein the implanted region is in the second A conductive type well region.
Further, the conductivity types a and B are specifically: a is P type, B is N type; or A is N type and B is P type.
Has the advantages that: 1. according to the invention, by increasing the distance between the two wells, the condition that the doping concentration of the deep junction is lower than that of the drain region is avoided, so that the breakdown voltage is improved.
2. According to the invention, materials with different conductive types are respectively injected and doped into the grid electrode, so that the breakdown voltage of the device is increased, the accidental conduction of current is inhibited, and the reliability of the device is improved.
Drawings
FIG. 1 is a schematic cross-sectional view of a conventional LDMOS structure;
FIG. 2 is a cross-sectional view of an LDMOS structure of the present invention;
FIG. 3 is a graph comparing the breakdown voltage of the LDMOS of the present invention with that of the prior art.
Detailed Description
The invention is further explained below with reference to the drawings.
As shown in fig. 2, the preparation method of the LDMOS structure of the present invention includes:
i: a lightly doped epitaxial layer 230 of a conductivity type is epitaxially grown on the a conductivity type substrate 220.
The added epitaxial layer 230 acts as a buffer layer to mitigate the risk of high current flowing directly to the substrate 220 causing the device to burn out when breakdown occurs.
II: forming a well region 210 of a B conductivity type by ion implantation downward on the surface of the lightly doped epitaxial layer 230 of an a conductivity type, and then forming a well region 202 of a first a conductivity type by ion implantation on the left side of the well region 210 of the B conductivity type, wherein the well region 210 and the well region 202 are not in contact with each other, and a gap is formed between the two, and the gap length of the gap is Lsub; meanwhile, the well region 203 of the second a conductivity type is formed by ion implantation at the right side of the well region 210 of the B conductivity type, and the well region 210 of the B conductivity type and the well region 203 of the second a conductivity type are overlapped and leaned against each other.
III: STI structures 208A and 208B are formed down the surface of the lightly doped epitaxial layer 230 of the a conductivity type, wherein the STI structures 208A are within the well region 210 of the B conductivity type and the STI structures 208B are between the well region 210 of the B conductivity type and the well region 203 of the second a conductivity type. The steps of forming the STI structure include, in sequence, trench etching, oxide filling, and oxide planarization.
IV: an oxide layer 218 is formed by oxidation of silicon on the surface of the epitaxial layer 230, and a gate 204 formed of a polysilicon layer is then deposited, the gate 204 spanning over a portion of the well region 202 of the first a conductivity type to over a portion of the STI structure 208A in the well region 210 of the B conductivity type.
V: the gate 204 is divided into four regions (i, ii, iii, and iv) from one end of the source region 214 along the crossing direction, wherein the region (ii) faces a spacing region between the first a conductivity type well region 202 and the B conductivity type well region 210, and the region (iii) faces a lateral drift region between the left side of the STI structure 208A and the left side of the B conductivity type well region 210; heavily doped implantation is performed on the four regions on the surface of the gate 204, and the region implantation type scheme is shown in the following table:
| ① | ② | ③ | ④ | |
| scheme 1 | B | B | A | B |
| Scheme 2 | B | B | A | A |
| Scheme 3 | B | B | A | Is free of |
| Scheme 4 | B | A | A | B |
| Scheme 5 | B | A | A | A |
| Scheme 6 | B | A | A | Is free of |
In the table, "none" indicates that the corresponding region is not doped.
VI: a first shallow implant region 213 is implanted at the left side of the gate 204 to form a Lightly Doped Drain (LDD) implant of B conductivity type, while a second shallow implant region 211 is implanted between the STI structures 208A and 208B to form a Lightly Doped Drain (LDD) implant of B conductivity type.
VII: spacers 216 are formed on both sides of the gate 204 to surround the polysilicon layer to prevent source and drain punch-through due to the large dose of source and drain implant being too close to the channel.
VIII: on the basis of step vi, a high dose implant of the same conductivity type is performed again in the first shallow implant region 213 to form the source region 214, and simultaneously, a high dose implant of the same conductivity type is performed again in the second shallow implant region 211 to form the drain region 212.
IX: an a conductivity type base region 217 is ion implanted in a region on the right side of the STI structure 208B, the implanted region being within the second a conductivity type well region 203.
In fig. 2, Lc is the channel length from the source region 214 of the device to the STI structure 208A; lo is the length of the gate 204 and the STI structure 208A in the covered region; ldp is the length of the STI structure 208A.
In the present invention, the conductivity types a and B are classified into the following two cases:
| type of conductivity | A | B |
| Scheme 1 | P type | N type |
| Scheme 2 | N type | P type |
Fig. 3 shows a comparison of the breakdown voltage of the conventional LDMOS device compared to the device provided by the present invention, where the breakdown voltage of the conventional LDMOS device is less than 15V, and the breakdown voltage of the device of the present invention can reach more than 20V.
In the figure: the values following the letters represent the applied gate voltage, e.g. a1.1 is a plot at gate voltage Vg = 1.1V; a1.1, a2.2 and a3.3 are breakdown voltages of the original device under the voltages of 1.1V, 2.2V and 3.3V respectively. b. When the curves of c and d are different Lsub values, 3 voltage curve graphs are provided, wherein b is more than c and less than d; in fig. 3, the Lsub values corresponding to the curves b, c, d are: 6.5% ((Lc + Lo), 26.3% ((Lc + Lo), 49.4% ((Lc + Lo)), where (Lc + Lo) is the length of the gate 204.
In the LDMOS structure prepared by the above method, a lateral drift region LW is formed between the left side of the STI structure 208A and the left side of the B conductive type well region 210, and the first a conductive type well region 202 and the B conductive type well region 210 are separated by a length Lsub, which can prevent a PN junction formed by overlapping the two, thereby improving breakdown voltage. Specifically, the lateral diffusion of the region Lw under the gate causes the device to have a high breakdown voltage, and the magnitude of the breakdown voltage is determined by two aspects:
a. is determined by the concentration of the B conductive type well region 210.
b. The concentration at the interface of the first a conductivity type well region 202 and the B conductivity type well region 210.
Since well region 210 of the B conductivity type is also required to provide complementary electrons to drain region 212, in the prior art shown in fig. 1, a PN junction is naturally formed between first P-well region 102 and N-well region 110 by relying on each other, which consumes the electron concentration of N-well region 110 and fails to provide sufficient complementary electrons to drain region 112.
The structure of the invention enables the interval with the length Lsub to be arranged between the well region 202 of the first A conductivity type and the well region 210 of the B conductivity type, thereby avoiding that the first well region 202 of the A conductivity type and the well region 210 of the B conductivity type naturally form PN junctions mutually, consuming electrons of the well region of the B conductivity type 210, ensuring that the well region 210 of the B conductivity type provides enough complementary electrons for the drain region 212, and finally achieving the purpose of improving breakdown voltage. Wherein, Lsub value is determined according to the length of the gate 204, and the preferred value range is: lsub =18.2% (Lc + Lo) to 49.7% (Lc + Lo), and the length of the gate 204 is determined according to the actual process requirements, which is not limited herein.
In the above scheme, the doping manner of the first region is opposite to that of the first a conductive type well region 202, and the doping manner of the third region is opposite to that of the B conductive type well region 210, so that the surface electric field of the device is increased along the length of the lateral diffusion region under the gate 204 by the doping manner, thereby increasing the breakdown voltage, and simultaneously suppressing the accidental conduction of current, that is, suppressing the current from flowing from the B conductive type well region 210 to the a conductive type substrate 220, thereby improving the reliability of the device.
In the scheme, the four regions are respectively subjected to heavy doping injection on the surface of the gate 204, the doping types of the region (i) and the region (iii) change the surface electric field of the device, so that the length of the transverse diffusion region under the gate 204 flowing to the drain region 212 is increased, the source-drain resistance Rsd is increased, and the breakdown voltage is increased under the conditions of the same device size and the same gate voltage.
The doping of region c is opposite to the first a conductivity type well 202 and the doping of region c is opposite to the B conductivity type well 210, which will inhibit the hole electrons in the first a conductivity type well 202 and the B conductivity type well 210 from flowing to the substrate 220. Accidental conduction of current is avoided, thereby improving the reliability of the device.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (5)
1. An LDMOS structure, comprising: the substrate comprises an A conductive type substrate (220), wherein a lightly doped epitaxial layer (230) of the A conductive type is arranged on the A conductive type substrate (220); a well region (202) of the first A conductivity type and a well region (210) of the B conductivity type are arranged on the lightly doped epitaxial layer (230) of the A conductivity type, and a gap is arranged between the well regions;
the well region (210) of the B conduction type is provided with an STI structure (208A), a grid electrode (204) of the LDMOS structure crosses over a part of the well region (202) of the first A conduction type to a part of the well region (210) of the B conduction type, above the STI structure (208A), a source region (214) of the LDMOS structure is positioned on the well region (202) of the first A conduction type and on the left side of the grid electrode (204), and a drain region (212) of the LDMOS structure is positioned on the well region (210) of the B conduction type and on the right side of the STI structure (208A);
dividing a grid electrode (204) into four regions from one end close to a source region (214) along the crossing direction, wherein the region is over against an interval region between a first A conductive type well region (202) and a B conductive type well region (210), and the region is over against a transverse drift region between the left side of an STI structure (208A) and the left side of the B conductive type well region (210); heavily doped injection is respectively carried out on the four regions on the surface of the grid (204), and the injection type of each region is as follows: the doping mode of the area I is opposite to that of the first A conductive type well region (202), the doping mode of the area III is opposite to that of the B conductive type well region (210), and the areas II and III are respectively selected to carry out A conductive type injection or B conductive type injection or undoped injection.
2. The LDMOS structure of claim 1, wherein a spacing length Lsub between the first well region of a conductivity type (202) and the well region of a conductivity type (210) is in a range of 18.2% to 49.7% of a length of the gate (204).
3. The LDMOS structure of claim 1 or 2, wherein the a and B conductivity types are in particular: a is P type, B is N type; or A is N type and B is P type.
4. A preparation method of an LDMOS structure is characterized by comprising the following steps:
i: epitaxially growing a lightly doped epitaxial layer (230) of the A conductivity type on the A conductivity type substrate (220);
II: forming a well region (210) of a B conductive type by downward ion implantation on the surface of the lightly doped epitaxial layer (230) of the A conductive type, and then forming a well region (202) of a first A conductive type by left side ion implantation of the well region (210) of the B conductive type, wherein a gap exists between the well region (210) of the B conductive type and the well region (202) of the first A conductive type; forming a well region (203) of a second A conductive type by ion implantation at the right side of the well region (210) of the B conductive type, wherein the well region (210) of the B conductive type and the well region (203) of the second A conductive type are mutually overlapped and leaned;
III: forming a first STI structure (208A) and a second STI structure (208B) on the surface of the lightly doped epitaxial layer (230) of the A conductive type, wherein the first STI structure (208A) is in the well region (210) of the B conductive type, and the second STI structure (208B) is between the well region (210) of the B conductive type and the well region (203) of the second A conductive type;
IV: forming an oxide layer (218) by oxidation of silicon on the surface of the epitaxial layer (230), and then depositing a gate (204) forming a polysilicon layer, wherein the gate (204) crosses over a portion of the well region (202) of the first A conductivity type to a portion of the first STI structure (208A) in the well region (210) of the B conductivity type;
v: the grid electrode (204) is divided into four regions from one end close to a source region (214) along the crossing direction, the region is over against an interval region between a first A conductive type well region (202) and a B conductive type well region (210), heavy doping injection is respectively carried out on the four regions on the surface of the grid electrode (204), and the injection type of each region is as follows: the doping mode of the first region is opposite to that of the first A conductive type well region (202), the doping mode of the third region is opposite to that of the B conductive type well region (210), and the second region and the fourth region respectively select to perform A conductive type injection or B conductive type injection or undoped injection;
VI: implanting a first shallow implant region (213) forming a lightly doped drain implant of the B conductivity type at the left side of the gate (204), and implanting a second shallow implant region (211) forming a lightly doped drain implant of the B conductivity type between the first STI structure (208A) and the second STI structure (208B);
VII: forming side walls (216) on two sides of the gate (204);
VIII: performing high-dose implantation of the same conductivity type in the first shallow implantation region (213) to form a source region (214), and performing high-dose implantation of the same conductivity type in the second shallow implantation region (211) to form a drain region (212);
IX: a base region (217) of the A conductivity type is formed by ion implantation in a region on the right side of the second STI structure (208B), and the implantation region is in a well region (203) of the second A conductivity type.
5. The method for preparing an LDMOS structure of claim 4, wherein the A conductivity type and the B conductivity type are specifically: a is P type, B is N type; or A is N type and B is P type.
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