CN114242669B - Stack packaging structure and stack packaging method - Google Patents
Stack packaging structure and stack packaging method Download PDFInfo
- Publication number
- CN114242669B CN114242669B CN202210183320.XA CN202210183320A CN114242669B CN 114242669 B CN114242669 B CN 114242669B CN 202210183320 A CN202210183320 A CN 202210183320A CN 114242669 B CN114242669 B CN 114242669B
- Authority
- CN
- China
- Prior art keywords
- chip
- substrate
- chips
- stacked
- glue layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 95
- 239000003292 glue Substances 0.000 claims abstract description 42
- 239000004033 plastic Substances 0.000 claims abstract description 28
- 239000010410 layer Substances 0.000 claims description 81
- 239000012790 adhesive layer Substances 0.000 claims description 41
- 239000002184 metal Substances 0.000 claims description 14
- 239000000853 adhesive Substances 0.000 claims description 11
- 230000001070 adhesive effect Effects 0.000 claims description 11
- 230000001681 protective effect Effects 0.000 claims description 9
- 230000017525 heat dissipation Effects 0.000 abstract description 9
- 230000006870 function Effects 0.000 description 14
- 230000003139 buffering effect Effects 0.000 description 7
- 230000010354 integration Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000006185 dispersion Substances 0.000 description 3
- 230000002349 favourable effect Effects 0.000 description 3
- 230000002745 absorbent Effects 0.000 description 2
- 239000002250 absorbent Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004793 Polystyrene Substances 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920002223 polystyrene Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001149 thermolysis Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The embodiment of the invention provides a stacked packaging structure and a stacked packaging method, and relates to the technical field of chip packaging. The stacked packaging structure comprises a substrate, a first chip, a second chip, a third chip and a fourth chip, wherein the first chip is inversely arranged on the substrate; the second chip is arranged on one side of the first chip far away from the substrate; the third chip is arranged on the substrate and is arranged at an interval with the first chip; a first groove is formed between the first chip and the third chip, and a buffer glue layer is filled in the first groove; the fourth chip is arranged on one side of the second chip and/or the third chip far away from the substrate; the substrate is provided with a plastic package body for protecting the first chip, the second chip, the third chip and the fourth chip; the thermal expansion coefficient of the buffer glue layer is smaller than that of the plastic package body. The stress of the stacked structure can be effectively relieved, and the heat dissipation performance of the structure can be improved.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a stacked packaging structure and a stacked packaging method.
Background
Since consumers prefer an electronic product with a thinner thickness and a higher product performance and a higher memory, the miniaturization design of the electronic product is more and more common, and in order to meet the requirements of users, a semiconductor package structure usually adopts a multi-chip stacking technology (Stack-Die) or a chip hybrid stacking technology (hybrid Stack-Die) to Stack two or more chips in a single package structure, so as to achieve the purposes of smaller product package volume and higher product performance. As the number of stacked chips increases, the greater the stress within the package structure, the more significantly the structure is affected by the stress.
Disclosure of Invention
The object of the present invention includes, for example, providing a package on package structure and a package on package method, which can improve the internal stress of the package structure and alleviate the adverse effect of the structural stress.
Embodiments of the invention may be implemented as follows:
in a first aspect, the present invention provides a package on package structure, which includes a substrate, and a first chip, a second chip, a third chip, and a fourth chip disposed on the substrate, wherein:
the first chip is inversely arranged on the chip;
the second chip is arranged on one side of the first chip far away from the substrate;
the third chip is arranged on the substrate and is arranged at an interval with the first chip; a first groove is formed between the first chip and the third chip, and a buffer glue layer is filled in the first groove;
the fourth chip is arranged on one side, far away from the substrate, of the second chip and/or the third chip;
a plastic package body is arranged on the substrate to protect the first chip, the second chip, the third chip and the fourth chip;
the thermal expansion coefficient of the buffer glue layer is smaller than that of the plastic package body.
In an alternative embodiment, the chip assembly includes the first chip and the second chip, and the height of the third chip is equal to the height of the chip assembly.
In an alternative embodiment, the height of the third chip is equal to the sum of the height of the first chip and the height of the second chip.
In an alternative embodiment, the fourth chip is inversely mounted on the second chip and the third chip; the third chip is connected with the substrate through a metal wire, the fourth chip is electrically connected with the third chip, and the second chip is electrically connected with the fourth chip.
In an optional embodiment, the ic further includes a fifth chip, and the fifth chip is disposed on a side of the fourth chip far away from the second chip.
In an alternative embodiment, the fifth chip is being mounted on the fourth chip, and the fifth chip and the substrate are connected by a metal wire.
In an optional embodiment, the chip further comprises a sixth chip, and the sixth chip is arranged on a side of the fifth chip away from the fourth chip; and a second groove is formed between every two adjacent fifth chips, the buffer glue layer is arranged in the second groove, and the buffer glue layer is positioned between the fourth chips and the sixth chips.
In an optional embodiment, the chip further comprises a seventh chip and an eighth chip, the seventh chip is arranged on one side of the sixth chip away from the fourth chip at intervals, and a third groove is formed between every two adjacent seventh chips;
the eighth chip is arranged on one side, away from the sixth chip, of the seventh chip, the eighth chip is electrically connected with the seventh chip, and the seventh chip is electrically connected with the substrate;
and the third groove is internally provided with the buffer glue layer, and the buffer glue layer is arranged between the sixth chip and the eighth chip.
In an alternative embodiment, the third groove is located corresponding to the second groove, and the second groove is located corresponding to the first groove.
In an optional implementation manner, a first bump is disposed on one side of the first chip close to the substrate, a first pad is disposed on the substrate, the first bump is electrically connected to the first pad, and a protective adhesive is disposed between the first chip and the substrate.
In an optional embodiment, a plurality of layers of chips are stacked on a side of the fourth chip away from the substrate, the plurality of layers of chips are alternately stacked according to flip chips and front-mounted chips, the buffer glue layer is arranged between two adjacent layers of flip chips, the flip chips are electrically connected with the front-mounted chips, and the front-mounted chips are electrically connected with the substrate.
In an optional implementation manner, an outer layer chip is disposed on one side of the third chip away from the first chip, the outer layer chip and the third chip are disposed at an interval to form a fourth groove, and the buffer glue layer is disposed in the fourth groove.
In a second aspect, the present invention provides a package method for a stacked structure, including:
providing a substrate;
a first chip is arranged on the substrate in an inverted and pasted mode;
a second chip is positively mounted and attached on the first chip;
a third chip is arranged on the substrate in a positive mounting and sticking mode, wherein the third chip and the first chip are arranged at intervals, and the height of the third chip is equal to the sum of the height of the first chip and the height of the second chip;
filling a buffer glue layer between the first chip and the third chip;
a fourth chip is arranged on the second chip and the third chip in an inverted mode, is electrically connected with the second chip and the third chip respectively, and is arranged on one side, far away from the substrate, of the buffer adhesive layer;
and arranging a plastic package body on the substrate to cover all chips and circuits on the substrate, wherein the thermal expansion coefficient of the buffer glue layer is smaller than that of the plastic package body.
In an alternative embodiment, the step of mounting the fourth chip further includes:
stacking a plurality of chips on a side of the fourth chip away from the substrate, wherein:
the multiple layers of chips are alternately stacked according to flip chips and forward chips, the buffer glue layer is arranged between two adjacent layers of flip chips, and the flip chips are electrically connected with the forward chips;
and a metal wire is arranged between the upright chip and the substrate.
The beneficial effects of the embodiment of the invention include, for example:
according to the stacked packaging structure provided by the embodiment of the invention, the second chip is stacked above the first chip, and the fourth chip is stacked above the second chip and the third chip, so that a multi-layer stacked structure is formed, the packaging efficiency is high, and the chip integration level is high; fill the buffering glue film between first chip and the third chip, because the thermal expansion coefficient of buffering glue film is less than the thermal expansion coefficient of plastic-sealed body, at the plastic-sealed in-process, the buffering glue film can be out of shape preferentially, the absorbent structure stress to make packaging structure's stress obtain alleviating, simultaneously, this buffering glue film can also play the supporting role, prevents that the structure from collapsing, and play the thermolysis to packaging structure, can improve packaging structure's heat dispersion.
According to the packaging method of the stack structure, provided by the embodiment of the invention, the multiple layers of chips are stacked on the substrate, and the packaging structure can realize function diversification, high integration level, excellent performance and small overall volume size. The height of the third chip is the sum of the heights of the first chip and the second chip, the structure is more compact, more chips can be stacked upwards, and the stacking structure is more stable. Fill the cushion glue film between first chip and third chip, can play the absorbent structure stress, alleviate the structure warpage, promote structural strength and stability to and the effect of improvement heat dispersion.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a first structural diagram of a package on package structure according to an embodiment of the invention;
fig. 2 is a schematic view of a stacked package structure with an outer chip layer according to an embodiment of the invention;
fig. 3 is a schematic structural diagram of another view angle of a stacked package structure with an outer chip according to an embodiment of the present invention;
FIG. 4 is a second structural diagram of a package on package structure according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating a third structure of a package on package structure according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating a trench location of a package on package structure according to an embodiment of the present invention;
fig. 7 is a first schematic flow chart illustrating a manufacturing method of a package with a stacked structure according to an embodiment of the present invention;
fig. 8 is a second manufacturing flow diagram of the package method with stacked structure according to the embodiment of the invention.
Icon: 10-stacked package structure; 110-a substrate; 101-a first pad; 103-a second pad; 111-solder balls; 113-a plastic package body; 115-protective glue; 118-an adhesive layer; 120-a first chip; 121-a first dome; 130-a second chip; 140-a third chip; 141-metal lines; 150-a fourth chip; 151-second stud ball; 160-buffer glue layer; 161-a first trench; 163-second trenches; 165-third trenches; 171-a fifth chip; 173-sixth chip; 175-seventh chip; 177-an eighth chip; 180-outer layer chip.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. indicate an orientation or a positional relationship based on that shown in the drawings or that the product of the present invention is used as it is, this is only for convenience of description and simplification of the description, and it does not indicate or imply that the device or the element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.
First embodiment
Referring to fig. 1, the present embodiment provides a package on package structure 10, including a substrate 110, a first chip 120, a second chip 130, a third chip 140, and a fourth chip 150, wherein: the first chip 120 is flip-chip mounted on the substrate 110; the second chip 130 is mounted on the first chip 120 at a side away from the substrate 110; the third chip 140 is disposed on the substrate 110 and spaced apart from the first chip 120; a first groove 161 (see fig. 6) is formed between the first chip 120 and the third chip 140, and the first groove 161 is filled with a buffer glue layer 160; the fourth chip 150 is disposed on a side of the second chip 130 and/or the third chip 140 away from the substrate 110; a plastic package body 113 is arranged on the substrate 110 to protect the first chip 120, the second chip 130, the third chip 140 and the fourth chip 150; the thermal expansion coefficient of the cushion glue layer 160 is smaller than that of the plastic package body 113. The stacked package structure 10 has high chip integration level, can realize function diversification, has excellent performance and small integral volume size, and is favorable for light weight and miniaturization design of electronic products. The buffer adhesive layer 160 is filled between the first chip 120 and the third chip 140, and because the thermal expansion coefficient of the buffer adhesive layer 160 is smaller than that of the plastic package body 113, the buffer adhesive layer 160 can be preferentially deformed and absorb the structural stress in the plastic package process, so that the stress of the package structure is relieved and released, and the structure warpage phenomenon is relieved; meanwhile, the buffer glue layer 160 can also play a supporting role, prevent the structure from collapsing, improve the structural strength and stability, play a role in heat dissipation of the stacked package structure 10, and improve the heat dissipation performance of the stacked package structure 10.
Optionally, the first chip 120 and the second chip 130 are configured as a chip combination, i.e. the chip combination includes the first chip 120 and the second chip 130, and the height of the third chip 140 is equal to the height of the chip combination. In the present embodiment, the chip assembly includes a first chip 120 and a second chip 130, and the height of the third chip 140 is substantially equal to the sum of the height of the first chip 120 and the height of the second chip 130. The structure is more compact, more chips are stacked upwards, the fourth chip 150 can be stably arranged on the second chip 130 and the third chip 140, and the stacking structure is more stable. In other embodiments, the number of chips stacked in a chip combination is not limited to two, and may be one, three, four, or more. The height of the chip assembly includes the height of the chip itself and the height of the connection between the chips, including but not limited to the glue layer thickness and the wire bonding height for mounting the chip. The height of the third chip 140 is equal to the height of the chip assembly, that is, the side surface of the third chip 140 away from the substrate 110 is flush with the side surface of the chip assembly away from the substrate 110, which is beneficial to the arrangement of the fourth chip 150, and the stacking manner is more flexible and the application range is wider. It is understood that the fourth chip 150 may be disposed on the second chip 130, the third chip 140, or both the second chip 130 and the third chip 140. In this embodiment, the bottom of the first chip 120 is provided with a first stud bump 121, and the first stud bump 121 is soldered to the first pad 101 of the substrate 110, so as to electrically connect the first chip 120 and the substrate 110. The fourth chip 150 is flip-chip mounted on the second chip 130 and the third chip 140; the third chip 140 is connected to the second pad 103 of the substrate 110 through a metal wire 141, the fourth chip 150 is electrically connected to the third chip 140, and the second chip 130 is electrically connected to the fourth chip 150, so that the second chip 130 and the fourth chip 150 are electrically connected to the substrate 110, respectively. It is understood that the second chip 130 and the third chip 140 are respectively provided with bonding pads for connecting with the bottom stud balls of the fourth chip 150.
Optionally, a protective adhesive 115 is disposed between the first chip 120 and the substrate 110 for protecting the first stud balls 121, and the protective adhesive 115 is a non-conductive adhesive. The second chip 130 may be adhered to the first chip 120 by an adhesive layer 118, the third chip 140 may be adhered to the substrate 110 by the adhesive layer 118, the bottom of the fourth chip 150 is provided with a second stud ball 151, the second stud ball 151 is respectively welded to the third chip 140 and the second chip 130, and the bottom of the fourth chip 150 is also provided with a protective adhesive 115 for protecting the second stud ball 151.
It is easy to understand that the number of the third chips 140 may include one or more, if the number of the third chips 140 is multiple, a plurality of the third chips 140 are disposed around the first chip 120 and the second chip 130 at intervals, each of the third chips 140 forms a first trench 161 between the first chips 120, and all the first trenches 161 are filled with the buffer glue layer 160. The number of the fourth chips 150 may also be one or more, and a plurality of the fourth chips 150 are spaced apart and located on the same height layer, which is not limited herein.
The side of the substrate 110 away from the first chip 120 is provided with solder balls 111, and the solder balls 111 are used for connecting with pads on a circuit board. The plastic package body 113 on the substrate 110 is used for plastic package protection of all chips, wire bonding structures, and the like. In the stack package structure 10, the chip integration level is high, the functions are various, the structure is compact, and the volume size is small; through setting up buffering glue film 160, alleviate structural stress, promote structural strength simultaneously, improve heat dispersion.
Optionally, with reference to fig. 2 and fig. 3, an outer layer chip 180 is disposed on a side of the third chip 140 away from the first chip 120, the outer layer chip 180 and the third chip 140 are disposed at an interval to form a fourth groove (not shown), and a buffer adhesive layer 160 is disposed in the fourth groove. The outer chip 180 is wire-bonded to the substrate 110, and the fourth chip 150 may be disposed on the third chip 140 and the outer chip 180, or the fourth chip 150 may be disposed on the outer chip 180 alone. Set up like this and can further alleviate the stress of piling up packaging structure 10, improve the radiating effect, and can pile up more chips, the chip integrated level is higher, and the function is abundanter various. The number of outward-extending annular turns of the outer layer chips 180 and the number of the outer layer chips 180 included in each turn may be set according to practical situations, and the buffer adhesive layer 160 is filled between every two adjacent turns of the outer layer chips 180, which is not particularly limited herein.
It should be noted that, in fig. 3, the structures of wire bonding and the like in the stacked package structure 10 are omitted only for showing the structure of the buffer adhesive layer 160 between the outer layer chip 180 and the third chip 140. The connection manner of the outer layer chip 180 and the substrate 110 is similar to the connection manner of the third chip 140 and the substrate 110, and is not repeated herein.
The buffer adhesive layer 160 has the functions of relieving stress, conducting heat, and having certain structural strength and bonding and fixing functions. In an alternative embodiment, the material composition of the cushion rubber layer 160 at different positions may be different to achieve the enhancement effect of the local corresponding function. For example, in the plane of the surface of the substrate 110, the buffer adhesive layer 160 includes a first loop, a second loop and a third loop in the direction from the first chip 120 to the outside, wherein the buffer adhesive layer 160 of the inner loop layer, such as the first loop, has the main function of thermal conductivity and the auxiliary function of buffering the release stress, and the buffer adhesive layer 160 of the outer loop layer, such as the second loop and the third loop, has the main function of releasing the stress and the auxiliary function of thermal conductivity. Alternatively, in the stacking height direction, the buffer adhesive layer 160 includes a first layer, a second layer and a third layer in the upward direction from the substrate 110, wherein the lower layer, such as the buffer adhesive layer 160 of the first layer and the second layer, has the main functions of heat conduction and improvement of structural strength and is assisted by buffering and releasing stress, and the higher layer, such as the buffer adhesive layer 160 of the third layer, has the main functions of releasing stress and is assisted by heat conduction. The leading performance of the buffer adhesive layer 160 can be flexibly adjusted according to the local situation of the actual stacked product, so as to fully exert various performances of the buffer adhesive layer 160 and improve the packaging quality of the product.
Second embodiment
Referring to fig. 4, the package on package structure 10 in the present embodiment continues to stack more chips based on the first embodiment, so as to improve the chip integration and fully utilize the stacking space on the substrate 110.
Optionally, the stacked package structure 10 further includes a fifth chip 171, and the fifth chip 171 is disposed on a side of the fourth chip 150 away from the second chip 130. The fifth chip 171 is mounted on the fourth chip 150, and the fifth chip 171 is connected to the substrate 110 through the metal wires 141, that is, by wire bonding. The number of the fifth chips 171 includes one or more, the plurality of fifth chips 171 are disposed at the same height layer at intervals, the plurality of fifth chips 171 are sequentially connected by the metal lines 141, and the fifth chip 171 located at the outer side is connected to the substrate 110 by the metal lines 141.
In this embodiment, the number of the fourth chips 150 is two, the number of the fifth chips 171 is three, the three fifth chips 171 are disposed above the two fourth chips 150, and optionally, the fifth chips 171 are fixed on the fourth chips 150 by the adhesive layer 118. Because the fourth chip 150 is disposed in an inverted manner, the height difference between the third chip 140 and the fifth chip 171 is increased, and more space is provided for routing the third chip 140. The operation is more convenient, the structure is more stable, and the routing connection is firmer.
The contents of the portions not mentioned in the present embodiment are similar to those described in the first embodiment, and are not particularly limited herein.
Third embodiment
With reference to fig. 5 and fig. 6, optionally, the stacked package structure 10 in the present embodiment is based on the second embodiment, and further stacks more chips upwards to improve the chip integration level and fully utilize the stacking space on the substrate 110.
The stacked package structure 10 further includes a sixth chip 173, wherein the sixth chip 173 is disposed on a side of the fifth chip 171 away from the fourth chip 150; a second groove 163 is formed between two adjacent fifth chips 171, a buffer adhesive layer 160 is disposed in the second groove 163, and the buffer adhesive layer 160 is located between the fourth chip 150 and the sixth chip 173. Optionally, the sixth chip 173 is flip-chip mounted on the fifth chip 171 and electrically connected to the fifth chip 171. One or more sixth chips 173 may be provided according to actual situations, the number of the sixth chips 173 shown in fig. 5 is two, two sixth chips 173 are provided corresponding to two fourth chips 150, and each sixth chip 173 is straddled on two fifth chips 171. It is understood that the bottom of the sixth chip 173 is provided with the stud balls, the stud balls are electrically connected to the fifth chip 171 by soldering, and the protective adhesive 115 is provided between the bottom of the sixth chip 173 and the fifth chip 171 to protect the stud balls at the bottom of the sixth chip 173.
Optionally, the stacked package structure 10 of the present embodiment further includes a seventh chip 175 and an eighth chip 177, the seventh chip 175 is disposed at an interval on a side of the sixth chip 173 away from the fourth chip 150, and a third trench 165 is formed between two adjacent seventh chips 175; the eighth chip 177 is disposed on a side of the seventh chip 175 away from the sixth chip 173, the eighth chip 177 is electrically connected to the seventh chip 175, and the seventh chip 175 is electrically connected to the substrate 110; a buffer adhesive layer 160 is disposed in the third trench 165, and the buffer adhesive layer 160 is disposed between the sixth chip 173 and the eighth chip 177. It should be noted that the number of the seventh chips 175 and the number of the eighth chips 177 may be one or more according to actual situations. In this embodiment, the number of the seventh chips 175 is three, and the number of the eighth chips 177 is two; the seventh chip 175 is mounted on the sixth chip 173, three seventh chips 175 are spaced apart from each other and disposed on the same height layer, a third groove 165 is formed between two adjacent seventh chips 175, and the seventh chips 175 may be fixed to the sixth chip by an adhesive layer 118.
The two eighth chips 177 are flip-chip mounted on the three seventh chips 175, and the two eighth chips 177 are spaced apart and located at the same height. The bottom of the eighth chip 177 is provided with a bump, the bump is electrically connected with the seventh chip 175 by welding, and a protective adhesive 115 is disposed between the bottom of the eighth chip 177 and the seventh chip 175 to protect the bump at the bottom of the eighth chip 177. In this embodiment, the eighth chip 177 and the sixth chip 173 are correspondingly disposed, the seventh chip 175 and the fifth chip 171 are correspondingly disposed, so that the structure is more stable, and after such disposition, the position of the third groove 165 corresponds to the position of the second groove 163, the position of the second groove 163 corresponds to the position of the first groove 161, the buffer adhesive layers 160 on the layers with different heights are located on the same vertical cross section, which is favorable for improving the structural strength, and the absorption effect of the structural stress is better, which is favorable for improving the heat dissipation effect. Certainly, without being limited thereto, the chips of each height layer may also be arranged in a staggered manner or stacked in other manners, so that the plurality of buffer glue layers 160 are distributed on different vertical cross sections, which can also enhance the strength of the package structure, improve heat dissipation, alleviate warpage caused by stress, and improve package quality.
The contents not mentioned in this embodiment are similar to those described in the first embodiment and the second embodiment, and are not described again here.
It should be noted that, a plurality of layers of chips are stacked on one side of the fourth chip 150 away from the substrate 110, the plurality of layers of chips are stacked alternately according to the flip chips and the normal chips, a buffer adhesive layer 160 is arranged between two adjacent layers of flip chips, the flip chips are electrically connected with the normal chips, and the normal chips are electrically connected with the substrate 110. The number of stacked chips and the number of chips per layer may be determined according to practical circumstances and is not particularly limited. Through flip chip and just adorn the chip and range upon range of in turn, the structure is compacter to flip chip's height has reserved the space for just adorning the routing of chip, is convenient for just adorn the routing of chip. The sum of the heights of the first chip 120 and the second chip 130 is equal to the height of the third chip 140, the structure is compact, a stable stacking base is provided for the fourth chip 150 and the chips above, and the structure is more stable. The arrangement of the buffer adhesive layer 160, including but not limited to the buffer adhesive layer 160 between the second chip 130 and the third chip 140, between the adjacent fifth chips 171, and between the adjacent seventh chips 175, can absorb the structural stress during the packaging process, alleviate the structural warpage, improve the structural strength, and improve the heat dissipation.
Fourth embodiment
With reference to fig. 7 and fig. 8, a package on package method for a stack structure according to an embodiment of the present invention is applied to the package on package structure 10, and the package on package structure 10 in the first embodiment is taken as an example for description, and the package on package method for a stack structure mainly includes:
providing a substrate 110; the substrate 110 is provided with a first bonding pad 101 and a second bonding pad 103, the first bonding pad 101 is used for welding with the flip-chip first chip 120, and the second bonding pad 103 is used for wire bonding with the forward-mounted chip.
A first chip 120 is flip-chip bonded on the substrate 110; the bottom of the first chip 120 is provided with a first stud bump 121, the first stud bump 121 is soldered to the first pad 101, and the bottom of the first chip 120, i.e., a protective adhesive 115 is disposed between the first chip 120 and the substrate 110 for protecting the first stud bump 121. The protective adhesive 115 is a non-conductive adhesive layer, and the material may be epoxy resin or the like.
A second chip 130 is attached to the first chip 120; wherein, the second chip 130 is fixed on the first chip 120 by the adhesive layer 118; a third chip 140 is mounted and attached on the substrate 110, wherein the third chip 140 and the first chip 120 are spaced apart from each other to form a first trench 161; and the height of the third chip 140 is equal to the sum of the height of the first chip 120 and the height of the second chip 130; the third chip 140 is fixed on the substrate 110 by the adhesive layer 118; the adhesive layer 118 may be a non-conductive adhesive for securing and dissipating heat. In this embodiment, the chip assembly includes the first chip 120 and the second chip 130, and the height of the third chip 140 is substantially equal to the sum of the height of the first chip 120 and the height of the second chip 130. In other embodiments, the number of chips stacked in a chip combination is not limited to two, and may be three, four or more. The height of the chip assembly includes the height of the chip itself and the height of the connection between the chips, including but not limited to the glue layer thickness and the wire bonding height for mounting the chip.
The buffer glue layer 160 is filled between the first chip 120 and the third chip 140, that is, the buffer glue layer 160 is filled in the first trench 161. The thermal expansion coefficient of the buffer adhesive layer 160 is smaller than that of the plastic package body 113, so that the buffer adhesive layer can deform preferentially to the plastic package body 113, absorb the structural stress of the plastic package body 113, prevent the plastic package body 113 from deforming and absorb the stress of the upper stacked structure, and simultaneously can serve as a heat dissipation layer to dissipate heat of the stacked structure. The buffer adhesive layer 160 is a non-conductive material, including but not limited to epoxy resin, polyimide, benzocyclobutene, polystyrene, and other polymer composite materials.
And (3) routing, and connecting the third chip 140 and the substrate 110 through the metal wire 141. A fourth chip 150 is flip-chip mounted on the second chip 130 and the third chip 140, and the fourth chip 150 is electrically connected to the second chip 130 and the third chip 140, and is disposed on a side of the buffer adhesive layer 160 away from the substrate 110; optionally, the length and width of the second chip 130 are adapted to the length and width of the first chip 120, so that the stacking structure is more stable, facilitating the stacking of the fourth chip 150 and the chips above.
And plastic packaging, wherein a plastic packaging body 113 is arranged on the substrate 110 to cover all chips and circuits on the substrate 110 so as to protect all chip and circuit structures on the substrate 110, and because the thermal expansion coefficient of the buffer adhesive layer 160 is smaller than that of the plastic packaging body 113, the buffer adhesive layer 160 can deform preferentially to the plastic packaging body 113 to absorb the structural stress of the plastic packaging body 113, so that the plastic packaging body 113 is prevented from deforming and the stress of the upper-layer stacked structure is absorbed, and meanwhile, the plastic packaging body can also be used as a heat dissipation layer to play a role in dissipating heat of the stacked structure.
And (3) ball planting, wherein a solder ball 111 is planted on one side of the substrate 110 far away from the chip, and the solder ball 111 is used for connecting with a circuit board. Finally, the encapsulated structure is cut into individual products.
Optionally, the step of mounting the fourth chip 150 further includes: and stacking a plurality of chips on the fourth chip 150 at a side away from the substrate 110, wherein the plurality of chips are alternately stacked according to flip chips and front mounted chips, a buffer adhesive layer 160 is arranged between two adjacent layers of flip chips, and a metal wire 141 is arranged between the front mounted chip and the substrate 110. In this embodiment, the flip chip is electrically connected to the front chip through the bottom bump, the front chip is connected to the second pad 103 on the substrate 110 through the metal line 141, the number of stacked chips and the number of chips in each layer structure are determined according to practical situations, and are not limited specifically here.
The contents of other parts not mentioned in this embodiment are similar to those described in the first, second, and third embodiments, and are not repeated here.
In summary, the embodiments of the present invention provide a stacked package structure 10 and a stacked package method, which can integrate a plurality of chips in a single package structure, have high chip integration and a compact structure, and can implement the function diversification of the package structure on the premise of a smaller overall package volume. The arrangement of the buffer glue layer 160 can play a role in absorbing structural stress, relieving structural warpage, improving structural strength and stability, and improving heat dissipation performance. Secondly, the height of the third chip 140 is the sum of the heights of the first chip 120 and the second chip 130, so that the structure is more compact, more chips can be stacked upwards, and the stacking structure is more stable. Among the multilayer stacked structure, set up flip chip between the two-layer chip of just adorning, make full use of piles up the space, and provides more spaces for just adorning the routing of chip, and the structure is more stable, and it is more convenient to operate, and the encapsulation efficiency is high, and the encapsulation quality is good.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (11)
1. A stack package structure, comprising a substrate, a first chip, a second chip, a third chip and a fourth chip, wherein:
the first chip is arranged on the substrate in a flip-chip manner;
the second chip is arranged on one side of the first chip far away from the substrate;
the third chip is arranged on the substrate and is arranged at an interval with the first chip; a first groove is formed between the first chip and the third chip, and a buffer glue layer is filled in the first groove;
the fourth chip is arranged on one side, far away from the substrate, of the second chip and/or the third chip;
a plastic package body is arranged on the substrate to protect the first chip, the second chip, the third chip and the fourth chip;
the thermal expansion coefficient of the buffer glue layer is smaller than that of the plastic package body;
and stacking a plurality of layers of chips on one side of the fourth chip far away from the substrate, wherein the plurality of layers of chips are alternately stacked according to flip chips and normal chips, the buffer glue layer is arranged between every two adjacent layers of flip chips, the flip chips are electrically connected with the normal chips, and the normal chips are electrically connected with the substrate.
2. The stacked package structure of claim 1, wherein the first chip and the second chip are configured as a chip combination, and wherein the third chip has a height equal to a height of the chip combination.
3. The package on package structure of claim 1, wherein the fourth chip is flip-chip mounted on the second chip and the third chip; the third chip is connected with the substrate through a metal wire, the fourth chip is electrically connected with the third chip, and the second chip is electrically connected with the fourth chip.
4. The stacked package structure of claim 1, further comprising a fifth chip, wherein the fifth chip is disposed on a side of the fourth chip away from the second chip.
5. The package on package structure of claim 4, wherein the fifth chip is being mounted on the fourth chip, and the fifth chip is connected to the substrate via a metal wire.
6. The stacked package structure of claim 4, further comprising a sixth chip, wherein the sixth chip is disposed on a side of the fifth chip away from the fourth chip; and a second groove is formed between every two adjacent fifth chips, the buffer glue layer is arranged in the second groove, and the buffer glue layer is positioned between the fourth chip and the sixth chip.
7. The stacked package structure of claim 6, further comprising a seventh chip and an eighth chip, wherein the seventh chip is spaced apart from the sixth chip on a side away from the fourth chip, and a third trench is formed between two adjacent seventh chips;
the eighth chip is arranged on one side, away from the sixth chip, of the seventh chip, the eighth chip is electrically connected with the seventh chip, and the seventh chip is electrically connected with the substrate;
and the third groove is internally provided with the buffer glue layer, and the buffer glue layer is arranged between the sixth chip and the eighth chip.
8. The stacked package structure of claim 7, wherein the third trench corresponds in position to the second trench, and wherein the second trench corresponds in position to the first trench.
9. The stacked package structure of claim 1, wherein a side of the first chip close to the substrate is provided with first stud balls, the substrate is provided with first bonding pads, the first stud balls are electrically connected to the first bonding pads, and a protective adhesive is provided between the first chip and the substrate.
10. The stacked package structure of any one of claims 1 to 9, wherein an outer layer chip is disposed on a side of the third chip away from the first chip, the outer layer chip and the third chip are disposed at an interval to form a fourth groove, and the buffer glue layer is disposed in the fourth groove.
11. A method of packaging a stacked structure, comprising:
providing a substrate;
a first chip is arranged on the substrate in an inverted and pasted mode;
a second chip is positively mounted and attached on the first chip;
a third chip is arranged on the substrate in a positive mounting and sticking mode, wherein the third chip and the first chip are arranged at intervals, and the height of the third chip is equal to the sum of the height of the first chip and the height of the second chip;
filling a buffer glue layer between the first chip and the third chip;
a fourth chip is arranged on the second chip and the third chip in an inverted mode, is electrically connected with the second chip and the third chip respectively, and is arranged on one side, far away from the substrate, of the buffer glue layer;
stacking a plurality of chips on a side of the fourth chip away from the substrate, wherein: the multiple layers of chips are alternately stacked according to flip chips and forward chips, the buffer adhesive layer is arranged between two adjacent layers of flip chips, and the flip chips are electrically connected with the forward chips; a metal wire is arranged between the upright chip and the substrate;
and arranging a plastic package body on the substrate to cover all chips and circuits on the substrate, wherein the thermal expansion coefficient of the buffer glue layer is smaller than that of the plastic package body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210183320.XA CN114242669B (en) | 2022-02-28 | 2022-02-28 | Stack packaging structure and stack packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210183320.XA CN114242669B (en) | 2022-02-28 | 2022-02-28 | Stack packaging structure and stack packaging method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114242669A CN114242669A (en) | 2022-03-25 |
| CN114242669B true CN114242669B (en) | 2022-07-08 |
Family
ID=80748201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210183320.XA Active CN114242669B (en) | 2022-02-28 | 2022-02-28 | Stack packaging structure and stack packaging method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114242669B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1355568A (en) * | 2000-11-27 | 2002-06-26 | 矽品精密工业股份有限公司 | Chip stack package structure |
| TW200826286A (en) * | 2006-12-12 | 2008-06-16 | Siliconware Precision Industries Co Ltd | Sensor semiconductor device and method for fabricating the same |
| CN102623441A (en) * | 2011-01-28 | 2012-08-01 | 三星电子株式会社 | Semiconductor device and method of fabricating the same |
| CN104471708A (en) * | 2012-02-08 | 2015-03-25 | 吉林克斯公司 | Stacked die assembly with multiple interposers |
| CN104769709A (en) * | 2012-07-23 | 2015-07-08 | 马维尔国际贸易有限公司 | Methods and arrangements relating to semiconductor packages including multi-memory dies |
| KR20160093948A (en) * | 2015-01-30 | 2016-08-09 | 앰코 테크놀로지 코리아 주식회사 | Stacked chip package and method for manufacturing the same |
| JP2016162985A (en) * | 2015-03-05 | 2016-09-05 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method |
| TWI729955B (en) * | 2020-10-27 | 2021-06-01 | 力成科技股份有限公司 | Package method of modular stacked semiconductor package |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11152330B2 (en) * | 2019-04-16 | 2021-10-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package structure and method for forming the same |
| US11276620B2 (en) * | 2019-12-30 | 2022-03-15 | Advanced Semiconductor Engineering, Inc. | Package structure and method for manufacturing the same |
-
2022
- 2022-02-28 CN CN202210183320.XA patent/CN114242669B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1355568A (en) * | 2000-11-27 | 2002-06-26 | 矽品精密工业股份有限公司 | Chip stack package structure |
| TW200826286A (en) * | 2006-12-12 | 2008-06-16 | Siliconware Precision Industries Co Ltd | Sensor semiconductor device and method for fabricating the same |
| CN102623441A (en) * | 2011-01-28 | 2012-08-01 | 三星电子株式会社 | Semiconductor device and method of fabricating the same |
| CN104471708A (en) * | 2012-02-08 | 2015-03-25 | 吉林克斯公司 | Stacked die assembly with multiple interposers |
| CN104769709A (en) * | 2012-07-23 | 2015-07-08 | 马维尔国际贸易有限公司 | Methods and arrangements relating to semiconductor packages including multi-memory dies |
| KR20160093948A (en) * | 2015-01-30 | 2016-08-09 | 앰코 테크놀로지 코리아 주식회사 | Stacked chip package and method for manufacturing the same |
| JP2016162985A (en) * | 2015-03-05 | 2016-09-05 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method |
| TWI729955B (en) * | 2020-10-27 | 2021-06-01 | 力成科技股份有限公司 | Package method of modular stacked semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114242669A (en) | 2022-03-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6558978B1 (en) | Chip-over-chip integrated circuit package | |
| US6365966B1 (en) | Stacked chip scale package | |
| US6664617B2 (en) | Semiconductor package | |
| US20040262774A1 (en) | Multi-chip packages having a plurality of flip chips and methods of manufacturing the same | |
| US5910682A (en) | Semiconductor chip stack package | |
| US20040070083A1 (en) | Stacked flip-chip package | |
| US7649248B2 (en) | Stack package implementing conductive support | |
| US6844217B2 (en) | Die support structure | |
| US6969906B2 (en) | Multi-chip package and method for manufacturing the same | |
| TW200812051A (en) | Stacked structure of chips and wafer structure for making same | |
| JP4308565B2 (en) | Multichip package with improved heat dissipation characteristics | |
| KR102170197B1 (en) | Package-on-package structures | |
| US7285847B2 (en) | Chip stack package, connecting board, and method of connecting chips | |
| US6163076A (en) | Stacked structure of semiconductor package | |
| US20080258288A1 (en) | Semiconductor device stack package, electronic apparatus including the same, and method of manufacturing the same | |
| CN101477979A (en) | Multi-chip encapsulation body | |
| JP5973456B2 (en) | Semiconductor device | |
| CN114242669B (en) | Stack packaging structure and stack packaging method | |
| TWI442522B (en) | Cavity chip package structure and package-on-package using the same | |
| TWI311354B (en) | Multi-chip package structure | |
| US20040104474A1 (en) | Semiconductor package and package stack made thereof | |
| CN114446943A (en) | Semiconductor packaging structure and preparation method thereof | |
| CN207834285U (en) | Multi-chip fan-out type packaging structure | |
| CN118263207B (en) | Radiator structure of flip chip ball grid array and manufacturing method thereof | |
| CN218647928U (en) | Semiconductor packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |