CN114242594B

CN114242594B - Ring gate device and back gate single diffusion partition process method and device manufacturing method

Info

Publication number: CN114242594B
Application number: CN202111524853.1A
Authority: CN
Inventors: 刘桃; 张卫; 徐敏; 汪大伟; 孙新; 潘哲成; 吴春蕾
Original assignee: Fudan University; Shanghai IC Manufacturing Innovation Center Co Ltd
Current assignee: Fudan University; Shanghai IC Manufacturing Innovation Center Co Ltd
Priority date: 2021-12-14
Filing date: 2021-12-14
Publication date: 2024-08-16
Anticipated expiration: 2041-12-14
Also published as: CN114242594A

Abstract

The invention provides a single diffusion isolation process method of a back gate on a ring gate device, which is used for forming a dummy gate of a single diffusion isolation cavity, wherein the etching of the dummy gate is performed after the preparation of an active metal gate of a GAA device is completed, and because a source/drain region can apply stress to fin structures at two sides; after the channel is released, only the channel layer is left in the fin structure corresponding to the active dummy gate, so that the stress of the source/drain region is concentrated on the channel layer, and the stress of the channel layer is enhanced. The dummy gate and the fin structure corresponding to the dummy gate also transmit stress to the channel layer of the GAA device, so that the stress of the channel layer of the GAA device is maximized; meanwhile, before the dummy gate is etched, the channel layer of the GAA device is wrapped by the active metal gate, so that the stress of the channel layer of the GAA device is restrained, and the influence of the stress of the channel layer of the GAA device caused by relaxation is minimized after the subsequent dummy gate is etched.

Description

Ring gate device and back gate single diffusion partition process method and device manufacturing method

Technical Field

The invention relates to the field of semiconductors, in particular to a ring gate device, a back gate single diffusion isolation process method and a device preparation method.

Background

A transistor device is understood to be a switching structure made of semiconductor material. As semiconductor technology evolves, transistor devices evolve from planar transistors to FinFET transistors and back to gate-all-around transistors. The gate-all-around transistors are also understood as GAA transistors GAAFET. Wherein, GAA is fully called: gate-All-Around, a full-Around Gate technology.

The mobility of carriers is different between the N-type transistor and the P-type transistor, so that the current capability of the N-type transistor and the P-type transistor in the same size is different. Wherein for planar transistors, the electron mobility of an N-type transistor is nearly doubled over the hole mobility of a P-type transistor, this problem is solved by adjusting the carrier mobility of the N-type transistor channel and the P-type transistor channel by a source-drain silicon germanium (SiGe) stress technique of the planar transistor. When the FinFE transistor is developed, the carrier mobility of the N-type transistor and the carrier mobility of the P-type transistor are not greatly different. When the mobility of the N-type transistor is greatly improved and the mobility of the hole of the P-type transistor is reduced when the mobility of the N-type transistor is developed to the GAA transistor, the carrier mobility of the N-type GAA transistor and the carrier mobility of the P-type GAA transistor are greatly different. Thus the current matching problem is very pronounced when integrating N-type GAA transistors with P-type GAA transistors. At the same time, the sensitivity of hole mobility to stress increases and the sensitivity of electron mobility to stress decreases, which increases the stress requirements on GAA transistors.

Below the 7nm technology node, single diffusion barriers (Single diffusion break, SDB) have replaced double diffusion barriers (Double diffusion break, DDB) to further increase transistor density. Both conventional SDB and self-aligned SDB (SA-SDB) schemes cause channel stress relaxation to varying degrees.

Therefore, how to solve the problem of stress relaxation in the single diffusion partition process has become a technical problem to be solved in the industry.

Disclosure of Invention

The invention provides a ring gate device, a single diffusion isolation process method of a rear gate and a device preparation method, which are used for reducing stress relaxation in the single diffusion isolation process and improving the device performance.

According to a first aspect of the present invention, there is provided a method of performing a back gate single diffusion barrier process on a ring gate device, comprising:

Providing a substrate structure;

forming a plurality of fin structures on the substrate structure, wherein the fin structures are arranged on the substrate structure along a first direction, and shallow trench isolation structures are arranged between every two adjacent fin structures; each fin structure of the plurality of fin structures includes a sacrificial layer and a channel layer alternately stacked;

forming a plurality of dummy gate structures on each fin structure along a second direction, the dummy gate structures crossing the corresponding fin structures; the dummy gate structure comprises a dummy gate and an active dummy gate; the second direction is perpendicular to the first direction;

performing source/drain etching on the fin structure by taking the pseudo gate structure as a mask to form a source/drain cavity;

A source/drain layer is epitaxially grown in the source/drain cavity to form a source/drain region;

Removing the active dummy gate and the sacrificial layer in the fin structure corresponding to the active dummy gate, and releasing a channel;

Forming an active metal gate;

Etching the dummy gate and the fin structure covered by the dummy gate until part of the substrate structure is etched away to form a single diffusion partition cavity; and

And forming a diffusion isolation layer in the single diffusion partition cavity.

Optionally, the forming a plurality of fin structures on the substrate structure specifically includes:

forming a stack on the substrate structure, the stack including sacrificial layers and channel layers alternately stacked;

And carrying out fin structure etching on the stacked piece to form a fin structure.

Optionally, before the source/drain etching is performed on the fin structure by using the gate structure as a mask to form a source/drain cavity, the method further includes: a spacer layer is deposited over the dummy gate structure.

Optionally, the source/drain layer is epitaxially formed in the source/drain cavity, and before forming the source/drain region, the method further comprises:

etching the sacrificial layer exposed on the surface after source drain etching to enable part of the sacrificial layer to be sunken;

an inner spacer layer is formed in the recessed region.

Optionally, the source/drain layer is epitaxially formed in the source/drain cavity, and after forming the source/drain region, the method further comprises:

an interlayer dielectric is deposited over the substrate structure, the interlayer dielectric overlying the source/drain regions.

Optionally, the forming the active metal gate specifically includes:

depositing a high dielectric constant dielectric on the channel layer after releasing the channel; and

A metal gate is deposited over the high-k dielectric.

According to a second aspect of the present invention, a method for manufacturing a gate-all-around device is further provided, including the method for performing a back-gate single diffusion isolation process on the gate-all-around device.

Optionally, the method for manufacturing the ring gate device further includes, after forming the diffusion isolation layer in the single diffusion isolation cavity: forming a device contact.

According to a third aspect of the present invention, there is also provided a gate-all-around device, which is manufactured by the above-mentioned method for manufacturing a gate-all-around device.

The etching of the dummy gate used for forming the single diffusion blocking cavity is performed after the preparation of the active metal gate of the GAA device is completed, and because the source/drain regions apply stress to fin structures (the fin structures corresponding to the active dummy gate and the fin structures corresponding to the dummy gate) on two sides; after the channel is released, only the channel layer is left in the fin structure corresponding to the active dummy gate, so that the stress of the source/drain region is concentrated on the channel layer, and the stress of the channel layer is enhanced. The dummy gate and the fin structure corresponding to the dummy gate also transmit stress to the channel layer of the GAA device, so that the stress of the channel layer of the GAA device is maximized; meanwhile, before the dummy gate is etched, the channel layer of the GAA device is wrapped by the active metal gate, and the high-dielectric-constant dielectric material in the active metal gate is not easy to deform, so that the stress of the channel layer is subjected to a confinement effect, and the influence of the stress of the channel layer of the GAA device caused by relaxation is reduced to the minimum after the subsequent dummy gate is etched. Effectively solves the problem of stress relaxation in the existing single diffusion partition process.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.

FIG. 1 is a schematic flow chart of a method for performing a back gate single diffusion barrier process on a gate-all-around device according to an embodiment of the present invention;

FIG. 2 is a schematic flow chart II of a method for performing a back gate single diffusion barrier process on a gate-all-around device according to an embodiment of the present invention;

fig. 3 to fig. 15 are partial schematic views of device structures corresponding to steps of a post gate single diffusion isolation process method on a gate-all-around device according to an embodiment of the present invention.

FIG. 16 is a graph of the stress simulation effect of the steps of the post gate single diffusion barrier process method of the present invention and a conventional single diffusion barrier process and self-aligned single diffusion barrier process for a P-type GAA device;

fig. 17 is a schematic structural diagram of a completed device fabricated by a back gate single diffusion barrier process.

Reference numerals illustrate:

1-a local device repeatable unit;

a 101-substrate structure;

110-fin structure;

111-a sacrificial layer;

112-a channel layer;

130-dummy gate stack;

131-active dummy gate;

132-dummy gate;

140-spacer layer;

150-source/drain cavities;

141-an inner spacer layer;

151-source/drain layers;

160-interlayer dielectric;

170-high-K gate dielectric;

180-a diffusion barrier layer;

A-A, B-cross-section lines;

a-stress simulation curves corresponding to the steps of the traditional single diffusion partition process;

b-stress simulation curves corresponding to the steps of the self-aligned single diffusion separation process;

c-stress simulation curves corresponding to the steps of the back gate single diffusion partition process method.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In the description of the present specification, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower surface", "upper surface", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description and simplification of description, and do not indicate or imply that the apparatus or element to be referred to must have a specific direction, be configured and operated in a specific direction, and thus should not be construed as limiting the present invention.

In the description of the present specification, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature.

In the description of the present invention, the meaning of "plurality" means a plurality, for example, two, three, four, etc., unless explicitly specified otherwise.

In the description of the present invention, unless explicitly stated and limited otherwise, the term "coupled" and the like should be construed broadly, and may be, for example, fixedly coupled, detachably coupled, or integrally formed; may be mechanically connected, may be electrically connected or may communicate with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.

The technical scheme of the invention is described in detail below by specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.

Before the invention is put forward, the applicant fully researches the single diffusion partition process of the GAA device of the advanced node, and the single diffusion partition process for the GAA device at present mainly comprises the following steps:

1. traditional single diffusion partition process

The specific flow of the process is as follows:

a. Epitaxial fin structure stacks (sacrificial layers/channel layers alternating) on the substrate structure;

b. patterning the fin structure stack;

c. etching the fin structure and cutting off the fin structure to form the fin structure and a single diffusion partition cavity;

d. filling an isolation layer to form an STI and a diffusion isolation layer;

e. Forming a dummy gate over the fin structure;

f. Source/drain etching and forming a source/drain region;

g. forming an interlayer dielectric;

h. Removing the pseudo grid electrode;

i. Removing the sacrificial layer and releasing the channel;

j. Forming a high-K gate dielectric;

k. Forming a metal contact.

2. Self-aligned single diffusion barrier process

The process is similar to conventional processes in that the step of forming a single diffusion barrier cavity is interposed between the step of forming an interlayer dielectric and the step of removing the dummy gate.

For GAA devices, the stress of the source/drain regions to the channel layer is critical to the performance of the device. For both processes, however, the applicant has found that there is a different degree of stress relaxation. To clarify the cause of stress relaxation, applicants have performed a series of stress simulations to find that both processes described above, after forming a single diffusion barrier cavity, have different degrees of stress relaxation such that the stress of the final channel layer is maintained at a low level.

After further follow-up of stress simulation of the individual process steps and research analysis, the applicant found that the reason for stress relaxation caused by the two processes is: both processes can cause free surfaces to be formed at both ends of the channel layer when forming the single diffusion barrier cavity, and stress is relaxed by the channels of the free surfaces, so that the stress of the final channel layer is lower.

Based on this, the applicant creatively proposes a new process method of single diffusion isolation of back gate on a gate-all-around device according to the requirement of GAA device, please refer to fig. 1, and combine fig. 3 to 15, wherein fig. 1 is a schematic flow diagram of the single diffusion isolation process method of back gate on a gate-all-around device according to an embodiment of the present invention; fig. 3 to fig. 15 are schematic device structures corresponding to steps of a method for performing a back gate single diffusion isolation process on a ring gate device according to an embodiment of the present invention. Wherein fig. 4 is a schematic cross-sectional view of fig. 3 taken along a cross-sectional line B-B, fig. 5 is a schematic cross-sectional view of fig. 3 taken along a cross-sectional line A-A, and fig. 6-15 are schematic device structure diagrams at different process steps shown on the basis of fig. 5.

Referring to fig. 1 and fig. 3 to fig. 15, the method for performing single diffusion isolation on a back gate on a ring gate device according to the embodiment of the invention includes the following steps:

S1, providing a substrate structure 101.

The substrate structure 101 may be a silicon substrate or a strain relaxed buffer layer (SRB, strain Relaxed Buffer), but may be other substrates. As long as the substrate structure meeting the GAA device requirements is within the scope of the present invention.

S2, forming a plurality of fin structures 110 on the substrate structure 101, wherein the fin structures 110 are arranged on the substrate structure 101 along a first direction, as shown in FIG. 3; the first direction in fig. 3 may be understood as a direction perpendicular to the channel direction of the final GAA device, and the second direction may be understood as a direction along the channel of the final GAA device, such that the first direction is perpendicular to the second direction.

A shallow trench isolation (STI, shallow Trench Isolation) structure 120 is disposed between each adjacent fin structure 110, and each fin structure 110 in the plurality of fin structures includes a sacrificial layer 111 and a channel layer 112 that are alternately stacked, as shown in fig. 4.

Four fin structures are shown in fig. 3 and 4 as an example, and in fact, after this step is completed, a plurality of fin structures are formed on the underlying structure, and the number is not limited to four, but may be other numbers.

In one embodiment, the forming the plurality of fin structures on the substrate structure further comprises:

Forming a stack including sacrificial layers 111 and channel layers 112 alternately stacked on the substrate structure 101;

The stack is fin structure etched to form fin structure 110. And the adjacent fin structures 110 are isolated by shallow trench isolation structures 120.

S3: forming a plurality of dummy gate structures on each fin structure along a second direction, the dummy gate structures crossing the corresponding fin structures; the dummy gate structure includes a dummy gate 132 and an active dummy gate 131 as shown in fig. 6.

Specifically, step S3 may include the following sub-steps:

first forming a plurality of dummy gate stacks 130 on each fin structure along a second direction, as shown in fig. 5; the dummy gate stack 130 spans the corresponding fin structure, in particular, the dummy gate stack 130 covers the top and both sides of the fin structure;

Then, the dummy gate stack 105 is etched to form a plurality of dummy gate structures, as shown in fig. 6; the plurality of dummy gate structures are sequentially distributed along the second direction. The dummy gate structure can be divided into a dummy gate 132 and an active dummy gate 131 according to the effect, wherein the dummy gate 132 is finally etched to form a single diffusion isolation cavity; the active dummy gate 131 therein is eventually etched to form an active metal gate. The dummy gate structure may be made of a metal gate material, and in particular, may be made of different metal gate materials according to the type of the ions doped in the corresponding region.

As a preferred embodiment, as shown in fig. 2, after forming the plurality of dummy gate structures, the method further includes step S31: a spacer layer 140 is deposited over the dummy gate structure and a schematic of the device structure after this step is completed is shown in fig. 7.

S4: performing source/drain etching on the fin structure by taking the pseudo gate structure as a mask to form a source/drain cavity 150; the etched device structure is shown in fig. 8.

As a preferred embodiment, as shown in FIG. 2, the method further comprises a step S41 of forming an inner spacer layer after the step S4; specifically, step S41 includes the following sub-steps:

etching the sacrificial layer 111 exposed on the surface after source drain etching to partially recess the sacrificial layer;

forming an inner spacer layer 141 in the recessed region; a schematic diagram of the device structure after this step is completed is shown in fig. 9.

S5: a source/drain layer is epitaxially formed within the source/drain cavity 150 to form a source/drain region 151.

As a preferred embodiment, as shown in fig. 2, after forming the source/drain regions 151, step S51 is further included: depositing an interlayer dielectric 160; specifically comprising:

depositing an interlayer dielectric 160 on the substrate structure, the interlayer dielectric 160 covering the source/drain regions 151;

The deposited interlayer dielectric 160 is planarized, and in particular, chemical mechanical polishing may be performed such that the deposited interlayer dielectric 160 is planarized. A schematic diagram of the device structure after this step is completed is shown in fig. 10.

S6: the active dummy gate 131 and the sacrificial layer 111 in the fin structure corresponding to the active dummy gate 131 are removed, and channel release is performed. Specifically, the method comprises the following substeps:

The active dummy gate 131 is removed, and the schematic device structure after this step is completed is shown in fig. 11; wherein the active dummy gate 131 may be removed through an etching process;

the sacrificial layer 111 in the corresponding fin structure is removed, and a schematic diagram of the device structure after this step is completed is shown in fig. 12; wherein the sacrificial layer 111 may be removed by an etching process.

S7: an active metal gate is formed. The method specifically comprises the following steps:

Depositing a high dielectric constant dielectric 170 on the channel layer 112 after the releasing the channel; a schematic diagram of the device structure after this step is completed is shown in fig. 13; and

A metal gate (not shown) is deposited over the high-k dielectric 170.

The high-k dielectric 170 may be a conventional high-k dielectric material.

S8: etching the dummy gate 132 and the fin structure covered by the dummy gate until a part of the substrate structure is etched away to form a single diffusion partition cavity; a schematic diagram of the device structure after this step is completed is shown in fig. 14; and

Forming a diffusion barrier 180 in the single diffusion barrier cavity; a schematic of the device structure after this step is completed is shown in fig. 15. The diffusion isolation layer 180 may be an insulating layer, such as silicon dioxide.

For comparison with the existing single diffusion partition process, the applicant performs stress simulation tracking on each corresponding step for each process method, please refer to fig. 16, wherein curve a is a stress simulation curve corresponding to each step of the conventional single diffusion partition process; curve b is a stress simulation curve corresponding to each step of the self-aligned single diffusion partition process; curve c is a stress simulation curve corresponding to each step of the back gate single diffusion partition process method; the ordinate of fig. 16 characterizes the stress magnitude, and the abscissa thereof characterizes the respective process steps; SDB in the figure represents a single diffusion barrier step (i.e., forming a single diffusion barrier cavity). As can be seen from fig. 16, for the P-type GAA device, after SDB is formed, the stress level of the P-type GAA device is about 1.5GPa, and the stress level of the subsequent channel layer is maintained at about-1 GPa; after SDB is formed in the curve b, the stress is about 1GPa, and the stress of the subsequent channel layer is maintained about 0 GPa; in curve c, after SDB is formed, the stress level is around-4.4 GPa, and the stress level of the subsequent channel layer is maintained around-4.4 GPa. Therefore, the channel stress of the rear gate single diffusion partition process method is obviously improved.

Similarly, for N-type GAA devices, the applicant also carried out stress simulation of each process step, and the channel stress is improved to about +3.2GPa by adopting the back gate single diffusion isolation process method. Also a significant improvement is obtained.

It should be noted that, fig. 3 to fig. 15 are only schematic structural diagrams illustrating a partial device manufactured by the back gate single diffusion blocking process on the ring gate device of the present application, and in actual cases, one or more active dummy gates are typically present between two dummy gates along the channel length direction in the single diffusion blocking process. In the present application, the case where an active dummy gate exists between two dummy gates is schematically illustrated, and referring to fig. 17, the local device repeatable unit 1 in fig. 17 is the structure illustrated in fig. 3-15. The complete repeatable unit shown in fig. 17 is a structure in which one active dummy gate exists between two dummy gates; wherein the local device repeatable unit 1 is half of a complete repeatable unit.

According to a second aspect of the present invention, a method for manufacturing a gate-all-around device is further provided, including the method for performing a back-gate single diffusion isolation process on the gate-all-around device. The preparation method of the ring gate device further comprises the following steps of: forming a device contact.

In the description of the present specification, the descriptions of the terms "one embodiment," "an embodiment," "a particular implementation," "an example," and the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A single diffusion separation process method for a rear gate on a ring gate device is characterized by comprising the following steps:

Providing a substrate structure;

forming an active metal gate, specifically including:

Depositing a metal gate over the high-k dielectric;

2. The method of claim 1, wherein forming a plurality of fin structures on the substrate structure comprises:

3. The method of claim 1, wherein before the step of performing source/drain etching on the fin structure with the dummy gate structure as a mask to form a source/drain cavity, further comprises: a spacer layer is deposited over the dummy gate structure.

4. The method of claim 1, wherein the step of epitaxially forming a source/drain layer in the source/drain cavity, prior to forming a source/drain region, further comprises:

an inner spacer layer is formed in the recessed region.

5. The method of claim 1, wherein the step of forming a source/drain region in the source/drain cavity by epitaxially forming a source/drain layer further comprises:

6. A method for preparing a gate-all-around device, comprising the method for performing a single diffusion barrier process on a gate-all-around device according to any one of claims 1 to 5.

7. The method of manufacturing a ring gate device of claim 6, further comprising, after forming a diffusion barrier layer in the single diffusion barrier cavity:

Forming a device contact.

8. A gate-all-around device prepared by the method of claim 6.