CN114221540B - Boost circuit and amplifier - Google Patents
Boost circuit and amplifier Download PDFInfo
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- CN114221540B CN114221540B CN202111546653.6A CN202111546653A CN114221540B CN 114221540 B CN114221540 B CN 114221540B CN 202111546653 A CN202111546653 A CN 202111546653A CN 114221540 B CN114221540 B CN 114221540B
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- supply voltage
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- 238000000034 method Methods 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses a booster circuit and an amplifier, wherein the booster circuit comprises: switching tube, voltage circuit and control circuit. The switching tube is connected with the power supply voltage and the output end; the voltage circuit receives zero temperature coefficient current and provides a comparison voltage; the control circuit is connected between the power supply voltage and the voltage circuit and is connected with the switching tube at the same time, when the power supply voltage is larger than the comparison voltage, the output end outputs the comparison voltage, and when the power supply voltage is smaller than the comparison voltage, the control circuit controls the switching tube to be turned off through the control end, and the output end outputs the power supply voltage. According to the boost circuit provided by the embodiment of the invention, the comparison voltage VB and the power supply voltage VDD are compared, and the output end outputs the high voltage of the comparison voltage and the power supply voltage under the condition that the comparison voltage VB and the power supply voltage VDD are not exceeded, wherein the comparison voltage is mainly influenced by the zero temperature coefficient voltage, so that the influence of a process can be avoided, the accurate boost is realized, and the precision is improved.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly to a booster circuit and an amplifier.
Background
The booster circuit is one of circuit structures commonly used in an amplifier. The existing boost circuit is complex in structure and high in cost, and meanwhile the boost size is easily affected by the process, so that the accuracy of the boost of the whole circuit is uncertain.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide a booster circuit and an amplifier, wherein the boosting precision is not affected by a process.
To achieve the above object, an embodiment of the present invention provides a booster circuit including: switching tube, voltage circuit and control circuit.
The switching tube is connected with the power supply voltage VDD and the output end VOUT; the voltage circuit receives zero temperature coefficient current and provides a comparison voltage VB; the control circuit is connected between the power supply voltage VDD and the voltage circuit and is connected with the switch tube at the same time, when the power supply voltage VDD is larger than the comparison voltage VB, the output end VOUT outputs the comparison voltage VB, and when the power supply voltage VDD is smaller than the comparison voltage VB, the control circuit controls the switch tube to be conducted through the control end VGP, and the output end VOUT outputs the power supply voltage VDD.
In one or more embodiments of the present invention, the switch tube is a PMOS tube MP, a source of the PMOS tube MP is connected to the power supply voltage VDD, a gate of the PMOS tube MP is connected to the control terminal VGP, and a drain of the PMOS tube MP is connected to the output terminal VOUT.
In one or more embodiments of the present invention, the voltage circuit includes a PMOS transistor M3, a PMOS transistor M4, and a resistor R1, where a source of the PMOS transistor M3 is connected to one end of the resistor R1 and receives a zero temperature coefficient current at the same time, another end of the resistor R1 is connected to a source of the PMOS transistor M4, a gate of the PMOS transistor M3 is connected to the output terminal VOUT, and a gate of the PMOS transistor M4 is connected to the input terminal VIN.
In one or more embodiments of the present invention, the comparison voltage vb=v IN +IM 4R 1, where V IN For the voltage input at input VIN, IM4 is zero temperature coefficient current flowing through resistor R1.
In one or more embodiments of the present invention, the control circuit includes a first current mirror, a current source I1, an NMOS tube M5 and an NMOS tube M6, where the first current mirror is connected to the power supply voltage VDD and the voltage circuit, a drain electrode of the NMOS tube M5 is connected to the gate and one end of the current source I1, a source electrode of the NMOS tube M5 is connected to the other end of the current source I1 and grounded, a gate electrode of the NMOS tube M6 is connected to the gate electrode of the NMOS tube M5, a source electrode of the NMOS tube M6 is grounded, and a drain electrode of the NMOS tube M6 is connected to the control terminal VGP.
In one or more embodiments of the present invention, the first current mirror includes a PMOS transistor M1 and a PMOS transistor M2, where a source of the PMOS transistor M1 is connected to a source of the PMOS transistor M2 and to a power supply voltage VDD, a gate of the PMOS transistor M1 is connected to a gate of the PMOS transistor M2, a drain of the PMOS transistor M1 is connected to a drain of the NMOS transistor M5, and a drain of the NMOS transistor M2 is connected to a voltage circuit.
In one or more embodiments of the invention, the boost circuit further comprises a zero temperature coefficient current circuit generating a zero temperature coefficient current, the zero temperature coefficient current circuit being connected between the supply voltage VDD and the control circuit.
In one or more embodiments of the present invention, the zero temperature coefficient current circuit includes an amplifier OPA0, an NMOS tube M0, a current mirror, and a resistor R0, wherein an anode input terminal of the amplifier OPA0 is connected to a reference voltage VREF, a cathode input terminal of the amplifier OPA0 is grounded through the resistor R0, a cathode input terminal of the amplifier OPA0 is connected to a source terminal of the NMOS tube M0, a gate terminal of the NMOS tube M0 is connected to an output terminal of the amplifier OPA0, a drain terminal of the NMOS tube M0 is connected to a current mirror, and the current mirror is connected to a power supply voltage VDD and a control circuit.
In one or more embodiments of the present invention, the current mirror includes a PMOS transistor MS0 and a PMOS transistor MS1, where a drain and a gate of the PMOS transistor MS0 are connected to each other and to a drain of the NMOS transistor M0 and a gate of the PMOS transistor MS1, a source of the PMOS transistor MS0 is connected to a source of the PMOS transistor MS1 and to a power supply voltage VDD, and a drain of the PMOS transistor MS1 is connected to a control circuit.
The invention also provides an amplifier comprising the booster circuit.
Compared with the prior art, according to the booster circuit and the amplifier provided by the embodiment of the invention, the comparison voltage VB and the power supply voltage VDD are compared, and under the condition that the comparison voltage VB and the power supply voltage VDD are not exceeded, the output end VOUT outputs high voltage in the comparison voltage VB and the power supply voltage VDD, and the comparison voltage VB is mainly influenced by zero temperature coefficient voltage, so that the influence of a process can be avoided, the accurate boosting is realized, and the precision is improved.
Drawings
FIG. 1 is a schematic circuit diagram of a boost circuit according to one embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of a zero temperature coefficient current circuit according to one embodiment of the present invention;
fig. 3 is a system block diagram of an amplifier OPA according to an embodiment of the invention.
Detailed Description
The following detailed description of embodiments of the invention is, therefore, to be taken in conjunction with the accompanying drawings, and it is to be understood that the scope of the invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations thereof such as "comprises" or "comprising", etc. will be understood to include the stated element or component without excluding other elements or components.
Example 1
As shown in fig. 1, the booster circuit includes: a switching tube, a zero temperature coefficient current circuit 10, a voltage circuit 20 and a control circuit 30.
The switching tube is connected with the power supply voltage VDD and the output end VOUT. The zero temperature coefficient current circuit 10, the voltage circuit 20 and the control circuit 30 are sequentially connected, the zero temperature coefficient current circuit 10 is simultaneously connected with the power supply voltage VDD, and the voltage circuit 20 is simultaneously connected with the input terminal VIN, the output terminal VOUT and the internal circuit 40 of the amplifier OPA. The voltage circuit 20 receives the zero temperature coefficient current generated by the zero temperature coefficient current circuit 10 and provides a comparison voltage VB. The control circuit 30 is used for controlling the on and off of the switching tube. When the power supply voltage VDD is greater than the comparison voltage VB, the output terminal VOUT outputs the comparison voltage VB, and when the power supply voltage VDD is less than the comparison voltage VB, the control circuit 30 controls the switch tube to be turned on through the control terminal VGP, and the output terminal VOUT outputs the power supply voltage VDD, so that the voltage output by the output terminal VOUT does not exceed the power supply voltage VDD.
As shown in fig. 1, the switch tube is a PMOS tube MP, a source of the PMOS tube MP is connected to the power voltage VDD, a gate of the PMOS tube MP is connected to the control terminal VGP and is connected to the internal circuit 40 of the amplifier OPA through the control terminal VGP, and a drain of the PMOS tube MP is connected to the output terminal VOUT. The booster circuit is a part of the amplifier OPA, and the internal circuit 40 of the amplifier OPA is composed of a plurality of connected NMOS transistors and PMOS transistors, and the internal circuit 40 is used for maintaining the operation of the booster circuit and other circuits.
As shown in fig. 2 and 1, the zero temperature coefficient current circuit 10 includes an amplifier OPA0, an NMOS transistor M0, a current mirror, and a resistor R0. The positive input end of the amplifier OPA0 is connected with the reference voltage VREF, the negative input end of the amplifier OPA0 is grounded through a resistor R0, and the negative input end of the amplifier OPA0 is connected with the source electrode of the NMOS tube M0. The gate of the NMOS tube M0 is connected with the output end of the amplifier OPA0, the drain of the NMOS tube M0 is connected with a current mirror, and the current mirror is connected with the power supply voltage VDD and the control circuit 30.
The current mirror comprises a PMOS tube MS0 and a PMOS tube MS1, wherein the drain electrode and the grid electrode of the PMOS tube MS0 are connected and connected with the drain electrode of the NMOS tube M0 and the grid electrode of the PMOS tube MS1, the source electrode of the PMOS tube MS0 is connected with the source electrode of the PMOS tube MS1 and the power supply voltage VDD, and the drain electrode of the PMOS tube MS1 is connected with the control circuit 30 through a VS2 end. The zero temperature coefficient current is equal to the reference voltage VREF divided by the resistance of the resistor R0. The zero temperature coefficient current flows through the VS2 terminal to the voltage circuit 20.
As shown in fig. 1, the voltage circuit 20 includes a PMOS transistor M3, a PMOS transistor M4, and a resistor R1. The source of the PMOS transistor M3 is connected to one end of the resistor R1 and receives the zero temperature coefficient current at the same time, and specifically, the source of the PMOS transistor M3 is connected to one end of the resistor R1 and connected to the control circuit 30 through the VD2 end. The other end of the resistor R1 is connected with the source electrode of the PMOS tube M4, the grid electrode of the PMOS tube M3 is connected with the output end VOUT, and the grid electrode of the PMOS tube M4 is connected with the input end VIN. The PMOS tube M3 and the PMOS tube M4 are both PMOS tubes, so that rail-to-rail input is realized, and the circuit cost is reduced.
Comparison voltage vb=v IN +IM 4R 1, where V IN For the voltage input at input VIN, IM4 is zero temperature coefficient current flowing through resistor R1. The zero temperature coefficient current is determined by the reference voltage VREF and the resistor R0. Namely, the voltage on the resistor R1 is mainly influenced by the reference voltage VREF, so that accurate boosting can be realized, the process influence is avoided, and the precision is improved.
As shown in fig. 1, the control circuit 30 includes a first current mirror, a current source I1, an NMOS transistor M5, and an NMOS transistor M6. The first current mirror is connected to the supply voltage VDD and the voltage circuit 20, and in this embodiment, a zero temperature coefficient current circuit 10 is connected between the first current mirror and the supply voltage VDD. The drain electrode of the NMOS tube M5 is connected with the grid electrode, one end of the current source I1 and the first current mirror, the source electrode of the NMOS tube M5 is connected with the other end of the current source I1 and is grounded, the grid electrode of the NMOS tube M6 is connected with the grid electrode of the NMOS tube M5, the source electrode of the NMOS tube M6 is grounded, and the drain electrode of the NMOS tube M6 is connected with the grid electrode of the PMOS tube MP through the control end VGP.
The first current mirror comprises a PMOS tube M1 and a PMOS tube M2. The source of the PMOS transistor M1 is connected to the source of the PMOS transistor M2 and to the power supply voltage VDD, and in this embodiment, the source of the PMOS transistor M1 is connected to the source of the PMOS transistor M2 and to the VS2 terminal connected to the drain of the PMOS transistor MS 1. The grid electrode of the PMOS tube M1 is connected with the grid electrode of the PMOS tube M2 and forms a VG2 end. The drain of the PMOS tube M1 is connected with the drain of the NMOS tube M5 and forms a VG5 end. The drain electrode of the NMOS tube M2 is connected with a resistor R1 and the source electrode of the PMOS tube M3 through the VD2 end.
According to the boosting circuit, when the power supply voltage VDD is greater than the comparison voltage VB, the NMOS transistor M6 is turned off when the output terminal OUT outputs the comparison voltage VB by setting the current of the current source I1 to be smaller than the current through the PMOS transistor M1, and the terminal VG5 is low.
When the power supply voltage VDD is smaller than the comparison voltage VB, the PMOS transistor M2 enters the linear region, the difference between the voltage at the VS2 end and the voltage at the VG2 end becomes larger, the current passing through the PMOS transistor M1 is larger than the current of the current source I1, the NMOS transistor M6 is turned on to make the VGP end be low voltage, the PMOS transistor MP is turned on, and the output end OUT outputs the power supply voltage VDD.
As shown in fig. 3, in other embodiments, an amplifier OPA is further provided, including the boosting circuit described above. The booster circuit is part of the amplifier OPA. The output VOUT of the amplifier OPA is connected to the negative input of the amplifier OPA. The positive input of the amplifier OPA is connected to the input VIN.
The foregoing descriptions of specific exemplary embodiments of the present invention are presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application to thereby enable one skilled in the art to make and utilize the invention in various exemplary embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (9)
1. A booster circuit, characterized by comprising:
the switching tube is connected with the power supply voltage VDD and the output end VOUT;
the voltage circuit receives zero temperature coefficient current and provides a comparison voltage VB; and
the control circuit is connected between the power supply voltage VDD and the voltage circuit and is simultaneously connected with the switch tube, when the power supply voltage VDD is larger than the comparison voltage VB, the output end VOUT outputs the comparison voltage VB, and when the power supply voltage VDD is smaller than the comparison voltage VB, the control circuit controls the switch tube to be conducted through the control end VGP, and the output end VOUT outputs the power supply voltage VDD;
the voltage circuit comprises a PMOS tube M3, a PMOS tube M4 and a resistor R1, wherein the source electrode of the PMOS tube M3 is connected with one end of the resistor R1 and simultaneously receives zero temperature coefficient current, the other end of the resistor R1 is connected with the source electrode of the PMOS tube M4, the grid electrode of the PMOS tube M3 is connected with an output end VOUT, and the grid electrode of the PMOS tube M4 is connected with an input end VIN.
2. The boost circuit of claim 1 wherein the switch tube is a PMOS tube MP, a source of the PMOS tube MP is connected to the power supply voltage VDD, a gate of the PMOS tube MP is connected to the control terminal VGP, and a drain of the PMOS tube MP is connected to the output terminal VOUT.
3. The boost circuit of claim 1, wherein said comparison voltage VB = V IN +IM 4R 1, where V IN For the voltage input at input VIN, IM4 is zero temperature coefficient current flowing through resistor R1.
4. The boost circuit of claim 1 wherein said control circuit comprises a first current mirror, a current source I1, an NMOS transistor M5 and an NMOS transistor M6, said first current mirror is connected to a power supply voltage VDD and a voltage circuit, a drain of said NMOS transistor M5 is connected to a gate and one end of said current source I1 and said first current mirror, a source of said NMOS transistor M5 is connected to another end of said current source I1 and to ground, a gate of said NMOS transistor M6 is connected to a gate of said NMOS transistor M5, a source of said NMOS transistor M6 is grounded, and a drain of said NMOS transistor M6 is connected to a control terminal VGP.
5. The boost circuit of claim 4 wherein said first current mirror comprises a PMOS transistor M1 and a PMOS transistor M2, wherein a source of said PMOS transistor M1 is connected to a source of said PMOS transistor M2 and to a power supply voltage VDD, a gate of said PMOS transistor M1 is connected to a gate of said PMOS transistor M2, a drain of said PMOS transistor M1 is connected to a drain of said NMOS transistor M5, and a drain of said NMOS transistor M2 is connected to a voltage circuit.
6. The boost circuit of claim 1, wherein said boost circuit further comprises a zero temperature coefficient current circuit generating a zero temperature coefficient current, said zero temperature coefficient current circuit being connected between a supply voltage VDD and a control circuit.
7. The booster circuit of claim 6 wherein said zero temperature coefficient current circuit comprises an amplifier OPA0, an NMOS tube M0, a current mirror, a resistor R0, wherein the positive input terminal of said amplifier OPA0 is connected to a reference voltage VREF, the negative input terminal of said amplifier OPA0 is grounded through said resistor R0, the negative input terminal of said amplifier OPA0 is connected to the source of said NMOS tube M0, the gate of said NMOS tube M0 is connected to the output terminal of said amplifier OPA0, the drain of said NMOS tube M0 is connected to a current mirror, and said current mirror is connected to a supply voltage VDD and a control circuit.
8. The boost circuit of claim 7 wherein said current mirror comprises a PMOS tube MS0 and a PMOS tube MS1, wherein the drain and gate of said PMOS tube MS0 are connected to the drain of said NMOS tube M0 and the gate of said PMOS tube MS1, the source of said PMOS tube MS0 is connected to the source of said PMOS tube MS1 and to the supply voltage VDD, and the drain of said PMOS tube MS1 is connected to the control circuit.
9. An amplifier comprising a boost circuit as claimed in any one of claims 1 to 8.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111546653.6A CN114221540B (en) | 2021-12-16 | 2021-12-16 | Boost circuit and amplifier |
| PCT/CN2022/139331 WO2023109908A1 (en) | 2021-12-16 | 2022-12-15 | Booster circuit, buck circuit and amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111546653.6A CN114221540B (en) | 2021-12-16 | 2021-12-16 | Boost circuit and amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114221540A CN114221540A (en) | 2022-03-22 |
| CN114221540B true CN114221540B (en) | 2023-12-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111546653.6A Active CN114221540B (en) | 2021-12-16 | 2021-12-16 | Boost circuit and amplifier |
Country Status (1)
| Country | Link |
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| CN (1) | CN114221540B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023109908A1 (en) * | 2021-12-16 | 2023-06-22 | 思瑞浦微电子科技(上海)有限责任公司 | Booster circuit, buck circuit and amplifier |
| CN114489214B (en) * | 2022-03-28 | 2022-07-12 | 苏州贝克微电子股份有限公司 | Circuit structure capable of reducing input-output voltage difference |
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| KR101221799B1 (en) * | 2005-11-21 | 2013-01-14 | 페어차일드코리아반도체 주식회사 | Current sensing circuit and boost converter including the same |
| US8179115B2 (en) * | 2009-07-15 | 2012-05-15 | AiceStar Technology (Suzhou) Corporation | Bandgap circuit having a zero temperature coefficient |
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- 2021-12-16 CN CN202111546653.6A patent/CN114221540B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7301321B1 (en) * | 2006-09-06 | 2007-11-27 | Faraday Technology Corp. | Voltage reference circuit |
| CN101136248A (en) * | 2006-10-12 | 2008-03-05 | 中兴通讯股份有限公司 | Charge pump output high-pressure control device |
| TW201336226A (en) * | 2012-02-24 | 2013-09-01 | Novatek Microelectronics Corp | Multi power domain operational amplifier and voltage generator using the same |
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| Publication number | Publication date |
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| CN114221540A (en) | 2022-03-22 |
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