CN114185486B - Data writing method of DRAM memory and DRAM control system - Google Patents
Data writing method of DRAM memory and DRAM control system Download PDFInfo
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Abstract
The invention discloses a data writing method and a system of a DRAM, wherein the method comprises the following steps: the method comprises the steps that a DRAM controller receives data to be written, wherein the data to be written comprises a data segment and an address segment, and the data segment corresponds to the address segment; judging whether the length of the continuous logic value of the data segment is larger than or equal to the preset length, wherein the continuous logic value is continuous 0 or 1; if the length of the continuous logic value is greater than or equal to the preset length, a lookup table is obtained, wherein the lookup table comprises the continuous logic value stored in the DRAM memory and an address range where the stored continuous logic value is located; inquiring whether an address range to be written corresponding to the continuous logic value is in a lookup table or not; if yes, sending an indication signal that continuous logic values are not required to be written to the DRAM controller, writing other logic values in the data section according to a common writing mode, reducing the access times of the DRAM memory, and improving the writing speed of the continuous logic values, thereby improving the data writing speed of the DRAM memory.
Description
Technical Field
The present invention relates to the field of memory technologies, and in particular, to a data writing method of a DRAM memory and a DRAM control system.
Background
DRAM is a data memory commonly used at present, and its data storage is realized by charging and discharging a capacitor of each memory cell thereof, so as to control a high level or a low level of stored data, corresponding to data 1 or 0. A DRAM controller currently controlling and data communicating a DRAM requires time to precharge the DRAM before each writing of data, a row activated precharge operation, and sequentially writing each memory cell in address order at each writing (see fig. 1). Because the internal default storage units of the DRAM are all high level after the DRAM is electrified and initialized, if the data is to be transferred to the DRAM and written with a series of continuous 1 data, the traditional method is to pre-operate the DRAM, and access the storage units without modifying the data; for a read operation, a pre-operation is first performed, and then data is read for each memory cell. Access operations are added upon such write of all 1 data. Some consecutive memory cells may in turn have consecutive data 0. Similarly, revisiting and writing 0's for consecutive data 0 addresses increases access operations, reducing the write speed of the DRAM.
Disclosure of Invention
The embodiment of the invention aims to provide a data writing method of a DRAM memory and a DRAM monitoring system.
In order to achieve the above object, according to a first aspect of the present invention, there is provided a data writing method of a DRAM memory, comprising: the method comprises the steps that a DRAM controller receives data to be written, wherein the data to be written comprises a data segment and an address segment, and the data segment corresponds to the address segment; judging whether the length of the continuous logic value of the data segment is larger than or equal to a preset length, wherein the continuous logic value is continuous 0 or 1; if the length of the continuous logic value is greater than or equal to the preset length, a lookup table is obtained, wherein the lookup table comprises the continuous logic value stored in a DRAM memory and an address range where the stored continuous logic value is located; inquiring whether an address range to be written corresponding to the continuous logic value is in the lookup table; if yes, sending an indication signal that the continuous logic value is not required to be written to the DRAM controller.
In one embodiment, the method further comprises: and receiving the preset length configured by the user.
In one embodiment, the method further comprises: determining the data length of the data segment; if the data length is smaller than the preset length, judging whether the data length is smaller than a burst length, wherein the burst length is smaller than the preset length, and the burst length is the data length for setting the minimum write-once of the DRAM; and if the data length is smaller than the burst length, sending an indication signal that the data segment is not required to be written to the DRAM controller.
In one embodiment, the method further comprises: and if the data length is greater than the burst length, executing writing according to a preset writing rule of the DRAM.
In one embodiment, after the determining whether the length of the continuous logical value of the data segment is greater than a preset length, the method further includes: and if the length of the continuous logic value is smaller than the preset length, executing writing according to a preset writing rule of the DRAM.
In one embodiment, the querying whether the address range to be written corresponding to the continuous logical value is in the lookup table according to the correspondence between the data segment and the address segment further includes: if not, executing writing according to the preset writing rule of the DRAM memory.
In one embodiment, the determining whether the length of the continuous logical value of the data segment is greater than a preset length includes: and judging whether the length of the continuous logic value of the data segment is larger than the preset length or not through a judging circuit.
In one embodiment, the method further comprises: acquiring a logic value stored in the DRAM memory and an address of the logic value; and writing the logic value and the address of the logic value in the DRAM memory into the lookup table.
In one embodiment, after the step of obtaining the logic value and the address of the logic value stored in the DRAM memory, the method further includes: judging whether the logic value stored in the DRAM memory contains a continuous logic value greater than the preset length; if so, the writing the logical value and the address of the logical value in the DRAM memory into the lookup table includes: and writing addresses of continuous logic values greater than or equal to the preset length and continuous logic values greater than or equal to the preset length in the logic values in the DRAM into the lookup table.
A second aspect of the present invention provides a DRAM control system comprising:
A DRAM controller circuit, a lookup table, a DRAM memory and a judging circuit;
The DRAM controller circuit comprises a DRAM controller and a judging circuit;
the DRAM controller is used for receiving data to be written, wherein the data to be written comprises a data segment and an address segment, and the data segment corresponds to the address segment;
The judging circuit is used for judging whether the length of the continuous logic value of the data segment is larger than a preset length, and the continuous logic value is continuous 0 or 1;
the DRAM controller is used for sending a query request to the lookup table if the length of the continuous logic value is greater than or equal to the preset length;
The lookup table is used for inquiring whether an address range to be written corresponding to the continuous logic value exists or not according to the inquiry request, wherein the lookup table comprises the continuous logic value stored in the DRAM memory and the address range where the stored continuous logic value is located;
And the DRAM controller is used for sending an indication signal that the continuous logic value is not required to be written to the DRAM controller if the address range to be written corresponding to the continuous logic value exists in the lookup table.
The data writing method of the DRAM comprises the following steps: when the DRAM controller receives data to be written, the data to be written comprises a data segment and an address segment, and the data segment corresponds to the address segment; judging whether the length of the continuous logic value of the data segment is larger than a preset length, wherein the continuous logic value is continuous 0 or 1; if the length of the continuous logic value is greater than or equal to the preset length, a lookup table is obtained, wherein the lookup table comprises the continuous logic value stored in the DRAM memory and an address range where the stored continuous logic value is located; inquiring whether an address range to be written corresponding to the continuous logic value is in a lookup table or not; if yes, sending an indication signal that the continuous logic value is not required to be written to the DRAM controller. The lookup table records data and data addresses stored in the DRAM, when the DRAM controller receives a task of writing data, the continuous logic value of the writing data is judged, when the length of the continuous logic value is longer, whether the storage addresses with the same address range of the continuous logic value exist in the DRAM is judged through the record information in the lookup table, and the data in the corresponding storage addresses in the DRAM are kept unchanged, so that the access times to the DRAM are reduced, and the writing speed of the data is accelerated.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a DRAM memory control system according to the present invention;
FIG. 2 is a schematic diagram of a DRAM memory control system according to the present invention;
FIG. 3 is a flow chart of a method for writing data into a DRAM according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is specifically noted that the following examples are only for illustrating the present invention, but do not limit the scope of the present invention. Likewise, the following examples are only some, but not all, of the examples of the present invention, and all other examples, which a person of ordinary skill in the art would obtain without making any inventive effort, are within the scope of the present invention.
The invention provides a data writing method of a DRAM memory.
Referring to fig. 1-3, fig. 2 is a schematic diagram of a DRAM control system, the DRAM control system 100 comprising: a DRAM controller 201, a lookup table 202, and a DRAM memory 203, and a judgment circuit 204; a DRAM controller 201 for receiving data to be written, the data to be written including a data segment and an address segment, the data segment corresponding to the address segment; a judging circuit 204, configured to judge whether the length of the continuous logic value of the data segment is greater than a preset length, where the continuous logic value is continuous 0 or 1; the DRAM controller 201 is configured to send a query request to the lookup table 202 if the length of the consecutive logical values is greater than or equal to a preset length; a lookup table 202, configured to query whether an address range to be written corresponding to the continuous logic value exists according to the query request, where the lookup table 202 includes the continuous logic value stored in the DRAM memory 203 and the address range where the stored continuous logic value is located; the DRAM controller 201 is configured to send an indication signal to the DRAM memory 203 to keep the address range to be written corresponding to the consecutive logical values unchanged if there is the address range to be written corresponding to the consecutive logical values in the lookup table 202.
As shown in fig. 3, fig. 3 is a flow chart of a data writing method of a DRAM memory. It should be noted that, if there are substantially the same results, the method of the present invention is not limited to the flow sequence shown in fig. 3. The method comprises the following steps:
S301: the DRAM controller receives data to be written.
In this embodiment, the data to be written includes a data segment and an address segment, where the data segment corresponds to the address segment.
The DRAM controller is used for controlling the data read-write operation of the DRAM memory. The data to be written refers to data to be written into the DRAM memory. The data to be written includes a data segment, which refers to the data to be stored, and an address segment, which refers to the storage address of the data. The correspondence of the data segment with the address segment means that each data has a unique corresponding address.
And after the DRAM control receives the data to be written, writing the data to be written into the DRAM memory according to the address segment according to a preset writing rule. The DRAM controller reads data from the DRAM memory according to a pre-configured read rule when receiving a read request to read the data.
S302, judging whether the length of the continuous logic value of the data segment is larger than or equal to a preset length.
In this particular embodiment, the consecutive logical values are consecutive 0 or 1.
The continuous logical value of the data segment is that the same logical value in the data segment is continuous, such as continuous 0 or 1, that is, 1 continuously appears multiple times or 0 continuously appears multiple times, such as one data segment of "0000, 1111, 1110, 0000, 0000", the front of the data segment comprises four continuous 0s, the middle comprises 7 continuous 1 s, the back comprises 9 continuous 0s, 4, 7 and 9 are lengths of the continuous logical value, and the lengths of the continuous logical value can be expressed in other forms. The preset length is a preset length critical value, and the length critical value is related to a specified read-write length of the DRAM memory, for example, the maximum length which can be written into the DRAM memory each time is taken as the preset length. The DRAMA memory is configured with corresponding writing rules when shipped from the factory, where the writing rules include a maximum length that can be written with data for each writing.
S303, if the length of the continuous logic value is greater than or equal to the preset length, a lookup table is obtained.
In this particular embodiment, the lookup table includes consecutive logical values stored in the DRAM memory and the address range in which the consecutive logical values are stored.
S304, inquiring whether the address range to be written corresponding to the continuous logic value is in the lookup table.
And S305, if yes, sending an indication signal that the continuous logic value is not required to be written to the DRAM controller.
The lookup table is a table for storing data and data addresses in the DRAM memory, and may be stored in the DRAM memory or in other memories that may be in communication with the DRAM control. The lookup table may store consecutive logical values stored in the DRAM memory and addresses where the consecutive logical values are stored, or may store non-consecutive logical values and addresses where the non-consecutive logical values are stored.
And when the length of the continuous logic value of the data segment of the data to be written is larger than the preset length, inquiring whether an address range corresponding to the address range of the continuous logic value exists in the lookup table. If the same logical value as the continuous logical value is found in the lookup table and the address range of the continuous logical value corresponds to the address range in the lookup table, the continuous logical value is already present in the DRAM memory, and the write operation of the data to be written is stopped without performing a write operation again. And sending an indication signal for indicating that writing operation is not required to be performed to the DRAM controller, wherein after the indication signal is received, the DRAM controller only needs to keep the data of the address range where the continuous logic value is positioned unchanged, so that the frequency of accessing the DRAM memory is reduced, the writing speed of the continuous logic value is increased, and the writing speed of the data to be written is improved.
According to the data writing method of the DRAM, the data and the address in the DRAM are stored in the lookup table, when the data is written into the DRAM, the length of the continuous logic value of the data section to be written is judged, if the length of the continuous logic value is larger than or equal to the preset critical length, whether the consistent data and the consistent address exist or not is searched in the lookup table, and if the consistent data and the consistent address exist, the writing operation is not needed, so that the writing times of the DRAM are reduced, and the data writing speed of the DRAM is improved.
In one embodiment, the data writing method of the DRAM memory further includes: and receiving the preset length configured by the user.
Specifically, the data writing length of the DRAM memory configuration refers to a writing length determined by a user according to a demand. Wherein the preset length is less than or equal to the maximum writing length of the data written each time. The maximum data length can be written into the DRAM memory each time as a critical value, the writing times of the data can be effectively reduced, if the maximum writing length is 8, the maximum writing length is 8 and is taken as a preset length, whether the writing operation needs to be executed or not is judged, if the length of the continuous logic value of the data section is greater than or equal to 8, and if the address corresponding to the continuous logic value is found in the lookup table, the writing operation can be skipped directly, and only the DRAM controller is informed that the writing operation exists in the memory. Thereby reducing the access times to the DRAM memory and improving the data writing speed of the DRAM memory.
In one embodiment, the data writing method of the DRAM memory further includes: determining the data length of the data segment; if the data length is smaller than the preset length, judging whether the data length is smaller than a burst length, wherein the burst length is smaller than the preset length, and the burst length is the data length for setting the minimum write-once of the DRAM; and if the data length is smaller than the burst length, sending an indication signal that the data segment is not required to be written to the DRAM controller.
Specifically, a preset length inside the DRAM memory is used to set the minimum write-once data length, which is referred to as the "burst length". And if the data length of the data segment is smaller than the burst length, not writing. The input data length is set to be greater than the burst length by default, and the preset length is set to be greater than the burst length by default.
In one embodiment, after determining whether the length of the continuous logical value of the data segment is greater than the preset length, the method further includes: if the length of the continuous logic value in the data segment is smaller than the preset length, writing is performed according to the preset writing rule of the DRAM memory.
The preconfigured writing rule refers to a rule related to writing data, such as a writing sequence, a writing length and the like, before writing data, of the DRAM, wherein the writing rule of the DRAM is predefined before the writing of the data, and the writing rule comprises a row/column of a first-written storage unit. If a DRAM memory includes a plurality of BANKs, each of which includes a plurality of memory cells, the locations of the memory cells are represented by the BANKs (BANKs), and the rows and columns of the BANKs.
If the length of the continuous logic value of the data segment is smaller than the preset length, for example, smaller than the maximum writing length of the DRAM, the data segment of the data to be written is sequentially written into the DRAM according to the maximum writing length according to the writing rule defined before. For data segments without longer continuous logical values, data is written according to the common data writing rules.
In one embodiment, if the data length < burst length < preset length, no write operation is performed to the DRAM memory at all; if the burst length is less than the data length is less than the preset length, directly writing to the DRAM, if the burst length is less than the preset length, searching the lookup table, and if the address range value in the lookup table is the same as the data segment, not writing to the DRAM.
In one embodiment, according to the correspondence between the data segment and the address segment, querying whether the address range to be written corresponding to the continuous logic value is in the lookup table further includes: if not, the writing is executed according to the preset writing rule of the DRAM.
The writing rule is the same as the definition of the writing rule in the above embodiment, and will not be described herein. If the address consistent with the address range of the continuous logic value cannot be found in the lookup table, the data consistent with the data of the continuous logic value of the data segment does not exist in the DRAM, and the data segment is written according to the common writing method.
In one embodiment, the preconfigured write rule includes a preset length, which is a maximum length of each write data stored by the DRAM; performing the writing of the data segment according to a pre-configured writing rule of the DRAM memory, comprising: determining a logic value to be written in the data segment at the present time according to the preset length; and writing the logic value to be written into the DRAM according to the address of the logic value to be written at present.
Specifically, when the length of the data segment is greater than the maximum length of a single write of the DRAM memory, i.e., the length of the data segment is greater than the maximum length of each write of data stored by the DRAM. Splitting the data segment into multiple writing according to the maximum length of single writing, wherein the maximum value of each writing length of the data segment is the maximum length of single writing. And writing the split data segment and the address to be written of the split data segment into the DRAM.
In one embodiment, determining whether the length of the consecutive logical values of the data segment is greater than a preset length includes: and judging whether the length of the continuous logic value of the data segment is larger than a preset length or not by a judging circuit.
Specifically, the judging circuit is used for judging whether the length of the continuous logic value in the data section of the data to be written is larger than a preset length. The judging circuit is connected with the DRAM controller and judges the continuous logic value of the data to be written received by the DRAM controller.
In one embodiment, the method for writing into a DRAM memory further includes: acquiring a logic value stored in a DRAM memory and an address of the logic value; the logical values and addresses of the logical values in the DRAM memory are written to a lookup table.
Specifically, before the lookup table is acquired, the logic value and the address of the logic value stored in the DRAM memory are written into the lookup table, and the logic value and the address of the logic value stored in the DRAM memory are read by the DRAM controller, and the DRAM controller writes the read data into the lookup table. After the DRAM controller obtains the logic value and the address of the logic value from the DRAM memory, the obtained logic value may be further determined to determine whether to write the obtained logic value and the address of the logic value into the lookup table.
In one embodiment, when the logic value and the address of the logic value are acquired from the DRAM memory, the data acquisition may be performed according to a preset condition, if the corresponding data is returned, the returned data is written into the lookup table, and if the data is not returned, the writing operation of the lookup table is not required to be performed.
In one embodiment, after retrieving the logical value and the address of the logical value stored in the DRAM memory, further comprising: judging whether the logic value stored in the DRAM memory contains a continuous logic value which is greater than or equal to a preset length; if included, writing the logical value and the address of the logical value in the DRAM memory into the lookup table includes: addresses of consecutive logical values greater than a preset length and consecutive logical values greater than the preset length among the logical values in the DRAM memory are written into the lookup table.
After the logic values stored in the DRAM memory are obtained, whether the length of the continuous logic values in the logic values stored in the DRAM memory is greater than a preset length is determined, if not, the data representing the DRAM memory does not need to be written into the lookup table, if so, the continuous logic values with the length greater than or equal to the preset length in the continuous logic values stored in the DRAM memory are written into the lookup table, and the addresses of the continuous logic values are also written into the lookup table, wherein the address writing can be writing the address corresponding to each logic value, or writing the address where the initial logic value and the last logic value of the continuous logic values are located, or writing the address where the initial logic value is located, the length of the continuous logic values, and the like, and the specific address representing the continuous logic values is not particularly limited herein.
In one embodiment, the data writing method of the DRAM memory further includes: initializing a DRAM memory so that data stored in the DRAM memory are all 1; a lookup table is initialized, the lookup table representing logical values stored in the DRAM memory and addresses of the logical values, wherein each logical value of the logical values stored in the DRAM memory is 1.
After the DRAM control system is powered on, initializing the DRAM memory, wherein after the DRAM memory is initialized, the data stored in each storage unit is 1. The lookup table is initialized, the data stored in the DRAM memory is recorded as 1 in the lookup table, and the address comprises all the addresses of the DRAM memory.
In one embodiment, the method for writing data into a DRAM memory further includes: if the address range to be written corresponding to the continuous logic value is in the lookup table and the data segment further comprises other logic values except for the continuous logic value, writing the other logic values into the DRAM according to a preset writing rule of the DRAM.
In the several embodiments provided herein, it should be understood that the disclosed systems and methods may be implemented in other ways. For example, the system embodiments described above are merely illustrative, e.g., the division of modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment.
In addition, each functional unit in each embodiment of the present invention may be integrated in one processing unit, each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the methods of the embodiments of the present invention. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing description is only a partial embodiment of the present invention, and is not intended to limit the scope of the present invention, and all equivalent devices or equivalent processes using the descriptions and the drawings of the present invention or directly or indirectly applied to other related technical fields are included in the scope of the present invention.
Claims (10)
1. A data writing method of a DRAM memory, comprising:
the method comprises the steps that a DRAM controller receives data to be written, wherein the data to be written comprises a data segment and an address segment, and the data segment corresponds to the address segment;
Judging whether the length of the continuous logic value of the data segment is larger than or equal to a preset length, wherein the continuous logic value is continuous 0 or 1;
If the length of the continuous logic value is greater than or equal to the preset length, a lookup table is obtained, wherein the lookup table comprises the continuous logic value stored in a DRAM memory and an address range where the stored continuous logic value is located;
inquiring whether an address range to be written corresponding to the continuous logic value is in the lookup table;
If yes, sending an indication signal that the continuous logic value is not required to be written to the DRAM controller.
2. The method according to claim 1, wherein the method further comprises:
and receiving the preset length configured by the user.
3. The method according to claim 1, wherein the method further comprises:
Determining the data length of the data segment;
if the data length is smaller than the preset length, judging whether the data length is smaller than a burst length, wherein the burst length is smaller than the preset length, and the burst length is the data length for setting the minimum write-once of the DRAM;
and if the data length is smaller than the burst length, sending an indication signal that the data segment is not required to be written to the DRAM controller.
4. A method according to claim 3, characterized in that the method further comprises:
and if the data length is greater than the burst length, executing writing according to a preset writing rule of the DRAM.
5. The method of claim 1, wherein after said determining whether the length of the consecutive logical values of the data segment is greater than a preset length, the method further comprises:
and if the length of the continuous logic value is smaller than the preset length, executing writing according to a preset writing rule of the DRAM.
6. The method according to claim 1, wherein the querying whether the address range to be written corresponding to the consecutive logical value is in a lookup table according to the correspondence between the data segment and the address segment, the method further comprises:
If not, executing writing according to the preset writing rule of the DRAM memory.
7. The method of claim 1, wherein determining whether the length of the consecutive logical values of the data segment is greater than a preset length comprises:
And judging whether the length of the continuous logic value of the data segment is larger than the preset length or not through a judging circuit.
8. The method according to any one of claims 1-7, further comprising:
acquiring a logic value stored in the DRAM memory and an address of the logic value;
And writing the logic value and the address of the logic value in the DRAM memory into the lookup table.
9. The method of claim 8, wherein after the retrieving the logical value stored in the DRAM memory and the address of the logical value, the method further comprises:
judging whether the logic value stored in the DRAM memory contains a continuous logic value greater than the preset length;
If so, the writing the logical value and the address of the logical value in the DRAM memory into the lookup table includes: and writing addresses of continuous logic values greater than or equal to the preset length and continuous logic values greater than or equal to the preset length in the logic values in the DRAM into the lookup table.
10. A DRAM control system, the control system comprising:
A DRAM controller circuit, a lookup table, a DRAM memory and a judging circuit;
The DRAM controller circuit comprises a DRAM controller and a judging circuit;
the DRAM controller is used for receiving data to be written, wherein the data to be written comprises a data segment and an address segment, and the data segment corresponds to the address segment;
The judging circuit is used for judging whether the length of the continuous logic value of the data segment is larger than a preset length, and the continuous logic value is continuous 0 or 1;
the DRAM controller is used for sending a query request to the lookup table if the length of the continuous logic value is greater than or equal to the preset length;
The lookup table is used for inquiring whether an address range to be written corresponding to the continuous logic value exists or not according to the inquiry request, wherein the lookup table comprises the continuous logic value stored in the DRAM memory and the address range where the stored continuous logic value is located;
And the DRAM controller is used for sending an indication signal that the continuous logic value is not required to be written to the DRAM controller if the address range to be written corresponding to the continuous logic value exists in the lookup table.
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