CN114172247B - Adapter device and electronic device - Google Patents
Adapter device and electronic device Download PDFInfo
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- CN114172247B CN114172247B CN202210129909.1A CN202210129909A CN114172247B CN 114172247 B CN114172247 B CN 114172247B CN 202210129909 A CN202210129909 A CN 202210129909A CN 114172247 B CN114172247 B CN 114172247B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The application provides adapter equipment and electronic equipment, which comprise a power output module, n protocol chips and n universal serial interfaces, wherein n is a positive integer greater than 1; the power output module is connected with the n protocol chips, the n protocol chips are connected with the corresponding n universal serial interfaces, and the n protocol chips are connected to a first node; any one protocol chip is used for determining the number of charging devices connected to the universal serial interface according to the voltage of the first node, and controlling the output voltage and the output current of the universal serial interface according to the number of the charging devices and the charging requirement. All the protocol chips can be connected through a single pin, information synchronization of the protocol chips in the adapter device is realized in a hardware improvement mode, a flexible charging strategy is provided for the electronic device, and meanwhile cost is reduced.
Description
Technical Field
The application relates to the technical field of charging, in particular to adapter equipment and electronic equipment.
Background
Along with the development of the technology, the application of "quick charging" of the electronic equipment during charging is more and more common, and the adapter equipment is used as an intermediate device for connecting a power supply and the electronic equipment to be charged, and corresponding improvement is also needed.
The existing adapter equipment with a plurality of output ports has the disadvantages that the output power of the output ports is high when the quick charging is carried out due to the fact that the total output power has a certain upper limit, and under the condition that the sum of the output power of the output ports cannot exceed the limit of the total output power, when a plurality of electronic equipment is connected into the adapter equipment, the quick charging strategy cannot be executed on each electronic equipment.
Disclosure of Invention
In view of this, the present application provides an adapter device and an electronic device, which may implement information synchronization of a protocol chip in the adapter device in a hardware-improved manner, and reduce cost while providing a flexible charging policy for the electronic device.
In a first aspect, the present application provides an adapter device, including a power output module, n protocol chips, and n universal serial interfaces, where n is a positive integer greater than 1;
the power output module is connected with the n protocol chips, the n protocol chips are connected with the corresponding n universal serial interfaces, and the n protocol chips are connected through a first node;
any one protocol chip is used for determining the number of charging devices connected to the universal serial interface according to the voltage of the first node, and controlling the output voltage and the output current of the universal serial interface according to the number of the charging devices and the charging requirement.
In a second aspect, the present application provides an electronic device comprising an adapter device as described in the first aspect of the present application.
Therefore, the adapter device and the electronic device comprise a power output module, n protocol chips and n universal serial interfaces, wherein n is a positive integer greater than 1; the power output module is connected with the n protocol chips, the n protocol chips are connected with the corresponding n universal serial interfaces, and the n protocol chips are connected to a first node; any one protocol chip is used for determining the number of charging devices connected to the universal serial interface according to the voltage of the first node, and controlling the output voltage and the output current of the universal serial interface according to the number of the charging devices and the charging requirement. All the protocol chips can be connected through a single pin, information synchronization of the protocol chips in the adapter device is realized in a hardware improvement mode, a flexible charging strategy is provided for the electronic device, and meanwhile cost is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an adapter device according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a protocol chip according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of another protocol chip provided in the embodiment of the present application;
fig. 4 is a schematic connection diagram of n protocol chips according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first," "second," and the like in the description and claims of the present application and in the foregoing drawings are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may alternatively include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be understood that the term "and/or" herein is merely one type of association relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" in this document indicates that the former and latter related objects are in an "or" relationship. The "plurality" appearing in the embodiments of the present application means two or more.
The term "connect" in the embodiments of the present application refers to various connection manners, such as direct connection or indirect connection, to implement communication between devices, which is not limited in this embodiment of the present application.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Referring to fig. 1, an adapter device in the embodiment of the present application is described, where fig. 1 is a schematic structural diagram of an adapter device provided in the embodiment of the present application, and the adapter device 100 includes a power output module 110, protocol chips 120, and universal serial interfaces 130, where there are n protocol chips 120 and n universal serial interfaces 130 corresponding to each protocol chip 120, where n is a positive integer greater than 1.
The power output module 110 is connected to the n protocol chips 120 and the n universal serial interfaces 130, the n protocol chips 120 are connected to the corresponding n universal serial interfaces 130, and the n protocol chips are connected to each other through a first node 121.
Any one of the protocol chips 120 is configured to determine the number of charging devices connected to the usb 130 according to the voltage of the first node 121, and control the output voltage and the output current of the usb 130 according to the number of charging devices and the charging requirement.
Specifically, the power output module 110 may be an AC-DC power supply, which represents the maximum power, the maximum current, and the maximum voltage of the adapter device 100, and the protocol chip 120 may control the power output module 110 to output the voltage required by the charging device connected to the usb from the corresponding usb 130, where it is understood that the n protocol chips 120 and the n usb are in one-to-one correspondence, and may number the protocol chips 120 and the usb 130, for example, the protocol chip 1 is connected to the corresponding usb 1, the protocol chip 2 is connected to the corresponding usb 2, and so on, the protocol chip n is connected to the corresponding usb n, and details are not repeated here. The n protocol chips 120 are connected to each other through the first node 121, and each protocol chip 120 may determine whether a charging device is connected to the corresponding usb 130, and may also determine the number of charging devices currently connected to the usb 130 by detecting the voltage of the first node 121, so as to control the output voltage and the output current of the corresponding usb according to the number of charging devices and the charging requirement.
Therefore, through the adapter equipment, all the protocol chips can be connected through a single pin, information synchronization of the protocol chips in the adapter equipment is realized in a hardware improvement mode, a flexible charging strategy is provided for the electronic equipment, and meanwhile cost is reduced.
For convenience of understanding, since the structures of each protocol chip are the same, the structure of a protocol chip in the embodiment of the present application is described below with reference to fig. 2, where fig. 2 is a schematic structural diagram of a protocol chip provided in the embodiment of the present application, and the protocol chip 120 includes a chip voltage terminal VDD, a first transistor Q1, a second transistor Q2, a current source terminal I, a processor CMP, an information synchronization switch S, an information synchronization pin SEL, a first resistor R1, a second resistor R2, and an output terminal PUT.
The chip voltage end VDD is connected to the first end of the first transistor Q1, the first end of the second transistor Q2, and one end of the first resistor R1, the current source end I is connected to the second end of the first transistor Q1, the third end of the first transistor Q1 is connected to the third end of the second transistor Q2, the second end of the second transistor Q2 is connected to one end of the processor CMP and one end of the information sync switch S, the other end of the processor CMP is connected to the other end of the first resistor R1 and one end of the second resistor R2, the other end of the second resistor R2 is grounded, the other end of the information sync switch S is connected to the information sync pin SEL, and it can be understood that the output end PUT is connected to a corresponding universal serial interface 130.
Specifically, the current source terminal I is a constant current source generated inside the protocol chip 120, Io is a current source after the current mirror is turned over, and the information synchronization switch S is a function switch of the information synchronization pin SEL.
Specifically, the output port PUT may include a VBUS pin, a DM pin, a DP pin, a CC pin, and the like, where the VBUS pin, the DM pin, the DP pin, and the CC pin are respectively connected to the universal serial interface 130, that is, the corresponding universal serial interface 130 also includes signal lines corresponding to the VBUS pin, the DM pin, the DP pin, the CC pin, and the like, and it is understood that the output port PUT is an exemplary illustration and does not represent a limitation on the signal lines on the universal serial interface.
For convenience of understanding, the structure of another protocol chip in the embodiment of the present application is described below with reference to fig. 3, and fig. 3 is a schematic structural diagram of another protocol chip provided in the embodiment of the present application, and it can be understood that the protocol chip 120 adds a current detection loop 310, a first current detection pin CSN, a second current detection pin CSP, a ground pin GND, and a current detection resistor Rn on the basis of the protocol chip provided in fig. 2;
one end of the current detection loop 310 is connected to the first current detection pin CSN, the other end of the current detection loop 310 is connected to the second current detection pin CSP, the first current detection pin CSN is connected to one end of the current detection resistor Rn, one end of the current detection resistor Rn is further connected to a ground pin GND, and the other end of the current detection resistor Rn is connected to the second current detection pin CSP and grounded;
the current detection loop 310 is used to detect the real-time current of the usb 130 corresponding to the protocol chip 120.
The parts not described in detail above can refer to the protocol chip described in fig. 2, and are not described again here.
After the description of the structure of the protocol chips 120, the connection relationship between the protocol chips may be further described, it is understood that each of the protocol chips 120 is connected to the first node 121 through the information synchronization pin SEL, the first node 121 is also connected to one end of a pull-down resistor Rs, and the other end of the pull-down resistor Rs is grounded;
the arbitrary protocol chip 120 determines the number of charging devices connected to the n usb interfaces 130 by detecting the voltage of the first node 121, and determines the output voltage of the output port PUT according to the number of charging devices and the requirement of the charging devices.
For the convenience of understanding, the connection relationship between the protocol chips is exemplarily described with reference to fig. 4, fig. 4 is a connection diagram of n protocol chips according to an embodiment of the present application, and it can be seen that the information synchronization pin SEL of the protocol chip 1 and the information synchronization pin SEL of the protocol chip n are both connected to the same first node 121, the voltage of the first node is Vsel, the first node is connected to one end of a pull-down resistor Rs, and the other end of the pull-down resistor Rs is grounded.
For ease of understanding, the functions and circuit flow of the protocol chip described above are further described below:
in a possible embodiment, when no charging device is connected to the universal serial interface corresponding to the protocol chip, the protocol chip controls the information synchronous switch to be switched off.
In a possible embodiment, when the charging device is connected to the universal serial interface corresponding to the protocol chip, the protocol chip controls the information synchronous switch of the protocol chip to be closed, then, the number of the charging devices is determined according to the voltage of the first node, the number of the charging devices includes 1, and when the number of the charging devices is 1, the universal serial interface corresponding to the protocol chip is controlled to output a first output voltage and a first output current according to the charging requirement and the real-time current of the charging device; when the number of the charging devices is x, x is a positive integer greater than 1, the universal serial interfaces corresponding to the protocol chips are controlled to output second output voltage and second output current according to the charging requirements and real-time currents of each charging device, the output of the universal serial interfaces is connected in parallel, the value of the second output voltage of the output voltage of each universal serial interface is the same, the second output currents with different values are configured for each charging device according to the charging requirements of each charging device, during charging, common charging is defaulted to 5V charging, and rapid charging can be applied to high-voltage charging of more than 5V, for example, the maximum power which can be output by a power adapter is assumed to be 50W, the maximum voltage is assumed to be 10V, and the maximum current is assumed to be 5A; when the number of the charging devices is 1, the maximum charging voltage of the charging device 1 is 10V, the maximum charging current is 5A, and the charging device 1 can request the maximum power of the power adapter, then a charging strategy within 10V and 5A (including 10V and 5A) can be provided for the charging device 1 according to the actual charging requirement of the charging device 1; when the number of the charging devices is 3, because the maximum voltage which can be supported by the 3 charging devices is not necessarily consistent, and only one power output is provided, at this time, because the protocol chip corresponding to each universal serial interface can know that the number of the current charging devices is 3 through the voltage of the first node, and the default output voltage of the adapter device is 5V when the adapter device provides the ordinary charging, the adapter device does not support the charging device to request the rapid charging of non-5V, at this time, a charging strategy within 5V and 5A (including 5V and 5A) can be provided for the charging devices 1 to 3 according to the actual charging requirements of the charging devices 1 to 3, the charging current is allocated according to the charging requirements of the charging devices 1 to 3, and the sum of the currents requested by the 3 charging devices is not more than 5A; if the charging device 1 requests a current of 1A, the charging device 2 requests a current of 2A, the charging device 3 requests a current of 1A, the total output current is 4A, the total output power is 20w, and the maximum output power of the adapter device is not exceeded.
It can be understood that the foregoing examples do not represent specific limitations on the embodiments of the present application, and the adapter device of the present application may have different default output voltages according to the requirements of a scene, and when the sum of the fast charging powers corresponding to the fast charging requirements required by the charging device accessing the universal serial interface is not greater than the maximum power supported by the adapter device in the embodiments of the present application, may provide a fast charging policy and a normal charging policy for the charging device accessing the universal serial interface; when the fast charging power required by the charging device connected to the universal serial interface is greater than the maximum power supported by the adapter device in the embodiment of the present application, a common charging strategy may be provided for the charging device connected to the universal serial interface, that is, a default output voltage is provided for each charging device, and a common charging current is configured according to the charging requirement of each charging device, which is not described herein again.
In a possible embodiment, in the aspect of determining the number of the charging devices according to the voltage of the first node, the any one protocol chip is configured to obtain a preset total voltage and the voltage of the first node, and determine the number of the charging devices according to a quotient of the preset total voltage and the voltage of the first node.
For ease of understanding, the following description is given by way of example.
When the universal serial interface corresponding to the adapter device in the embodiment of the application is not accessed by the charging device, the information synchronous switches of all the protocol chips in the adapter device are switched off, and the universal serial interface outputs default voltage or does not output voltage.
When a charging device is connected to the universal serial interface USBi port, the protocol chip ICi controls the information synchronous switch Si of the protocol chip ICi to be closed, the constant current source Ii of the ICi passes through the current mirror, the current source Ioi after the current mirror is turned over flows through the pull-down resistor Rs to generate the voltage Vseli of the first node, at the moment, Vseli = Rs Ioi, the ICi communicates with the output voltage and the output current required by the charging device through the signal line of the USBi, and controls the power output module to output the voltage required by the charging device, at this time, because a single charging device is connected to the adapter device, the charging device can apply for the maximum voltage, the maximum current and the maximum power which can be output by the adapter device, for example, the adapter device supports a maximum power of 40w, a maximum voltage of 20V, a maximum current of 2A, the charging device may apply for an output voltage of 20V, an output current of 2A and an output power of 40 w. It can be understood that the charging device can perform quick charging at this time.
When the first charging device is performing fast charging, and at this time, a second charging device is connected to the usb interface, the protocol chip ICj controls the information synchronizing switch Sj to close, the current source Ioj, after the constant current source Ij of ICj is inverted by the current mirror, flows through the pull-down resistor Rs to generate the voltage Vselj of the first node, and at this time, the total voltage Vsel = Vseli + Vselj of the first node, and since each protocol chip is the same, Vseli = Vselj. At this time, both the protocol chips may detect the voltage of Vsel, and may know that several charging devices are currently connected through the voltage of Vsel, for example, the ICi may determine that the number of connected charging devices is 2 through Vsel/Vseli, and ICj may determine that the number of connected charging devices is 2 through Vsel/Vselj, which is not described herein.
When ICi detects that another charging device is connected to USBj, the output voltage of the USBi is immediately closed and waits for a preset time, after the output voltage of the USBi is reduced to be within a preset voltage threshold value, ICi opens the USBi again to charge the charging device, similarly ICj also synchronously opens the USBj to charge the charging device at the moment, because two charging devices exist at the moment and the total power of the AD-DC power supply is constant, the protocol chips ICi and ICj can detect the current on respective current detection loops through respective CSP pins and CSN pins to distribute the power of respective universal serial interfaces, and flexibly adjust the output voltage, the output current and the output power of the respective universal serial interfaces in real time. It is understood that whether the fast charging can be performed on the two charging devices depends on the total power of the AC-DC and the power required by each of the two charging devices in the fast charging mode, the fast charging strategy can be performed on both the two charging devices when the total power is greater than the sum of the powers required by the two charging devices in the fast charging mode, and the fast charging strategy cannot be performed on both the charging devices when the total power is less than the sum of the powers required by the two charging devices in the fast charging mode.
When a third charging device is connected to the USBk, the protocol chip ICk controls the information synchronization switch Sk to close, the current source Iok, after the constant current source Ik of ICk is inverted by the current mirror, flows through the pull-down resistor Rs to generate the voltage Vselk at the first node, at this time, the total voltage Vsel = Vseli + Vselj + Vselk at the first node, at this time, each of the ICi, the ICj, and the ICk detects that the number of the charging devices connected to the adapter device is 3, and each of the ICi, the ICj, and the ICk will pass through the number of the currently connected devices and the current conditions on the CSP and CSN current detection loops, and adjust the charging voltage and the charging current of each USB.
When the nth charging device is connected to the usb, the working signal flow of each protocol chip is as described above, and it should be noted that the maximum number of charging devices that the adapter device can support being connected is determined by the pull-down resistor Rs, the maximum output current Io, and the maximum voltage Vsel of the first node in this embodiment of the application.
Therefore, through the adapter device, each protocol chip can determine the number of the charging devices currently accessed to the universal serial interface, and when the charging devices are pulled out of the universal serial interface, each protocol chip can detect that the number of the charging devices accessed to the universal serial interface is reduced, and synchronously adjust the power distributed to the charging devices still accessed to the universal serial interface, so that each charging device accessed to the universal serial interface can be distributed to the currently allowed maximum power.
In one possible embodiment, when the charging device is gradually pulled out from a plurality of charging devices and only one charging device is finally connected to the universal serial interface, the corresponding protocol chip can provide the maximum output voltage, the maximum output current and the maximum output power for the charging device according to the requirements of the charging device.
In a possible embodiment, when the charging device is charged with electricity, the real-time current required by the charging device is gradually reduced, the protocol chip can detect that the real-time current is smaller and smaller through the current detection loop, and when the real-time current is smaller than the preset current threshold, the protocol chip can adjust the output loop to reduce the output voltage of the universal serial interface so as to protect the charging device.
It can be seen that, by the above adapter device, it includes a power output module, n protocol chips, n universal serial interfaces, where n is a positive integer greater than 1; the power output module is connected with the n protocol chips, the n protocol chips are connected with the corresponding n universal serial interfaces, and the n protocol chips are connected to a first node; and any one protocol chip is used for determining the number of the charging devices connected to the universal serial interface according to the voltage of the first node, and controlling the output voltage and the output current of the universal serial interface according to the number of the charging devices and the charging requirement. All the protocol chips can be connected through a single pin, information synchronization of the protocol chips in the adapter equipment is realized in a hardware improvement mode, a complex communication protocol is not required to be set, peripheral devices are few, the logic of each protocol chip is the same, a master chip and a slave chip are not required to be set, a flexible charging strategy is provided for the electronic equipment, and meanwhile cost is reduced.
Next, referring to fig. 5, an electronic device in the embodiment of the present application is described, where the electronic device 500 may include the adapter device, which is not described herein again.
Therefore, the adapter device and the electronic device comprise a power output module, n protocol chips and n universal serial interfaces, wherein n is a positive integer greater than 1; the power output module is connected with the n protocol chips, the n protocol chips are connected with the corresponding n universal serial interfaces, and the n protocol chips are connected to a first node; any one protocol chip is used for determining the number of charging devices connected to the universal serial interface according to the voltage of the first node, and controlling the output voltage and the output current of the universal serial interface according to the number of the charging devices and the charging requirement. All the protocol chips can be connected through a single pin, information synchronization of the protocol chips in the adapter device is realized in a hardware improvement mode, a flexible charging strategy is provided for the electronic device, and meanwhile cost is reduced.
It should be noted that, for the sake of simplicity, the embodiments of the present application are described as a series of acts or combinations, but those skilled in the art should understand that the present application is not limited by the described order of acts, as some steps may be performed in other orders or simultaneously according to the present application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the above-described division of the units is only one type of division of logical functions, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application with specific examples, and the above description of the embodiments is only provided to help understand the present application and its core ideas; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in view of the above, the content of the present specification should not be construed as a limitation to the present application.
Claims (8)
1. An adapter device is characterized by comprising a power output module, n protocol chips and n universal serial interfaces, wherein n is a positive integer greater than 1;
the power output module is connected with the n protocol chips, the n protocol chips are connected with the corresponding n universal serial interfaces, and the n protocol chips are connected through a first node;
any one protocol chip comprises a chip voltage end, a first triode, a second triode, a current source end, a processor, an information synchronous switch, an information synchronous pin, a first resistor, a second resistor, an output end, a current detection loop, a first current detection pin, a second current detection pin, a grounding pin and a current detection resistor;
the chip voltage end is respectively connected with a first end of the first triode, a first end of the second triode and one end of the first resistor, the current source end is connected with a second end of the first triode, a third end of the first triode is connected with a third end of the second triode, a second end of the second triode is connected with one end of the processor and one end of the information synchronous switch, the other end of the processor is connected with the other end of the first resistor and one end of the second resistor, the other end of the second resistor is grounded, the other end of the information synchronous switch is connected with the information synchronous pin, and the output end is connected with a corresponding universal serial interface;
each protocol chip is connected to the first node through the information synchronization pin, the first node is also connected with one end of a pull-down resistor, and the other end of the pull-down resistor is grounded;
one end of the current detection loop is connected with the first current detection pin, the other end of the current detection loop is connected with the second current detection pin, the first current detection pin is connected with one end of the current detection resistor, one end of the current detection resistor is also connected with the grounding pin, and the other end of the current detection resistor is connected with the second current detection pin and grounded;
the arbitrary protocol chip is used for determining the number of charging devices connected to the n universal serial interfaces by detecting the voltage of the first node, detecting the real-time current of the universal serial interfaces by the current detection loop, and determining the output voltage and the output current of the output end according to the number of the charging devices, the real-time current and the charging requirement of the charging devices.
2. The adapter device of claim 1, wherein the output comprises a VBUS pin, a DM pin, a DP pin, and a CC pin, the VBUS pin, the DM pin, the DP pin, and the CC pin being connected to the universal serial interface, respectively.
3. The adapter device of claim 1 wherein the power output module comprises an AC-DC power supply.
4. The adapter device according to any of claims 1-3, wherein any of the protocol chips is configured to:
and when no charging equipment is connected to the universal serial interface corresponding to any protocol chip, controlling the information synchronous switch of the protocol chip to be switched off.
5. The adapter device according to any of claims 1-3, wherein any of the protocol chips is configured to:
when the charging equipment is connected to the universal serial interface corresponding to any protocol chip, controlling an information synchronous switch of the protocol chip to be closed;
determining the number of the charging devices according to the voltage of the first node, wherein the number of the charging devices comprises 1;
and when the number of the charging equipment is 1, controlling a universal serial interface corresponding to the protocol chip to output a first output voltage and a first output current according to the charging requirement of the charging equipment and the real-time current.
6. The adapter device according to claim 5, wherein the number of charging devices comprises x, x being a positive integer greater than 1; after determining the number of charging devices according to the voltage of the first node, the any one protocol chip is further configured to:
and when the number of the charging equipment is x, controlling the universal serial interface corresponding to the protocol chip to output a second output voltage and a second output current according to the charging requirement and the real-time current of each charging equipment.
7. The adapter device according to claim 5, wherein in said determining the number of charging devices according to the voltage of the first node, the arbitrary one protocol chip is configured to:
acquiring a preset total voltage and the voltage of the first node;
and determining the number of the charging devices according to the quotient of the preset total voltage and the voltage of the first node.
8. An electronic device, characterized in that it comprises an adapter device according to any one of claims 1-7.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210129909.1A CN114172247B (en) | 2022-02-11 | 2022-02-11 | Adapter device and electronic device |
| CN202210572880.4A CN116632953A (en) | 2022-02-11 | 2022-02-11 | Adapter device and related electronic device |
| PCT/CN2023/074890 WO2023151569A1 (en) | 2022-02-11 | 2023-02-08 | Adapter device and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210129909.1A CN114172247B (en) | 2022-02-11 | 2022-02-11 | Adapter device and electronic device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210572880.4A Division CN116632953A (en) | 2022-02-11 | 2022-02-11 | Adapter device and related electronic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114172247A CN114172247A (en) | 2022-03-11 |
| CN114172247B true CN114172247B (en) | 2022-05-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210129909.1A Active CN114172247B (en) | 2022-02-11 | 2022-02-11 | Adapter device and electronic device |
| CN202210572880.4A Pending CN116632953A (en) | 2022-02-11 | 2022-02-11 | Adapter device and related electronic device |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210572880.4A Pending CN116632953A (en) | 2022-02-11 | 2022-02-11 | Adapter device and related electronic device |
Country Status (2)
| Country | Link |
|---|---|
| CN (2) | CN114172247B (en) |
| WO (1) | WO2023151569A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114172247B (en) * | 2022-02-11 | 2022-05-17 | 深圳英集芯科技股份有限公司 | Adapter device and electronic device |
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| CN105144638A (en) * | 2013-03-15 | 2015-12-09 | 密克罗奇普技术公司 | Multi-current harmonized paths for low power local interconnect network (lin) receiver |
| CN212343388U (en) * | 2020-07-10 | 2021-01-12 | 深圳英集芯科技有限公司 | Be used for battery charging outfit interface to ground short-circuit protection circuit |
| CN113629802A (en) * | 2021-07-15 | 2021-11-09 | 深圳天德钰科技股份有限公司 | Power supply device |
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| US20180339597A1 (en) * | 2017-05-23 | 2018-11-29 | Martin Kruszelnicki | Charging connector |
| CN113285517B (en) * | 2021-07-23 | 2021-10-01 | 深圳英集芯科技股份有限公司 | Power adapter and charging control method |
| CN114172247B (en) * | 2022-02-11 | 2022-05-17 | 深圳英集芯科技股份有限公司 | Adapter device and electronic device |
-
2022
- 2022-02-11 CN CN202210129909.1A patent/CN114172247B/en active Active
- 2022-02-11 CN CN202210572880.4A patent/CN116632953A/en active Pending
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2023
- 2023-02-08 WO PCT/CN2023/074890 patent/WO2023151569A1/en unknown
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| CN105144638A (en) * | 2013-03-15 | 2015-12-09 | 密克罗奇普技术公司 | Multi-current harmonized paths for low power local interconnect network (lin) receiver |
| CN212343388U (en) * | 2020-07-10 | 2021-01-12 | 深圳英集芯科技有限公司 | Be used for battery charging outfit interface to ground short-circuit protection circuit |
| CN113629802A (en) * | 2021-07-15 | 2021-11-09 | 深圳天德钰科技股份有限公司 | Power supply device |
| CN113629806A (en) * | 2021-08-04 | 2021-11-09 | 闪极科技(深圳)有限公司 | Multi-interface charger with freely-distributed output power |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN116632953A (en) | 2023-08-22 |
| CN114172247A (en) | 2022-03-11 |
| WO2023151569A1 (en) | 2023-08-17 |
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