CN114156283A

CN114156283A - Display substrate, preparation method thereof and display device

Info

Publication number: CN114156283A
Application number: CN202111443277.8A
Authority: CN
Inventors: 熊星; 李希萌; 杨钟; 刘莉; 刘全; 徐春雷; 温庆林
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2021-11-30
Filing date: 2021-11-30
Publication date: 2022-03-08

Abstract

The disclosure provides a display substrate, a preparation method thereof and a display device. The display substrate comprises a first electrode, a blocking electrode and a second electrode which are sequentially arranged on a substrate, the second electrode is connected with the first electrode through a connecting through hole, the orthographic projection of the blocking electrode on the substrate is at least partially overlapped with the orthographic projection of the connecting through hole on the substrate, and the blocking electrode is configured to enable the hole wall of the connecting through hole to be of a step structure. This is disclosed through setting up the blocking electrode, sets the connection via hole of connecting first electrode and second electrode to the stair structure, has improved the rete deposition quality in the via hole, has effectively solved current preparation technology and has had the low scheduling problem of yields, has improved the yields.

Description

Display substrate, preparation method thereof and display device

Technical Field

The present disclosure relates to but not limited to the field of display technologies, and in particular, to a display substrate, a method for manufacturing the same, and a display device.

Background

Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active Light Emitting display devices, and have the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, very high response speed, thinness, flexibility, low cost, and the like. With the continuous development of display technology, a display device using an OLED or a QLED as a light emitting device and performing signal control by a Thin Film Transistor (TFT) has become a mainstream product in the display field at present.

The research of the inventor of the application discovers that the existing preparation process of the OLED or QLED display device has the problems of low yield and the like.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The technical problem to be solved by the present disclosure is to provide a display substrate, a manufacturing method thereof, and a display device, so as to solve the problems of low yield and the like in the existing manufacturing process.

The utility model provides a display substrate, include first electrode, blocking electrode and the second electrode that sets gradually on the basement, the second electrode through connect the via hole with first electrode is connected, blocking electrode is in orthographic projection on the basement with connect the via hole and be in orthographic projection on the basement at least part overlap, blocking electrode is configured to make the pore wall of connecting the via hole is the stair structure.

In an exemplary embodiment, the display substrate further includes: a first composite insulating layer disposed between the first electrode and the barrier electrode, a second composite insulating layer disposed between the barrier electrode and the second electrode; the connecting via hole comprises a first sub-hole, a second sub-hole and a third sub-hole which are communicated with each other, the first sub-hole is a via hole formed in the first composite insulating layer, the second sub-hole is a via hole formed in the blocking electrode, and the third sub-hole is a via hole formed in the second composite insulating layer.

In an exemplary embodiment, an orthographic projection of the first sub-aperture on the substrate is within an orthographic projection of the second sub-aperture on the substrate, and an orthographic projection of the second sub-aperture on the substrate is within an orthographic projection of the third sub-aperture on the substrate.

In an exemplary embodiment, a step is formed at an intersection of the second sub-hole and a third sub-hole exposing surfaces of the second sub-hole and a side of the blocking electrode away from the substrate.

In an exemplary embodiment, the first sub-hole, the second sub-hole, and the third sub-hole have an inverted trapezoidal cross-sectional shape in a plane perpendicular to the substrate.

In an exemplary embodiment, the hole wall angle of the third sub-hole is greater than the hole wall angle of the first sub-hole, the hole wall angle of the first sub-hole is greater than the hole wall angle of the second sub-hole, and the hole wall angle is an included angle between an inner wall of the hole and the substrate plane.

In an exemplary embodiment, the hole wall angle of the first sub-hole is 55 ° to 75 °.

In an exemplary embodiment, the second sub-hole has a hole wall slope angle of 25 ° to 45 °.

In an exemplary embodiment, the hole wall dispersion angle of the third sub-hole is 55 ° to 80 °.

In an exemplary embodiment, the barrier electrode has a shape of a circular ring, an elliptical ring, a rectangular ring, a pentagonal ring, or a hexagonal ring in a plane parallel to the substrate.

In an exemplary embodiment, the cross-sectional shape of the blocking electrode in a plane perpendicular to the substrate is a trapezoid shape, a side slope angle of the blocking electrode on the outer side of the ring shape is 25 ° to 45 °, and the side slope angle is an angle between a side of the blocking electrode and the substrate plane.

In an exemplary embodiment, the display substrate includes a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a fourth conductive layer sequentially disposed on a substrate, the first electrode is disposed in the first conductive layer, the second electrode is disposed in the fourth conductive layer, and the blocking electrode is disposed in the second conductive layer and/or the third conductive layer.

In an exemplary embodiment, the first electrode is a shielding electrode, and the second electrode is a source electrode of a transistor.

The present disclosure also provides a display device including the display substrate.

The present disclosure also provides a method for manufacturing a display substrate, including:

the method comprises the steps that a first electrode, a blocking electrode and a second electrode are sequentially formed on a substrate, the second electrode is connected with the first electrode through a connecting through hole, the orthographic projection of the blocking electrode on the substrate is at least partially overlapped with the orthographic projection of the connecting through hole on the substrate, and the blocking electrode is configured to enable the hole wall of the connecting through hole to be of a step structure.

The embodiment of the disclosure discloses a display substrate, a preparation method thereof and a display device.

Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the example serve to explain the principles of the disclosure and not to limit the disclosure. The shapes and sizes of the various elements in the drawings are not to be considered as true proportions, but are merely intended to illustrate the present disclosure.

FIG. 1 is a schematic diagram of a display device;

FIG. 2 is a schematic plan view of a display substrate;

FIG. 3 is a schematic cross-sectional view of a display substrate;

FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

FIG. 5 is a timing diagram of a pixel driving circuit;

FIG. 6 is a schematic cross-sectional view illustrating a display substrate according to an exemplary embodiment of the disclosure;

fig. 7 is a schematic view after a first conductive layer pattern is formed according to an exemplary embodiment of the present disclosure;

fig. 8 is a schematic view after forming a semiconductor pattern according to an exemplary embodiment of the present disclosure;

fig. 9 is a schematic view after a second conductive layer pattern is formed according to an exemplary embodiment of the present disclosure;

fig. 10 is a schematic plan view of a barrier electrode according to an exemplary embodiment of the present disclosure;

fig. 11 is a schematic cross-sectional structure view of a barrier electrode according to an exemplary embodiment of the present disclosure;

fig. 12 is a schematic view after a third conductive layer pattern is formed according to an exemplary embodiment of the present disclosure;

fig. 13 is a schematic view after a fourth insulation layer pattern is formed according to an exemplary embodiment of the present disclosure;

FIG. 14 is a schematic cross-sectional view of a third via according to an exemplary embodiment of the disclosure;

fig. 15 is a schematic view after a fourth conductive layer pattern is formed according to an exemplary embodiment of the present disclosure;

FIG. 16 is a schematic structural diagram of a source electrode connected to a shielding electrode according to an exemplary embodiment of the disclosure;

FIG. 17 is a schematic cross-sectional view of another display substrate according to an exemplary embodiment of the disclosure;

FIG. 18 is a schematic cross-sectional view of another third via according to an exemplary embodiment of the present disclosure;

FIG. 19 is a schematic cross-sectional view of another display substrate according to an exemplary embodiment of the disclosure;

fig. 20 is a schematic cross-sectional structure view of a third via according to an exemplary embodiment of the disclosure.

Description of reference numerals:

10-a substrate; 11 — a first insulating layer; 12 — a second insulating layer;

13 — a third insulating layer; 14 — a fourth insulating layer; 21-shielding electrodes;

22 — active layer; 23-a gate electrode; 24-a source electrode;

25-a drain electrode; 30-a barrier electrode; 30A — first barrier electrode;

30B — a second barrier electrode; 31 — first side; 32-a second side edge;

41-a first plate; 42-a second pole plate; 51 — a first sublayer;

52 — a second sublayer; 53 — third sublayer; 101-a transistor;

101A-storage capacitance; 102-a driving circuit layer; 103-light emitting structure layer;

104-packaging structure layer; 301-anode; 302-pixel definition layer;

303 — an organic light emitting layer; 304-a cathode; 401 — first encapsulation layer;

401 — second encapsulation layer; 403-third encapsulation layer.

Detailed Description

To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments may be implemented in a plurality of different forms. Those skilled in the art can readily appreciate the fact that the forms and details may be varied into a variety of forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. The embodiments and features of the embodiments in the present disclosure may be arbitrarily combined with each other without conflict.

The drawing scale in this disclosure may be referenced in the actual process, but is not limited thereto. For example: the width-length ratio of the channel, the thickness and the interval of each film layer and the width and the interval of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the drawings, and the drawings described in the present disclosure are only schematic structural views, and one embodiment of the present disclosure is not limited to the shapes, numerical values, and the like shown in the drawings.

The ordinal numbers such as "first", "second", "third", and the like in the present specification are provided for avoiding confusion among the constituent elements, and are not limited in number.

In this specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicating orientations or positional relationships are used to explain positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present disclosure. The positional relationship of the components is changed as appropriate in accordance with the direction in which each component is described. Therefore, the words described in the specification are not limited to the words described in the specification, and may be replaced as appropriate.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise specifically indicated and limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The specific meaning of the above terms in the present disclosure can be understood in specific instances by those of ordinary skill in the art.

In this specification, a transistor refers to an element including at least three terminals, i.e., a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region where current mainly flows.

In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors of opposite polarities, or in the case of changing the direction of current flow during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged with each other.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having a certain electric function" is not particularly limited as long as it can transmit and receive an electric signal between connected components. Examples of the "element having some kind of electric function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present specification, "parallel" means a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less, and therefore, includes a state in which the angle is-5 ° or more and 5 ° or less. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and therefore includes a state in which the angle is 85 ° or more and 95 ° or less.

In the present specification, "film" and "layer" may be interchanged with each other. For example, the "conductive layer" may be sometimes replaced with a "conductive film". Similarly, the "insulating film" may be replaced with an "insulating layer".

In the present specification, the term "disposed on the same layer" is used to refer to a structure formed by patterning two (or more) structures by the same patterning process, and the materials thereof may be the same or different. For example, the materials forming the precursors of the various structures disposed in the same layer are the same, and the materials ultimately formed may be the same or different.

In this specification, a triangle, a rectangle, a trapezoid, a pentagon, a hexagon, or the like is not strictly defined, and may be an approximate triangle, a rectangle, a trapezoid, a pentagon, a hexagon, or the like, and some small deformations due to tolerances may exist, and a lead angle, a curved edge, deformation, or the like may exist.

"about" in this disclosure means that the limits are not strictly defined, and that the numerical values are within the tolerances allowed for the process and measurement.

Fig. 1 is a schematic structural diagram of a display device. As shown in fig. 1, the display device may include a timing controller connected to the data driver, the scan driver and the light emitting driver, respectively, the data driver connected to the plurality of data signal lines (D1 to Dn), respectively, the scan driver connected to the plurality of scan signal lines (S1 to Sm), respectively, the light emitting driver connected to the plurality of light emitting signal lines (E1 to Eo), respectively, and a pixel array. The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one of the sub-pixels Pxij may include a circuit unit and a light emitting device connected to the circuit unit, and the circuit unit may include at least one scan signal line, at least one data signal line, at least one light emitting signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller may supply a gray value and a control signal suitable for the specification of the data driver to the data driver, may supply a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver, and may supply a clock signal, an emission stop signal, etc. suitable for the specification of the light emitting driver to the light emitting driver. The data driver may generate data voltages to be supplied to the data signal lines D1, D2, D3, … …, and Dn using the gray scale value and the control signal received from the timing controller. For example, the data driver may sample a gray value using a clock signal and apply a data voltage corresponding to the gray value to the data signal lines D1 to Dn in units of pixel rows, n may be a natural number. The scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, … …, and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan driver may be constructed in the form of a shift register, and may generate the scan signals in such a manner that scan start signals provided in the form of on-level pulses are sequentially transmitted to the next stage circuit under the control of a clock signal, and m may be a natural number. The light emission driver may generate emission signals to be supplied to the light emission signal lines E1, E2, E3, … …, and Eo by receiving a clock signal, an emission stop signal, and the like from the timing controller. For example, the light emission driver may sequentially supply emission signals having off-level pulses to the light emission signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register, and the emission signal may be generated in such a manner that the emission stop signal provided in the form of an off-level pulse is sequentially transmitted to the next stage circuit under the control of a clock signal, and o may be a natural number.

Fig. 2 is a schematic plan view of a display substrate. As shown in fig. 2, the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting light of a first color, a second sub-pixel P2 emitting light of a second color, and a third sub-pixel P3 emitting light of a third color, and each of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 includes a pixel driving circuit and a light emitting device. The pixel driving circuits in the first, second and third sub-pixels P1, P2 and P3 are respectively connected to the scan signal line, the data signal line and the light emitting signal line, and the pixel driving circuits are configured to receive the data voltage transmitted from the data signal line and output corresponding currents to the light emitting devices under the control of the scan signal line and the light emitting signal line. The light emitting devices in the first, second and third sub-pixels P1, P2 and P3 are respectively connected to the pixel driving circuit of the sub-pixel in which they are located, and the light emitting devices are configured to emit light of corresponding luminance in response to a current output from the pixel driving circuit of the sub-pixel in which they are located.

In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel emitting red (R) light, the second sub-pixel P2 may be a blue sub-pixel emitting blue (B) light, and the third sub-pixel P3 may be a green sub-pixel emitting green (G) light. In an exemplary embodiment, the shape of the sub-pixels in the pixel unit may be a rectangle, a diamond, a pentagon, a hexagon, or the like, and may be arranged in a horizontal juxtaposition, a vertical juxtaposition, a delta arrangement, or the like.

In an exemplary embodiment, the pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel manner, a vertical parallel square manner, a diamond shape, or the like, and the disclosure is not limited thereto.

Fig. 3 is a schematic cross-sectional structure diagram of a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate. As shown in fig. 3, the display substrate may include a driving circuit layer 102 disposed on the substrate 10, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 10, and a package structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 10, in a plane perpendicular to the display substrate. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, and the disclosure is not limited herein.

In exemplary embodiments, the substrate 10 may be a flexible substrate, or may be a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit, and only the pixel driving circuit including one transistor 101 and one storage capacitor 101A is exemplified in fig. 3. The light emitting structure layer 103 may include an anode 301, a pixel defining layer 302, an organic light emitting layer 303, and a cathode 304, the anode 301 is connected to the drain electrode of the driving transistor 210 through a via hole, the organic light emitting layer 303 is connected to the anode 301, the cathode 304 is connected to the organic light emitting layer 303, and the organic light emitting layer 303 emits light of a corresponding color under the driving of the anode 301 and the cathode 304. The encapsulation structure layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 that are stacked, the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, the second encapsulation layer 402 may be made of organic materials, and the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403, so as to ensure that external moisture cannot enter the light emitting structure layer 103.

In an exemplary embodiment, the organic light emitting layer 303 may include an emission layer (EML) and any one or more of: a hole injection layer HIL), a Hole Transport Layer (HTL), an electron blocking Electrode (EBL), a hole blocking electrode (HBL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, the hole transport layer, the electron blocking electrode, the hole blocking electrode, the electron transport layer, and the electron injection layer of all the sub-pixels may be a common layer connected together, and the light emitting layers of adjacent sub-pixels may have a small amount of overlap or may be isolated.

Fig. 4 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. As shown in fig. 4, the pixel driving circuit may include 7 transistors (transistors T1 to seventh transistor T7), 1 storage capacitor C, and the pixel driving circuit may be connected to 7 signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, light emitting signal line E, initial signal line INIT, first power supply line VDD, and second power supply line VSS).

In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is respectively connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4, and the second pole of the fifth transistor T5, the second node N2 is respectively connected to the second pole of the transistor, the first pole of the second transistor T2, the control pole of the third transistor T3, and the second end of the storage capacitor C, and the third node N3 is respectively connected to the second pole of the second transistor T2, the second pole of the third transistor T3, and the first pole of the sixth transistor T6.

In an exemplary embodiment, a first terminal of the storage capacitor C is connected to the first power line VDD, and a second terminal of the storage capacitor C is connected to the second node N2, that is, the second terminal of the storage capacitor C is connected to the control electrode of the third transistor T3.

A control electrode of the transistor T1 is connected to the second scanning signal line S2, a first electrode of the transistor T1 is connected to the initialization signal line INIT, and a second electrode of the transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the transistor T1 transmits an initialization voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.

A control electrode of the second transistor T2 is connected to the first scan signal line S1, a first electrode of the second transistor T2 is connected to the second node N2, and a second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 with the second electrode.

A control electrode of the third transistor T3 is connected to the second node N2, that is, a control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C, a first electrode of the third transistor T3 is connected to the first node N1, and a second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 may be referred to as a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to a potential difference between a control electrode and a first electrode thereof.

A control electrode of the fourth transistor T4 is connected to the first scan signal line S1, a first electrode of the fourth transistor T4 is connected to the data signal line D, and a second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 may be referred to as a switching transistor, a scan transistor, or the like, and when an on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

A control electrode of the fifth transistor T5 is connected to the light emitting signal line E, a first electrode of the fifth transistor T5 is connected to the first power source line VDD, and a second electrode of the fifth transistor T5 is connected to the first node N1. A control electrode of the sixth transistor T6 is connected to the light emitting signal line E, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. The fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors. When the on-level light emission signal is applied to the light emission signal line E, the fifth transistor T5 and the sixth transistor T6 make the light emitting device emit light by forming a driving current path between the first power line VDD and the second power line VSS.

A control electrode of the seventh transistor T7 is connected to the first scanning signal line S1, a first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and a second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device. When the on-level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits an initialization voltage to the first pole of the light emitting device to initialize or release the amount of charge accumulated in the first pole of the light emitting device.

In an exemplary embodiment, the second pole of the light emitting device is connected to a second power line VSS, the second power line VSS being a low level signal, and the first power line VDD being a high level signal. The first scanning signal line S1 is a scanning signal line in the pixel driving circuit of the display line, the second scanning signal line S2 is a scanning signal line in the pixel driving circuit of the previous display line, that is, for the nth display line, the first scanning signal line S1 is S (n), the second scanning signal line S2 is S (n-1), the second scanning signal line S2 of the display line and the first scanning signal line S1 in the pixel driving circuit of the previous display line are the same signal line, which can reduce the signal lines of the display panel and realize the narrow frame of the display panel.

In an exemplary embodiment, the first to seventh transistors T1 to T7 may be P-type transistors or may be N-type transistors. The same type of transistors are adopted in the pixel driving circuit, so that the process flow can be simplified, the process difficulty of the display panel is reduced, and the yield of products is improved. In some possible implementations, the transistors T1 through T7 may include P-type transistors and N-type transistors.

In an exemplary embodiment, the first to seventh transistors T1 to T7 may employ a low temperature polysilicon thin film transistor, or may employ an oxide thin film transistor, or may employ both a low temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the Low Temperature polysilicon thin film transistor adopts Low Temperature polysilicon (LTPS for short), and the active layer of the Oxide thin film transistor adopts Oxide (Oxide). The low-temperature polycrystalline silicon thin film transistor has the advantages of high mobility, quick charging and the like, and the oxide thin film transistor has the advantages of low leakage current and the like. In an exemplary embodiment, a Low Temperature polysilicon thin film transistor and an Oxide thin film transistor may be integrated on a display substrate to form a Low Temperature Polysilicon Oxide (LTPO) display substrate, and may use advantages of the two, may implement high resolution (Pixel Per inc, PPI for short), may perform Low frequency driving, may reduce power consumption, and may improve display quality.

In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the light emitting signal line E, and the initial signal line INIT may extend in a horizontal direction, and the second power supply line VSS, the first power supply line VDD, and the data signal line D may extend in a vertical direction.

In an exemplary embodiment, the light emitting device may be an organic electroluminescent diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

Fig. 5 is a timing diagram of an operation of a pixel driving circuit. The exemplary embodiment of the present disclosure will be explained by the operation process of the pixel driving circuit illustrated in fig. 4, where the pixel driving circuit in fig. 4 includes 7 transistors (the transistor T1 to the seventh transistor T7) and 1 storage capacitor C, and the 7 transistors are all P-type transistors.

In an exemplary embodiment, the operation of the pixel driving circuit may include:

in the first phase a1, which is referred to as a reset phase, the signal of the second scan signal line S2 is a low level signal, and the signals of the first scan signal line S1 and the light-emitting signal line E are high level signals. The signal of the second scan signal line S2 is a low level signal, turning on the transistor T1, and the signal of the initialization signal line INIT is provided to the second node N2, initializing the storage capacitor C, and clearing the original data voltage in the storage capacitor. The signals of the first scanning signal line S1 and the light emitting signal line E are high level signals, turning off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7, and the OLED does not emit light at this stage.

In the second phase a2, which is referred to as a data write phase or a threshold compensation phase, the signal of the first scanning signal line S1 is a low level signal, the signals of the second scanning signal line S2 and the light emitting signal line E are high level signals, and the data signal line D outputs a data voltage. At this stage, the second terminal of the storage capacitor C is at a low level, so the third transistor T3 is turned on. The signal of the first scan signal line S1 is a low level signal to turn on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output from the data signal line D is supplied to the second node N2 through the first node N1, the turned-on third transistor T3, the turned-on third node N3, and the turned-on second transistor T2, and a difference between the data voltage output from the data signal line D and the threshold voltage of the third transistor T3 is charged in the storage capacitor C, the voltage at the second terminal (the second node N2) of the storage capacitor C is Vd- | Vth |, Vd is the data voltage output from the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on to supply the initial voltage of the initial signal line INIT to the first electrode of the OLED, initialize (reset) the first electrode of the OLED, clear the pre-stored voltage therein, complete the initialization, and ensure that the OLED does not emit light. The signal of the second scanning signal line S2 is a high-level signal, turning off the transistor T1. The signal of the light emitting signal line E is a high level signal, turning off the fifth transistor T5 and the sixth transistor T6.

In the third stage a3, referred to as a light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals. The signal of the light emitting signal line E is a low level signal, the fifth transistor T5 and the sixth transistor T6 are turned on, and the power voltage output from the first power line VDD supplies a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, thereby driving the OLED to emit light.

During the driving of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the gate electrode and the first electrode thereof. Since the voltage of the second node N2 is Vdata- | Vth |, the driving current of the third transistor T3 is:

I＝K*(Vgs-Vth)²＝K*[(Vdd-Vd+|Vth|)-Vth]²＝K*[(Vdd-Vd]²

where I is a driving current flowing through the third transistor T3, that is, a driving current driving the OLED, K is a constant, Vgs is a voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is a threshold voltage of the third transistor T3, Vd is a data voltage output from the data signal line D, and Vdd is a power voltage output from the first power line Vdd.

The research of the inventor of the application discovers that the existing preparation process has the problems of low yield and the like, and is caused by the fact that the depth of a through hole for connecting two electrodes is large to a certain extent. For example, in a dual gate structure transistor provided with a shield electrode, since a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer are provided between a source electrode and the shield electrode, a via hole connecting the source electrode and the shield electrode is a deep hole. Due to the fact that the depth of the via hole is large, the depth of the via hole is larger than 1 mu m, the slope angle of the side wall of the via hole is large and is about 75-85 degrees, the deposition effect of the conductive material in the via hole is poor, and the yield is reduced. Through further research by the inventor of the application, the main phenomenon that the deposition effect of the first source drain metal layer with the three-layer structure is poor is that: (1) the top layer deposited in the deep hole can not completely coat the middle layer, and the display substrate is unqualified due to oxidation and corrosion risks caused by the exposure of the middle layer; (2) the middle layer thickness of deep hole lateral wall and deep hole bottom is less, has because of the impaling risk that downthehole burr leads to, leads to the display substrate unqualified.

In order to solve the problems of low yield and the like of the existing preparation process, the exemplary embodiment of the disclosure provides a display substrate. In an exemplary embodiment, the display substrate may include a first electrode, a barrier electrode, and a second electrode sequentially disposed on a substrate, the second electrode being connected to the first electrode through a connection via, an orthographic projection of the barrier electrode on the substrate at least partially overlapping an orthographic projection of the connection via on the substrate, the barrier electrode being configured such that a hole wall of the connection via is a step structure. According to the through hole forming step structure, the film deposition quality in the through hole is improved, the problems that the existing preparation process is low in yield and the like are effectively solved, and the yield is improved.

Fig. 6 is a schematic cross-sectional structure diagram of a display substrate according to an exemplary embodiment of the disclosure, illustrating a structure of a transistor and a storage capacitor. As shown in fig. 6, the display substrate may include a base 10, and a first conductive layer, a first insulating layer 11, a semiconductor layer, a second insulating layer 12, a second conductive layer, a third insulating layer 13, a third conductive layer, a fourth insulating layer 14, and a fourth conductive layer sequentially disposed on the base 10 in a plane perpendicular to the display substrate. Wherein, the first conductive layer may include the shielding electrode 21 as the first electrode of the present disclosure, the semiconductor layer may include the active layer 22, the second conductive layer may include the gate electrode 23, the blocking electrode 30 and the first electrode plate 41, the third conductive layer may include the second electrode plate 42, the fourth conductive layer may include the drain electrode 25 and the source electrode 24 as the second electrode of the present disclosure, the source electrode 24 may be connected with the active layer 22 and the shielding electrode 21 through the first via hole and the third via hole, respectively, and the drain electrode 25 may be connected with the active layer 22 through the second via hole.

In an exemplary embodiment, the first insulating layer 11 and the second insulating layer 12 are disposed between the barrier electrode 30 and the shielding electrode 21 as the first electrode, the first insulating layer 11 and the second insulating layer 12 may be a first composite insulating layer of the present disclosure, the third insulating layer 13 and the fourth insulating layer 14 are disposed between the barrier electrode 30 and the source electrode 24 as the second electrode, the third insulating layer 13 and the fourth insulating layer 14 may be a second composite insulating layer of the present disclosure, and the third via hole connecting the source electrode 24 and the shielding electrode 21 may be a connection via hole of the present disclosure.

In an exemplary embodiment, the third via hole connecting the source electrode 24 and the shielding electrode 21 may include a first sub-hole, which is a via hole penetrating the first and second insulating

layers

11 and 12, a second sub-hole, which is a via hole disposed on the blocking electrode 30, and a third sub-hole, which is a via hole penetrating the third and fourth insulating

layers

13 and 14, communicating with each other.

In an exemplary embodiment, an orthographic projection of the first sub-aperture on the substrate may be within a range of an orthographic projection of the second sub-aperture on the substrate, and an orthographic projection of the second sub-aperture on the substrate may be within a range of an orthographic projection of the third sub-aperture on the substrate.

In an exemplary embodiment, a step is formed at an intersection of the second sub-hole and a third sub-hole exposing the second sub-hole and a surface of the barrier electrode 30 on a side away from the substrate.

In an exemplary embodiment, the first sub-hole, the second sub-hole, and the third sub-hole may have an inverted trapezoidal sectional shape in a plane perpendicular to the substrate.

In an exemplary embodiment, the shape of the blocking electrode 30 may be a circular ring shape, an elliptical ring shape, a rectangular ring shape, a pentagonal ring shape, or a hexagonal ring shape in a plane parallel to the substrate.

In an exemplary embodiment, the cross-sectional shape of the barrier electrode 30 may be a trapezoidal shape in a plane perpendicular to the substrate.

In an exemplary embodiment, the fourth conductive layer may adopt a multi-layer composite structure including a first sub-layer, a second sub-layer, and a third sub-layer stacked. In an exemplary embodiment, the first and third sub-layers may be made of titanium (Ti), the second sub-layer may be made of aluminum (Al), and a Ti/Al/Ti three-layer structure with a bottom layer and a top layer of titanium and a middle layer of aluminum is formed.

In an exemplary embodiment, the blocking electrode 30 is disposed at the same layer as the gate electrode 23 of the transistor and is simultaneously formed through the same patterning process.

The following is an exemplary description through a process of manufacturing a display substrate. The "patterning process" referred to in the present disclosure includes processes of coating a photoresist, mask exposure, development, etching, stripping a photoresist, and the like, for a metal material, an inorganic material, or a transparent conductive material, and processes of coating an organic material, mask exposure, development, and the like, for an organic material. The deposition can be any one or more of sputtering, evaporation and chemical vapor deposition, the coating can be any one or more of spraying, spin coating and ink-jet printing, and the etching can be any one or more of dry etching and wet etching, and the disclosure is not limited. "thin film" refers to a layer of a material deposited, coated, or otherwise formed on a substrate. The "thin film" may also be referred to as a "layer" if it does not require a patterning process throughout the fabrication process. If the "thin film" requires a patterning process during the entire fabrication process, it is referred to as "thin film" before the patterning process and "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". In the present disclosure, the term "a and B are disposed in the same layer" means that a and B are formed simultaneously by the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiment of the present disclosure, "the forward projection of B is located within the range of the forward projection of a" or "the forward projection of a includes the forward projection of B" means that the boundary of the forward projection of B falls within the boundary range of the forward projection of a, or the boundary of the forward projection of a overlaps with the boundary of the forward projection of B.

In an exemplary embodiment, the process of preparing the display substrate may include the following operations.

(1) A first conductive layer pattern is formed. In an exemplary embodiment, the forming of the first conductive layer pattern may include: a first conductive film is deposited on the substrate 10, and is patterned through a patterning process to form a first conductive layer pattern disposed on the substrate 10, the first conductive layer pattern including at least a shielding electrode 21, as shown in fig. 7.

In an exemplary embodiment, the shielding electrode 21 is configured as a shielding electrode of a transistor on the one hand and as a gate of a lower transistor on the other hand.

In an exemplary embodiment, the first conductive layer may employ a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), may be a single layer structure, or a multi-layer composite structure, and the like, and may be referred to as a shield (LS) layer.

(2) A semiconductor layer pattern is formed. In an exemplary embodiment, the forming of the semiconductor layer pattern may include: on the substrate formed with the aforementioned pattern, a first insulating film and a semiconductor film are sequentially deposited, and the semiconductor film is patterned by a patterning process to form a first insulating layer 11 covering the first conductive layer pattern, and a semiconductor layer pattern disposed on the first insulating layer 11, where the semiconductor layer pattern at least includes an active layer 22, a position of the active layer 22 corresponds to a position of the shielding electrode 21, and an orthogonal projection of the active layer 22 on the substrate is within an orthogonal projection range of the shielding electrode 21 on the substrate, as shown in fig. 8.

In an exemplary embodiment, the semiconductor thin film may be single crystal silicon, polycrystalline silicon, or oxide, and the disclosure is not limited thereto.

(3) Forming a second conductive layer pattern. In an exemplary embodiment, the forming of the second conductive layer pattern may include: on the substrate on which the aforementioned patterns are formed, a second insulating film and a second conductive film are sequentially deposited, and the second conductive film is patterned through a patterning process to form a second insulating layer 12 covering the semiconductor layer pattern and a second conductive layer pattern disposed on the second insulating layer 12, as shown in fig. 9.

In an exemplary embodiment, the second conductive layer pattern includes at least the gate electrode 23, the blocking electrode 30, and the first plate 41.

In the exemplary embodiment, the position of the gate electrode 23 corresponds to the position of the active layer 22, and the orthographic projection of the gate electrode 23 on the substrate is within the range of the orthographic projection of the active layer 22 on the substrate.

In the exemplary embodiment, the position of the blocking electrode 30 corresponds to the position of the third via hole formed subsequently, the orthographic projection of the blocking electrode 30 on the substrate is within the range of the orthographic projection of the blocking electrode 21 on the substrate, and the orthographic projection of the blocking electrode 30 on the substrate does not overlap with the orthographic projection of the active layer 22 on the substrate. In an exemplary embodiment, the third via is a via connecting the source electrode and the shielding electrode.

In an exemplary embodiment, the first plate 41 is disposed on a side of the second insulating layer 12 away from the substrate, and the first plate 41 is configured to serve as one plate of a storage capacitor in the pixel driving circuit.

Fig. 10 is a schematic plan view of a barrier electrode according to an exemplary embodiment of the present disclosure. As shown in fig. 10, in an exemplary embodiment, the shape of the blocking electrode 30 may be a circular ring shape in a plane parallel to the substrate. In some possible embodiments, the shape of the blocking electrode 30 may also be an elliptical ring shape, a rectangular ring shape, a pentagonal ring shape, a hexagonal ring shape, or the like.

Fig. 11 is a schematic cross-sectional structure diagram of a barrier electrode according to an exemplary embodiment of the present disclosure. As shown in fig. 11, in an exemplary embodiment, the cross-sectional shape of the barrier electrode 30 may be a trapezoidal shape in a plane perpendicular to the substrate.

In an exemplary embodiment, the barrier electrode 30 having a trapezoid shape may include a lower side near a side of the substrate, an upper side far from the side of the substrate, and a side between the lower side and the upper side, and the side may include a first side 31 located inside the loop shape and a second side 32 located outside the loop shape.

In an exemplary embodiment, the second conductive layer pattern may be formed using a dry etching process such that a side slope angle α of the first side 31 may be about 25 ° to 45 °, the side slope angle α may be an angle between a side of the barrier electrode 30 and the substrate plane, and the side slope angle α is configured to control a hole wall slope angle of a subsequently formed third via hole.

In an exemplary embodiment, the side slope angle α of the first side 31 may be about 30 ° to 40 °. For example, the side slope angle α may be about 35 °.

In an exemplary embodiment, the side slope angle of the second side 32 may be the same as or similar to the side slope angle α of the first side 31.

In an exemplary embodiment, the second conductive layer may employ a metal material, such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), and may be referred to as a first GATE metal (GATE1) layer. For example, molybdenum may be used for the second conductive layer.

In an exemplary embodiment, after the patterning process, the semiconductor layer may be subjected to a semiconductor process by masking the second conductive layer, the semiconductor layer that is not masked by the second conductive layer may be subjected to a semiconductor process, a semiconductor source region and a semiconductor drain region may be formed, and the source region and the drain region may be configured to connect a source electrode and a drain electrode that are formed later.

In some possible embodiments, the second insulating film and the second conductive film may be simultaneously patterned through a patterning process in the process, so that the patterns of the second conductive layer and the second insulating layer are substantially the same, and the disclosure is not limited herein.

(4) Forming a third conductive layer pattern. In an exemplary embodiment, the forming of the third conductive layer pattern may include: on the substrate on which the aforementioned patterns are formed, a third insulating film and a third conductive film are sequentially deposited, and the third conductive film is patterned through a patterning process to form a third insulating layer 13 covering the second conductive layer pattern and a third conductive layer pattern disposed on the third insulating layer 13, as shown in fig. 12.

In an exemplary embodiment, the third conductive layer pattern includes at least a second plate 42, a position of the second plate 42 corresponds to a position of the first plate 41, and an orthogonal projection of the second plate 42 on the substrate at least partially overlaps an orthogonal projection of the first plate 41 on the substrate.

In an exemplary embodiment, the second plate 42 is disposed on a side of the third insulating layer 13 away from the substrate, the second plate 42 is configured to serve as the other plate of the storage capacitor in the pixel driving circuit, and the first plate 41 and the second plate 42 constitute the storage capacitor of the pixel driving circuit.

In an exemplary embodiment, the third conductive layer may use a metal material, such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), and may be referred to as a second GATE metal (GATE2) layer. For example, molybdenum may be used for the third conductive layer.

In some possible embodiments, the third insulating film and the third conductive film may be simultaneously patterned through a patterning process in the process, so that the patterns of the third conductive layer and the third insulating layer are substantially the same, and the disclosure is not limited herein.

(5) A fourth insulating layer pattern is formed. In an exemplary embodiment, the forming of the fourth insulation layer pattern may include: on the substrate on which the aforementioned pattern is formed, a fourth insulating film is deposited, and the fourth insulating film is patterned by a patterning process to form a fourth insulating layer 14 pattern covering the third conductive layer pattern, as shown in fig. 13.

In an exemplary embodiment, the fourth insulation layer 14 pattern includes at least a first via K1, a second via K2, and a third via K3.

In an exemplary embodiment, an orthographic projection of the first via K1 on the substrate may be within an orthographic projection of the source region of the active layer 22 on the substrate, the fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12 within the first via K1 are etched away to expose a surface of the source region of the active layer 22, and the first via K1 is configured to connect a subsequently formed source electrode with the source region of the active layer 22 through the via.

In an exemplary embodiment, an orthographic projection of the second via K2 on the substrate may be within an orthographic projection of the drain region of the active layer 22 on the substrate, the fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12 within the second via K2 are etched away to expose a surface of the drain region of the active layer 22, and the second via K2 is configured to connect a subsequently formed drain electrode with the drain region of the active layer 22 through the via.

In an exemplary embodiment, an orthographic projection of the third via K3 on the substrate may be within an orthographic projection of the shielding electrode 21 on the substrate, the fourth insulating layer 14, the third insulating layer 13, the second insulating layer 12, and the first insulating layer 11 within the third via K3 are etched away to expose a surface of the shielding electrode 21, and the third via K3 is configured to connect a subsequently formed source electrode with the shielding electrode 21 through the via.

Fig. 14 is a schematic cross-sectional structure view of a third via according to an exemplary embodiment of the disclosure. As shown in fig. 14, the third via hole may include a first sub hole K11, a second sub hole K12, and a third sub hole K13 communicating with each other in a plane perpendicular to the substrate, and the first sub hole K11, the second sub hole K12, and the third sub hole K13 constitute a step-structured third via hole.

In an exemplary embodiment, the first sub-hole K11 may be a via hole opened on the second insulating layer 12 and the first insulating layer 11, the second insulating layer 12 and the first insulating layer 11 in the first sub-hole K11 are etched away to expose the surface of the shielding electrode 21, and the first insulating layer 11 and the second insulating layer 12 may serve as the first composite insulating layer of the present exemplary embodiment.

In an exemplary embodiment, the second sub-hole K12 may be a via hole disposed on the barrier electrode 30, the second sub-hole K12 exposes the first sub-hole K11, and an orthographic projection of the first sub-hole K11 on the substrate may be within a range of an orthographic projection of the second sub-hole K12 on the substrate.

In an exemplary embodiment, the third sub-hole K13 may be a via hole opened on the fourth insulating layer 14 and the third insulating layer 13, the fourth insulating layer 14 and the third insulating layer 13 in the third sub-hole K13 are etched away to expose the second sub-hole K12 and a portion of the surface of the barrier electrode 30 on the side away from the substrate, an orthographic projection of the second sub-hole K12 on the substrate may be within an orthographic projection of the third sub-hole K13 on the substrate, and the third insulating layer 13 and the fourth insulating layer 14 may serve as the second composite insulating layer of the present exemplary embodiment.

In an exemplary embodiment, a step is formed at an interface of the second sub-hole K12 and the third sub-hole K13, and the third sub-hole K13 exposes the second sub-hole K12 and a surface of the barrier electrode 30 on a side away from the substrate, that is, the step in the step structure is a surface of the barrier electrode 30 on a side away from the substrate.

In an exemplary embodiment, the cross-sectional shape of the first sub-hole K11 may be an inverted trapezoid in a plane perpendicular to the substrate, and the first hole wall slope angle θ 1 of the hole walls of the first sub-hole K11 may be about 55 ° to 75 °.

In an exemplary embodiment, the cross-sectional shape of the second sub-hole K12 may be an inverted trapezoid in a plane perpendicular to the substrate, the hole wall of the second sub-hole K12 is the first side 31 of the barrier electrode 30, the second hole wall slope angle θ 2 of the hole wall of the second sub-hole K12 is the side slope angle α of the first side 31 of the barrier electrode 30, and the second hole wall slope angle θ 2 may be about 25 ° to 45 °.

In an exemplary embodiment, the cross-sectional shape of the third sub-hole K13 may be an inverted trapezoid in a plane perpendicular to the substrate, and the third hole wall slope angle θ 3 of the hole wall of the third sub-hole K13 may be about 55 ° to 80 °.

In an exemplary embodiment, the hole wall slope angle may be the angle between the inner wall of the hole and the base plane.

In an exemplary embodiment, the third bore wall angle θ 3 may be greater than the first bore wall angle θ 1, and the first bore wall angle θ 1 may be greater than the second bore wall angle θ 2.

In an exemplary embodiment, the first bore wall angle θ 1 may be about 55 ° to 70 °. For example, the first bore wall angle θ 1 may be about 60 °.

In an exemplary embodiment, the second bore wall angle θ 2 may be about 30 ° to 40 °. For example, the second bore wall angle θ 2 may be about 35 °.

In an exemplary embodiment, the third aperture wall slope angle θ 3 may be about 60 ° to 80 °. For example, the third aperture wall slope angle θ 3 may be about 70 °.

In an exemplary embodiment, the forming of the fourth insulation layer pattern may include: after a fourth insulating film is deposited on the substrate on which the patterns are formed, a layer of photoresist is coated, the photoresist is exposed by using a common mask plate, a photoresist pattern is formed after development, the photoresist pattern comprises an exposure area and an unexposed area, the exposure area is respectively the area where the first through hole K1, the second through hole K2 and the third through hole K3 are located, the photoresist in the exposure area is removed, the surface of the fourth insulating film is exposed, and the photoresist in the unexposed area is reserved. Then, the exposure region is etched by using a dry etching process to form a first via hole K1, a second via hole K2 and a third via hole K3, respectively. Finally, the remaining photoresist is stripped.

In an exemplary embodiment, in the process of forming the third via hole K3, after the fourth insulating film and the third insulating film are etched away, the blocking electrode 30 is exposed, and the second sub-hole K12 and the third sub-hole K13 are formed, the second sub-hole K12 is located in the third sub-hole K13, and an orthographic projection of the second sub-hole K12 on the substrate is located within an orthographic projection of the third sub-hole K13 on the substrate. Subsequently, the second insulating layer 12 and the first insulating layer 11, which are not shielded by the blocking electrode 30, in the second sub-hole K12 are etched by using the blocking electrode 30 as a mask (hard mask), so as to form a first sub-hole K11 exposing the shielding electrode 21, wherein the first sub-hole K11 is located in the second sub-hole K12, an orthographic projection of the first sub-hole K11 on the substrate is located in a range of an orthographic projection of the second sub-hole K12 on the substrate, and a step-structured third via hole K3 is formed.

In an exemplary embodiment, since the photoresist is used as a mask in forming the third sub-hole K13, the hole wall of the third sub-hole K13 etched by using a dry etching process has a large hole wall slope angle. Since the barrier electrode 30 blocks the formation of the second sub-hole K12, the etching degree of the barrier electrode 30 is small, so that the hole wall slope angle of the second sub-hole K12 is substantially the same as or close to the side slope angle of the first side 31 of the barrier electrode 30, and a platform with a step structure is formed, wherein the platform is the surface of the barrier electrode 30 on the side away from the substrate. Because the first side edge 31 of the blocking electrode 30 is used as a mask in the process of forming the first sub-hole K11, the side slope angle of the first side edge 31 is about 25 degrees to 45 degrees, and the hole wall slope angle of the etched first sub-hole K11 is about 20 degrees to 25 degrees larger than the side slope angle, the hole wall slope angle of the first sub-hole K11 can be about 55 degrees to 75 degrees, and the hole wall slope angle is smaller. Compared with the existing structure, the hole wall gradient angle of the first sub-hole can be reduced by about 15 degrees to 25 degrees, the film deposition quality of the subsequent fourth conductive film is facilitated, and the yield is improved.

(6) Forming a fourth conductive layer pattern. In an exemplary embodiment, the forming of the fourth conductive layer pattern may include: on the substrate on which the aforementioned pattern is formed, a fourth conductive film is deposited, and the fourth conductive film is patterned through a patterning process, forming a fourth conductive layer pattern on the fourth insulating layer 14, as shown in fig. 15. In an exemplary embodiment, the fourth conductive layer may be referred to as a first source drain metal (SD1) layer.

In an exemplary embodiment, the fourth conductive layer pattern includes at least a source electrode 24 and a drain electrode 25, the source electrode 24 is connected to the source region of the active layer 22 through the first via hole K1 on the one hand, and is connected to the shielding electrode 21 through the third via hole K3 on the other hand, and the drain electrode 25 is connected to the drain region of the active layer 22 through the second via hole K2.

Fig. 16 is a schematic structural diagram of a source electrode and a shielding electrode according to an exemplary embodiment of the disclosure. As shown in fig. 16, in an exemplary embodiment, the fourth conductive layer may adopt a multilayer composite structure, and include a first sub-layer 51, a second sub-layer 52, and a third sub-layer 53 stacked, where the first sub-layer 51 is disposed on a side of the fourth insulating layer 14 away from the substrate, the second sub-layer 52 is disposed on a side of the first sub-layer 51 away from the substrate, and the third sub-layer 53 is disposed on a side of the second sub-layer 52 away from the substrate.

In an exemplary embodiment, the first and third sub-layers 51 and 53 may employ titanium (Ti), and the second sub-layer 52 may employ aluminum (Al) to constitute a Ti/Al/Ti three-layer structure.

In an exemplary embodiment, since the third via hole has a stepped structure, which divides the third via hole into the first sub hole, the second sub hole, and the third sub hole, which are communicated with each other, the deposition depth of the fourth conductive film in the hole is minimized, which is equivalent to the deposition in the first sub hole, the second sub hole, and the third sub hole, respectively. That is, the fourth conductive film is deposited in the first sub-hole with the first depth, the second sub-hole with the second depth and the third sub-hole with the third depth, instead of the fourth conductive film being deposited in the via hole with the first depth + the second depth + the third depth, so that the thickness of the aluminum layer at the bottom of the via hole is ensured, and the piercing risk caused by burrs in the via hole is reduced to the maximum extent.

In an exemplary embodiment, because the third via hole K3 is a step structure, the hole wall slope angle of the whole third via hole is effectively reduced, the first sub-layer can better cover the side walls of the first sub-hole, the second sub-hole and the third sub-hole, and the third sub-layer can better cover the aluminum layer, so that the aluminum layer is covered and coated by the titanium layer, and the oxidation and corrosion risks caused by the exposure of the aluminum layer are reduced to the maximum extent.

To this end, a driving circuit layer including a transistor and a storage capacitor may be formed on a substrate, the storage capacitor may include a first plate 41 and a second plate 42, the transistor of the dual gate structure may include a lower transistor and an upper transistor of the same channel, the upper transistor may include an active layer 22, a gate electrode 23, a source electrode 24, and a drain electrode 25, and the lower transistor may include the active layer 22, a shielding electrode 21, the source electrode 24, and the drain electrode 25. Because the signal voltage value of the grid (shielding electrode) of the lower transistor is smaller than that of the grid (grid electrode) of the upper transistor, the negative bias degree of the threshold voltage of the lower transistor is smaller than that of the threshold voltage of the upper transistor, the overall negative bias degree of the transistor can be reduced, the stability of the transistor is ensured, and the uniformity of the electrical characteristics of the transistor is ensured.

The subsequent manufacturing process may include processes of forming a first planarization layer, a second source-drain metal (SD2), a second planarization layer, a light emitting structure layer, and a package structure layer, which are not described herein again.

In an exemplary embodiment, the substrate may be a rigid substrate, which may be glass or quartz, or a flexible substrate, which may be a single-layer structure or a stacked-layer structure including a flexible material layer. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer may be referred to as a Buffer (Buffer) layer, the second and third insulating layers may be referred to as a gate insulating layer (GI), and the fourth insulating layer may be referred to as an interlayer Insulating (ILD) layer.

According to the display substrate structure and the manufacturing process of the display substrate, the barrier electrode is arranged, the third via hole connected with the source electrode and the shielding electrode is arranged to be of the step structure, the hole wall gradient angle of the third via hole is integrally reduced, the thickness of the aluminum layer at the bottom of the via hole is guaranteed, the piercing risk caused by burrs in the hole is reduced to the maximum extent, the covering and cladding of the titanium layer on the top layer on the aluminum layer are guaranteed, the oxidation and corrosion risks caused by exposure of the aluminum layer are reduced to the maximum extent, the film deposition quality in the via hole is improved, the problems that the existing manufacturing process is low in yield and the like are effectively solved, and the yield is improved.

According to the manufacturing method of the semiconductor device, the blocking electrode is arranged in the second conducting layer, the blocking electrode and the gate electrode are arranged on the same layer and are formed synchronously through the same patterning process, the patterning process is not additionally added, the manufacturing process is simple, the process compatibility is good, the process quality is guaranteed, and the production cost is reduced.

Fig. 17 is a schematic cross-sectional structure view of another display substrate according to an exemplary embodiment of the disclosure, and fig. 18 is a schematic cross-sectional structure view of another third via according to an exemplary embodiment of the disclosure. As shown in fig. 17 and 18, the main structure of the display substrate of the present exemplary embodiment is similar to that of the foregoing embodiments, and the display substrate may include a substrate 10, and a first conductive layer, a first insulating layer 11, a semiconductor layer, a second insulating layer 12, a second conductive layer, a third insulating layer 13, a third conductive layer, a fourth insulating layer 14, and a fourth conductive layer sequentially disposed on the substrate 10. Unlike the foregoing exemplary embodiment, the barrier electrode 30 of the present exemplary embodiment is provided in the third conductive layer.

In an exemplary embodiment, the third via hole may include a first sub hole K11, a second sub hole K12, and a third sub hole K13 communicating with each other in a plane perpendicular to the substrate, and the first sub hole K11, the second sub hole K12, and the third sub hole K13 constitute a stepped-structure third via hole.

In an exemplary embodiment, the first sub-hole K11 may be a via hole opened on the third insulating layer 13, the second insulating layer 12, and the first insulating layer 11, the third insulating layer 13, the second insulating layer 12, and the first insulating layer 11 in the first sub-hole K11 are etched away to expose a surface of the shielding electrode 21, and the first insulating layer 11, the second insulating layer 12, and the third insulating layer 13 may serve as the first composite insulating layer of the present exemplary embodiment.

In an exemplary embodiment, the third sub-hole K13 may be a via hole opened on the fourth insulating layer 14, the fourth insulating layer 14 in the third sub-hole K13 is etched away to expose the second sub-hole K12 and a portion of the surface of the blocking electrode 30 on the side away from the substrate, an orthographic projection of the second sub-hole K12 on the substrate may be within an orthographic projection of the third sub-hole K13 on the substrate, and the fourth insulating layer 14 may serve as the second composite insulating layer of the present exemplary embodiment.

In an exemplary embodiment, parameters of the cross-sectional shape and the slope angle of the barrier electrode 30, the first sub-hole K11, the second sub-hole K12, and the third sub-hole K13 may be substantially the same as or similar to those of the previous embodiments.

In an exemplary embodiment, a manufacturing process of the display substrate of this exemplary embodiment may be substantially similar to that of the foregoing embodiment, except that no blocking electrode is formed in the second conductive layer pattern, and a blocking electrode and a second electrode plate are simultaneously formed when the third conductive layer pattern is formed, the blocking electrode being located corresponding to a location of a third via hole to be subsequently formed, an orthogonal projection of the blocking electrode on the substrate being within a range of an orthogonal projection of the blocking electrode on the substrate, the orthogonal projection of the blocking electrode on the substrate not overlapping an orthogonal projection of the active layer on the substrate. In forming the fourth insulation layer pattern, a third via hole of a stepped structure is formed using the blocking electrode.

The display substrate of the exemplary embodiment can also improve the deposition quality of the film layer in the through hole, and effectively solves the problems of low yield and the like in the existing preparation process. The barrier electrode and the second electrode plate are arranged on the same layer and are synchronously formed through the same patterning process, so that the patterning process is not additionally arranged, the preparation process is simple, the process compatibility is good, the process quality is favorably ensured, and the production cost is favorably reduced.

Fig. 19 is a schematic cross-sectional structure view of a display substrate according to still another exemplary embodiment of the disclosure, and fig. 20 is a schematic cross-sectional structure view of a third via according to yet another exemplary embodiment of the disclosure. As shown in fig. 19 and 20, the main structure of the display substrate of the present exemplary embodiment is similar to that of the foregoing embodiments, and the display substrate may include a substrate 10, and a first conductive layer, a first insulating layer 11, a semiconductor layer, a second insulating layer 12, a second conductive layer, a third insulating layer 13, a third conductive layer, a fourth insulating layer 14, and a fourth conductive layer sequentially disposed on the substrate 10. Unlike the foregoing exemplary embodiment, the present exemplary embodiment includes the first barrier electrode 30A disposed in the second conductive layer and the second barrier electrode 30B disposed in the third conductive layer.

In an exemplary embodiment, the third via hole may include a first sub hole K11, a second sub hole K12, a fourth sub hole K14, a fifth sub hole K15, and a third sub hole K13 that are communicated with each other in a plane perpendicular to the substrate, and the first sub hole K11, the second sub hole K12, the fourth sub hole K14, the fifth sub hole K15, and the third sub hole K13 constitute the third via hole of a stepped structure.

In an exemplary embodiment, the second sub-hole K12 may be a via hole disposed on the first barrier electrode 30A, the second sub-hole K12 exposes the first sub-hole K11, and an orthographic projection of the first sub-hole K11 on the substrate may be within a range of an orthographic projection of the second sub-hole K12 on the substrate.

In an exemplary embodiment, the fourth sub-hole K14 may be a via hole opened on the third insulating layer 13, the third insulating layer 13 in the fourth sub-hole K14 is etched away to expose the second sub-hole K12 and a portion of the surface of the first blocking electrode 30A on the side away from the substrate, and an orthographic projection of the second sub-hole K12 on the substrate may be within an orthographic projection of the fourth sub-hole K14 on the substrate.

In an exemplary embodiment, the fifth sub hole K15 may be a via hole disposed on the second barrier electrode 30B, the fifth sub hole K15 exposes the fourth sub hole K14, and an orthographic projection of the fourth sub hole K14 on the substrate may be within a range of an orthographic projection of the fifth sub hole K15 on the substrate.

In an exemplary embodiment, the third sub-hole K13 may be a via hole opened on the fourth insulating layer 14, the fourth insulating layer 14 in the third sub-hole K13 is etched away to expose the fifth sub-hole K15 and a portion of the surface of the second blocking electrode 30B on the side away from the substrate, an orthographic projection of the fifth sub-hole K15 on the substrate may be within an orthographic projection of the third sub-hole K13 on the substrate, and the fourth insulating layer 14 may serve as the second composite insulating layer of the present exemplary embodiment.

In an exemplary embodiment, a step is formed at an interface of the second sub-hole K12 and the fourth sub-hole K14, and the fourth sub-hole K14 exposes the second sub-hole K12 and a surface of the first barrier electrode 30A on a side away from the substrate, that is, one step in the step structure is a surface of the first barrier electrode 30A on a side away from the substrate.

In an exemplary embodiment, another step is formed at an interface of the fifth sub-hole K15 and the third sub-hole K13, and the third sub-hole K13 exposes the fifth sub-hole K15 and a portion of the surface of the second barrier electrode 30B on the side away from the substrate, i.e., another step in the step structure is the surface of the second barrier electrode 30B on the side away from the substrate.

In an exemplary embodiment, parameters of the sectional shape and the slope angle of the first and

second barrier electrodes

30A and 30B may be substantially the same as or similar to those of the barrier electrodes in the previous embodiments, and parameters of the sectional shape and the wall slope angle of the first, second, and third sub-holes K11, K12, and K13 may be substantially the same as or similar to those of the previous embodiments.

In an exemplary embodiment, the cross-sectional shapes of the fourth sub-hole K14 and the fifth sub-hole K15 may be inverse trapezoids, the fourth hole wall slope angle of the hole walls of the fourth sub-hole K14 may be about 55 ° to 75 °, and the fifth hole wall slope angle of the hole walls of the fifth sub-hole K15 may be about 25 ° to 45 °, in a plane perpendicular to the substrate.

In an exemplary embodiment, the fourth aperture wall angle may be less than the third aperture wall angle and the fourth aperture wall angle may be greater than the first aperture wall angle.

In an exemplary embodiment, the hole wall of the second sub-hole K12 may be a side edge of the first barrier electrode 30A, and the second hole wall slope angle of the hole wall of the second sub-hole K12 may be a side edge slope angle of the first barrier electrode 30A. The hole wall of the fifth sub-hole K15 may be the side edge of the second barrier electrode 30B, and the fifth hole wall slope angle of the hole wall of the fifth sub-hole K15 may be the side edge slope angle of the second barrier electrode 30B.

In an exemplary embodiment, a manufacturing process of the display substrate of the present exemplary embodiment may be substantially similar to that of the foregoing embodiment, except that a first blocking electrode is formed in the formed second conductive layer pattern, and a second blocking electrode is formed in the formed third conductive layer pattern, positions of the first blocking electrode and the second blocking electrode correspond to positions of subsequently formed third via holes, orthographic projections of the first blocking electrode and the second blocking electrode on the substrate are within a range of orthographic projections of the blocking electrode on the substrate, and the orthographic projections of the first blocking electrode and the second blocking electrode on the substrate do not overlap with an orthographic projection of the active layer on the substrate. In forming the fourth insulating layer pattern, a third via hole having a stepped structure is formed using the first and second barrier electrodes.

The display substrate of the exemplary embodiment can also improve the deposition quality of the film layer in the through hole, and effectively solves the problems of low yield and the like in the existing preparation process. Because the first blocking electrode and the gate electrode are arranged on the same layer and are synchronously formed through the same patterning process, and the second blocking electrode and the second electrode plate are arranged on the same layer and are synchronously formed through the same patterning process, the patterning process is not additionally added, the preparation process is simple, the process compatibility is good, the process quality is favorably ensured, and the production cost is favorably reduced.

The structure and the preparation process thereof shown in the exemplary embodiments of the present disclosure are only exemplary illustrations, and the corresponding structure may be changed and the patterning process may be added or reduced according to actual needs, and the present disclosure is not limited herein.

The display substrate of the present disclosure may be applied to a display device having a pixel driving circuit, such as an OLED, a QLED, a light emitting diode display (Micro LED or Mini LED), a quantum dot light emitting diode display (QDLED), and may also be applied to other display devices, such as a liquid crystal display, a plasma display, or an electrophoretic display, and the disclosure is not limited herein.

The present disclosure also provides a method of manufacturing a display substrate, which may include, in an exemplary embodiment:

The present disclosure also provides a display device including the display substrate of the foregoing embodiment. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame or a navigator, etc.

Although the embodiments disclosed in the present disclosure are described above, the descriptions are only for the convenience of understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art of the present disclosure that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the present disclosure is to be limited only by the terms of the appended claims.

Claims

1. The display substrate is characterized by comprising a first electrode, a blocking electrode and a second electrode which are sequentially arranged on a substrate, wherein the second electrode is connected with the first electrode through a connecting through hole, the orthographic projection of the blocking electrode on the substrate is at least partially overlapped with the orthographic projection of the connecting through hole on the substrate, and the blocking electrode is configured to enable the hole wall of the connecting through hole to be of a step structure.

2. The display substrate of claim 1, further comprising: a first composite insulating layer disposed between the first electrode and the barrier electrode, a second composite insulating layer disposed between the barrier electrode and the second electrode; the connecting via hole comprises a first sub-hole, a second sub-hole and a third sub-hole which are communicated with each other, the first sub-hole is a via hole formed in the first composite insulating layer, the second sub-hole is a via hole formed in the blocking electrode, and the third sub-hole is a via hole formed in the second composite insulating layer.

3. The display substrate of claim 2, wherein an orthographic projection of the first sub-aperture on the base is within an orthographic projection of the second sub-aperture on the base, and wherein an orthographic projection of the second sub-aperture on the base is within an orthographic projection of the third sub-aperture on the base.

4. The display substrate according to claim 2, wherein a step is formed at an intersection of the second sub-hole and a third sub-hole, and the third sub-hole exposes the second sub-hole and a surface of the barrier electrode on a side away from the substrate.

5. The display substrate of claim 2, wherein the cross-sectional shapes of the first sub-aperture, the second sub-aperture and the third sub-aperture are inverse trapezoid shapes in a plane perpendicular to the base.

6. The display substrate of claim 2, wherein the third sub-hole has a hole wall slope angle greater than the first sub-hole, the first sub-hole has a hole wall slope angle greater than the second sub-hole, and the hole wall slope angle is an angle between an inner wall of the hole and the base plane.

7. The display substrate of claim 6, wherein the first sub-aperture has an aperture wall slope angle of 55 ° to 75 °.

8. The display substrate of claim 6, wherein the second sub-wells have a wall slope angle of 25 ° to 45 °.

9. The display substrate of claim 6, wherein the hole wall diffusion angle of the third sub-hole is 55 ° to 80 °.

10. The display substrate according to claim 1, wherein the barrier electrode has a circular ring shape, an elliptical ring shape, a rectangular ring shape, a pentagonal ring shape, or a hexagonal ring shape in a plane parallel to the base.

11. The display substrate of claim 10, wherein the cross-sectional shape of the blocking electrode in a plane perpendicular to the substrate is a trapezoid shape, a side slope angle of the blocking electrode at the outer side of the ring shape is 25 ° to 45 °, and the side slope angle is an angle between a side of the blocking electrode and the substrate plane.

12. The display substrate according to any one of claims 1 to 11, wherein the display substrate comprises a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a fourth conductive layer, which are sequentially provided over a base, wherein the first electrode is provided in the first conductive layer, the second electrode is provided in the fourth conductive layer, and the blocking electrode is provided in the second conductive layer and/or the third conductive layer.

13. The display substrate according to claim 12, wherein the first electrode is a shielding electrode, and the second electrode is a source electrode of a transistor.

14. A display device comprising the display substrate according to any one of claims 1 to 13.

15. A method for preparing a display substrate is characterized by comprising the following steps: