CN114143520B - Method for realizing multi-channel HDMI interface transmission and automatic correction - Google Patents

Abstract

The invention provides a method for realizing multi-channel HDMI interface transmission and automatic correction, which can realize the simultaneous input of two channels of HDMI video image data and output of the two channels of HDMI interface image data through image recognition, image correction and image caching. Meanwhile, the invention supports the functions of automatically identifying HDMI source end pixels and compensating correction, and improves the error correction capability and stability of the system. The method relates to 4K high-definition video transceiving, image recognition, image correction, image caching and display technologies, in particular to a comprehensive display method for realizing multipath 4K high-definition image processing based on FPGA.

Description

A method for realizing multi-channel HDMI interface transmission and automatic correction

Technical field

The present invention relates to the field of image processing technology, and in particular to a method for realizing multi-channel HDMI interface transmission and automatic correction.

Background technique

FPGA is a field programmable gate array. It is a programmable chip based on programmable devices such as PAL, GAL, and CPLD. It appears as a semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gates in the original programmable device.

Currently, with the vigorous development of various high-definition display devices on the market, monitors support increasingly higher resolutions, and 4K high-definition video applications are becoming more and more common. Most methods of implementing HDMI interface transmission based on FPGA rely on imported chips. After decoding the HDMI video, it is transmitted to the FPGA through a large number of parallel data lines, which greatly increases the wiring resources, is high in cost and has poor flexibility.

At the same time, HDMI interface transmission video has increasingly higher requirements for system stability. Especially when the entire system requires domestic replacement, domestic GPUs are used as the source to output HDMI signals to the next level. Since domestic GPUs are in their infancy, the output HDMI signals occasionally have unstable problems such as missing or extra pixels. , will cause the output picture to be jittered or even black screen after processing by the receiving end, resulting in unstable output and poor user experience.

Contents of the invention

The purpose of the present invention is to provide a method for realizing multi-channel HDMI interface transmission and automatic correction in view of the above-mentioned shortcomings of the existing technology, overcoming the traditional technical solutions that rely on imported clock chips or video decoding chips, and completely The FPGA independently implements multi-channel HDMI interface transmission.

In order to achieve the above objects, the present invention adopts the following technical solutions:

The invention provides a method for realizing multi-channel HDMI interface transmission and automatic correction, which includes the following steps:

S1. Connect the HDMI signal source to the FPGA. The source obtains the EDID of the FPGA through I2C and sends TMDS data and TMDS clock to the FPGA;

S2. HDMI input interface PHY completes the basic configuration of the HDMI interface PHY end and converts high-speed TMDS serial data into parallel data;

S3. HDMI input MAC unit to complete the configuration of the HDMI receiving end MAC, extract the valid information of the data frame, identify the resolution, frame frequency, color depth, and data format information of the source end, and parse out the frame header, end of each line flag, valid Data enable and valid data;

S4. The image processing unit completes the column correction function of the analyzed image data;

S5. The image data column corrected data is cached in FIFO_W, written to DDR, and the column pixels of the source data are corrected;

S6. After writing two frames of images to the DDR, start reading image data from the DDR and write it to FIFO_R;

S7. When the number of data in the FIFO_R is greater than M, start reading data from the FIFO_R;

S8. The HDMI output MAC unit mainly completes the configuration of the HDMI transmitter MAC. According to the EDID of the reading sink, it sets the resolution, frame rate, color depth, and data format information of the output image data. It receives the data of the FIFO_R and outputs rows in time sequence. , field and valid data;

S9, HDMI output interface PHY completes the basic configuration of the HDMI interface PHY end, and converts parallel data into high-speed TMDS serial data and clock.

Further, the image processing unit performs an image sequence correction function on the input image data, and corrects the phenomenon of missing or redundant pixels in the source image sequence.

Furthermore, it also includes timing optimization of standard image data. The steps are as follows:

S10. Detect the frame header, clear all counts, and start line counting of valid data. When the end flag of each line is valid, the line count is cleared;

S20. When the end of each line flag is valid, the column calculation is incremented by one, and the frame header is cleared when it arrives;

S30. Compare whether the value of the column count when the end flag of each row is valid is equal to the number of pixel columns identified in S30.

If the total number of pixel columns at the source is less than the total number of pixel columns identified in S30, then the number of pixel columns is supplemented;

If the total number of source pixel columns is greater than the value of the pixel column identified in S30, the excess pixel columns are deleted so that they are output as standard pixels.

Further, the source image column pixels are corrected, including the following steps:

S100. When the header of each frame of image data is valid, start writing the corrected image valid data of column S4 into FIFO_W;

S200. When the number of data in the FIFO_W is greater than M, start writing image data to DDR until all valid data in a frame are written to DDR. Each frame of data occupies a space address of DDR of N;

S300. When the frame header of the next frame is valid, perform a frame count on the written frame image data. Clear the frame count when it reaches three, start to repeat the S100 and the S200, and continuously cache the source valid data to the DDR;

Among them, when the header of each frame is valid, image data is written starting from the address space 0, N, 2N, and 3N of the DDR. This ensures that when the source row pixels are lacking, they will be automatically added to the total number of rows specified by the protocol. At the same time, it ensures that when the source row pixels are excess, they will be automatically trimmed to the total number of rows specified by the protocol, making it a stable output.

The beneficial effects of the present invention are: realizing an image processing method for multi-channel HDMI interface transmission based on FPGA. By inputting the image data of the two HDMI interfaces into the FPGA and entering the HDMI input processing unit, the serial-to-parallel conversion and information extraction are completed, and the identification to the resolution and frame rate of the source video image, input the recognized image data to the image processing unit, convert it into standard pixel image data through correction method, cache it to DDR, and then read out the image data and Two channels of image data are output through the HDMI interface output unit.

It can eliminate the phenomenon of occasional missing or extra pixels at the source end causing the output picture to jitter or even black screen, improve the stability of HDMI interface transmission, and meet the technical requirements in the display field.

At the same time, the present invention supports correction output for occasional missing or redundant pixels at the signal source end, improving error correction capabilities and stability. It is used to solve existing comprehensive display technology problems, improve the stability of HDMI interface transmission, and enhance user experience.

Description of the drawings

Figure 1 is a timing diagram of images parsed by the present invention at the source end;

Figure 2 is an image timing diagram showing missing pixels in the source column;

Figure 3 is an image timing diagram showing redundant pixels in the source column;

Figure 4 is an image correction cache diagram of a method for realizing multi-channel HDMI interface transmission and automatic correction.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described here are only used to explain the present invention and are not intended to limit the present invention.

Please refer to Figure 1, a method to implement multi-channel HDMI interface transmission and automatic correction, including the following steps:

S1. Connect the HDMI signal source to the FPGA. The source obtains the EDID of the FPGA through I2C and sends TMDS data and TMDS clock to the FPGA;

Among them, the main function of S1 is to connect the HDMI interfaces of the source and sink. The source will obtain the EDID information of the sink before sending a signal to the sink.

S2. HDMI input interface PHY completes the basic configuration of the HDMI interface PHY end and converts high-speed TMDS serial data into parallel data;

Among them, the main function of S2 is to convert high-speed HDMI serial signals into parallel signals and provide them for post-processing.

S3. HDMI input MAC unit to complete the configuration of the HDMI receiving end MAC, extract the valid information of the data frame, identify the resolution, frame frequency, color depth, and data format information of the source end, and parse out the frame header, end of each line flag, valid Data enable and valid data;

Among them, the main function of S3 is to obtain the resolution, frame rate and other information of the source signal source, and provide it to the subsequent image processing unit for image correction.

S4. The image processing unit completes the column correction function of the analyzed image data;

Among them, the main function of S4 is to correct the phenomenon of missing or extra pixels in the source image sequence.

Please refer to Figure 4, S5. The image data column corrected data is buffered through FIFO_W, written to DDR, and the column pixels of the source data are corrected;

Among them, the function of S5 is to correct the phenomenon of missing or extra pixels in the source image line.

S6. After writing two frames of images to the DDR, start reading image data from the DDR and write it to FIFO_R;

Among them, the role of S6 is to cache valid image data to DDR.

S7. When the number of data in the FIFO_R is greater than M, start reading data from the FIFO_R;

Among them, the function of S7 is to read and cache the image data in DDR into FIFO to prepare for output to the next level.

S8. The HDMI output MAC unit mainly completes the configuration of the HDMI transmitter MAC. According to the EDID of the reading sink, it sets the resolution, frame rate, color depth, and data format information of the output image data. It receives the data of the FIFO_R and outputs rows in time sequence. , field and valid data;

Among them, the role of S8 is to provide HDMI output resolution, frame rate, color depth, data format and other information to prepare for output.

S9, HDMI output interface PHY completes the basic configuration of the HDMI interface PHY end, and converts parallel data into high-speed TMDS serial data and clock.

Among them, the function of S9 is to output HDMI high-speed serial signals as the source end.

The image processing unit performs an image column correction function on the input image data, and corrects the phenomenon of missing or redundant pixels in the source image column.

Please refer to Figure 1 to Figure 3, which also includes standard image data timing optimization. The steps are as follows:

S10. Detect the frame header, clear all counts, and start line counting of valid data. When the end flag of each line is valid, the line count is cleared;

S20. When the end of each line flag is valid, the column calculation is incremented by one, and the frame header is cleared when it arrives;

S30. Compare whether the value of the column count when the end flag of each row is valid is equal to the number of pixel columns identified in S30.

If the total number of pixel columns at the source is less than the total number of pixel columns identified in S30, then the number of pixel columns is supplemented;

If the total number of source pixel columns is greater than the value of the pixel column identified in S30, the excess pixel columns are deleted so that they are output as standard pixels.

The image processing unit performs an image row correction function on the input image data, which mainly corrects and corrects the phenomenon of missing or redundant pixels in the source image rows; the source image column pixel correction includes the following steps:

S100. When the header of each frame of image data is valid, start writing the corrected image valid data of column S4 into FIFO_W;

S200. When the number of data in the FIFO_W is greater than M, start writing image data to DDR until all valid data in a frame are written to DDR. Each frame of data occupies a space address of DDR of N;

S300. When the frame header of the next frame is valid, perform a frame count on the written frame image data. Clear the frame count when it reaches three, start to repeat the S100 and the S200, and continuously cache the source valid data to the DDR;

Among them, when the header of each frame is valid, image data is written starting from the address space 0, N, 2N, and 3N of the DDR.

The above-mentioned embodiments only express the implementation of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the patent scope of the present invention. It should be noted that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the scope of protection of the patent of the present invention should be determined by the appended claims.

Claims (3)

1. The method for realizing the transmission and automatic correction of the multipath HDMI interface is characterized by comprising the following steps:

s1, connecting an HDMI signal source to an FPGA, acquiring the EDID of the FPGA by a source end through an I2C, and transmitting TMDS data and a TMDS clock to the FPGA;

s2, the HDMI input interface PHY completes basic configuration of an HDMI interface PHY end, and high-speed TMDS serial data are converted into parallel data;

s3, HDMI inputs the MAC unit to complete the configuration of the HDMI receiving end MAC, extracts the effective information of the data frame, identifies the resolution, frame frequency, color depth and data format information of the source end, and analyzes the frame header, each line ending mark, effective data enabling and effective data;

s4, the image processing unit completes a column correction function of the analyzed image data;

s5, the corrected data of the image data column is cached through FIFO_W, written into DDR, and column pixels of the source end data are corrected;

s6, after writing two frames of images into the DDR, starting to read out the image data from the DDR, and writing the image data into the FIFO_R;

s7, when the data quantity in the FIFO_R is larger than M, starting to read out data from the FIFO_R;

s8, the HDMI output MAC unit mainly completes configuration of an HDMI transmitting end MAC, sets resolution, frame frequency, color depth and data format information of output image data according to the EDID of a reading host end, receives the data of the FIFO_R and outputs row, field and effective data according to time sequence;

s9, the HDMI output interface PHY completes basic configuration of an HDMI interface PHY end, and parallel data are converted into high-speed TMDS serial data and a clock;

the method also comprises the step of optimizing the time sequence of the standard image data, wherein the steps are as follows:

s10, detecting frame heads, resetting all counts, starting to count the effective data in rows, and resetting the row counts when end marks of each row are effective;

s20, when the tail end mark of each row is valid, adding one to column calculation, and clearing when the frame head arrives;

s30, comparing whether the value of the column count and the number of the identified pixel columns are equal when the end-of-line flag is valid,

if the total number of the pixel columns at the source end is smaller than the total number of the identified pixel columns, the column numbers of the pixels are supplemented;

and if the total number of the pixel columns at the source end is larger than the value of the identified pixel columns, deleting the redundant pixel columns, and outputting the redundant pixel columns as standard pixel points.

2. The method for implementing multi-channel HDMI transmission and automatic correction according to claim 1, wherein: the image processing unit performs an image column correction function on input image data, and corrects a phenomenon that a missing or redundant pixel appears in the source-side image column.

3. The method for implementing multi-channel HDMI transmission and automatic correction according to claim 2, wherein said source image column pixels are corrected, comprising the steps of:

s100, when each frame head of the image data is valid, starting to write the image valid data corrected by the S4 column into the FIFO_W;

s200, when the data quantity in the FIFO_W is larger than M, starting to write the image data into the DDR until all effective data of one frame are written into the DDR, wherein the space address occupied by each frame of data is N;

s300, when the next frame header is valid, performing frame counting on the written frame image data, clearing when the frame counting is three, starting to repeat the S100 and the S200, and continuously caching source end valid data to the DDR;

when the frame header of each frame is valid, the image data is written from the address space 0, N,2N,3N of the DDR.