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CN114141767A - Integrated structure of IGZO transistor and GaN HEMT gate control circuit and preparation method thereof - Google Patents

Integrated structure of IGZO transistor and GaN HEMT gate control circuit and preparation method thereof Download PDF

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CN114141767A
CN114141767A CN202111419995.1A CN202111419995A CN114141767A CN 114141767 A CN114141767 A CN 114141767A CN 202111419995 A CN202111419995 A CN 202111419995A CN 114141767 A CN114141767 A CN 114141767A
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layer
gan hemt
igzo
source
etching
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李彦佐
陈兴
王东
吴勇
黄永
陈瑶
林长志
邱慧嫣
谢雨峰
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Wuhu Research Institute of Xidian University
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Wuhu Research Institute of Xidian University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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Abstract

The invention discloses an integrated structure of an IGZO transistor and a GaN HEMT gate control circuit and a preparation method thereof, relating to the technical field of semiconductors, wherein the integrated structure is divided into two parts, one part is a GaN HEMT structure, the other part is an IGZO transistor, and the two parts are grown on a substrate (101). The diamond material has good heat-conducting property, and can be introduced as a substrate to better enhance the heat-dissipating capability of devices and circuits.

Description

Integrated structure of IGZO transistor and GaN HEMT gate control circuit and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to an integrated structure of an IGZO transistor and a GaN HEMT gate control circuit and a preparation method of the integrated structure.
Background
Wide Band Gap Semiconductor (WBGS) similar to gallium nitride (GaN), diamond, and silicon carbide (SiC) are also known as third generation Semiconductor materials. Among them, gallium nitride (GaN) has a wide band gap, a direct band gap, a high breakdown field strength, a low dielectric constant, a high saturated electron drift velocity, a good radiation resistance and a good chemical stability, and thus has become a hot spot for research and application. AlGaN/GaN HEMTs have many advantages, including high breakdown voltage, low on-resistance, and so on, and are considered by the industry as excellent power switching devices or power electronic devices. Under the application conditions of high temperature, high power, high frequency, irradiation and the like, the GaN device has a plurality of advantages. Therefore, gallium nitride materials and circuits thereof are key basic materials of high-precision technologies such as microelectronics, power electronics, photoelectrons and the like, and have certain influence on the fields of national defense industry, information technology industry and the like.
In the field of displays, IGZO technology has several advantages over α -Si amorphous silicon technology. First, the high mobility of the IGZO transistor, its migrationThe rate is about 10cm2about/Vs, the crystal is at least ten times or more of alpha-Si amorphous silicon, which is the basis of a high-frequency grid-control switching device. IGZO has good stability under illumination, and also has the advantages of good uniformity, high transparency and simple manufacturing process. In addition, it is very important that the IGZO transistor is turned off well, which is an important guarantee for reducing the power consumption of the control circuit. The leakage rate of IGZO is only one ten thousandth of it compared to Low Temperature Polysilicon (LTPS). If the control terminal of the control circuit is a mobile small-capacity direct-current power supply, the IGZO transistor as the control terminal circuit has a good advantage in terms of low power consumption.
The development and application of gan power devices have been hindered to some extent by the problem that silicon is not ideal for epitaxial substrate materials in gan power devices. In the prior art, polycrystalline diamond and a gallium nitride-based power device can be bonded, so that the heat dissipation performance of the whole device is improved. In controlling high power GaN HEMT devices with low voltage signals, Si-based CMOS circuits are typically used. Si-based integrated circuits have a very good performance in the years of semiconductor development, taking all aspects into consideration, and thus have been widely used in the field of integrated circuits, and have also made a large share in the market. However, Si-based integrated circuits also have their limitations and do not perform well enough in some respects for compound semiconductors. In the prior art, few double-channel IGZO transistors are used in low-voltage control circuits. IGZO transistors are used in display applications, but they have the advantages of good turn-off effect and low driving power, which makes them suitable for driving switches used in low-power circuits to drive high-power circuits. Therefore, how to combine the two circuit structures and apply the combined circuit structures to control the high-power GaN HEMT is a problem to be solved at present.
Disclosure of Invention
The invention aims to provide an integrated structure of an IGZO transistor and a GaN HEMT gate control circuit and a preparation method thereof, so as to solve the defects caused in the prior art.
An integrated structure of an IGZO transistor and a GaN HEMT gate control circuit is specifically divided into two parts, wherein one part is a GaN HEMT structure, the other part is an IGZO transistor, and the two parts are grown on a substrate (101);
the GaN HEMT structure is sequentially provided with a substrate, an AlGaN buffer layer, a GaN layer, an AlN layer and Al from bottom to top0.2Ga0.8N layer, AlGaN layer, first SiN layer, source drain electrode, and Al2O3A dielectric layer and a GaN HEMT grid end;
the IGZO transistor is sequentially provided with a substrate and SiO from bottom to top2Layer, ITO layer (as source terminal, drain terminal, gate terminal), Al2O3Buffer layer, IGZO base layer, IGZO Boost layer, HfO2A dielectric layer and an IGZO transistor gate terminal;
after the two parts are manufactured, a second SiN layer 118, an extraction electrode connected with the source/drain electrode, an external metal wire 120 connected with the source/drain extraction electrode of the GaN HEMT, a first extraction metal wire connected with the gate end of the GaN HEMT, a second extraction metal wire connected with the ITO layer, a third metal extraction wire, a first metal lead wire and a second metal lead wire which are respectively connected with the gate end extraction metal wire of the GaN HEMT and the source/drain extraction metal wire of the IGZO transistor are further arranged on the two parts.
Furthermore, the substrate is made of a diamond material of an epitaxial GaN film, and the size range of the diamond material is 2-8 inch.
Further, an SiN layer grows on the substrate, etching is carried out on the region corresponding to the position of the GaN HEMT device to form a concave hole, and the GaN HEMT device is manufactured in the region.
Further, the AlGaN buffer layer is grown by a metal organic source chemical vapor deposition method.
Further, the Al0.2Ga0.8The thickness of the N layer is 6nm, and the thickness of the AlGaN layer is 20 nm.
The device can be prepared by the following method:
(1) growing a thicker SiN layer on the substrate, and etching the position area of the corresponding GaN HEMT device to form a concave hole;
(2) on the basis of the structure, an AlGaN buffer layer is grown by adopting a metal organic source chemical vapor deposition method;
(3) forming a GaN buffer layer by adopting a metal organic source chemical vapor deposition method or other methods on the basis of the structure through unintended doping growth, wherein the thickness of the GaN buffer layer is 100nm-10 um;
(4) forming an AlN layer by adopting a metal organic source chemical vapor deposition method through unintended doping growth on the basis of the structure;
(5) al is formed by adopting a metal organic source chemical vapor deposition method and unintentionally doping growth on the basis of the structure0.2Ga0.8N layers;
(6) forming an AlGaN layer by adopting a metal organic source chemical vapor deposition method on the basis of the structure through unintentional doping growth;
(7) etching the AlGaN layer to leave a concave hole, and growing the AlGaN layer in the concave hole by PECVD (plasma enhanced chemical vapor deposition) to reserve the positions of a gate dielectric and a gate electrode;
(8) a first SiN layer 107 is grown on the basis of the structure by adopting a PECVD method, and the thickness is 100 nm;
(9) adopting magnetron sputtering to manufacture ohmic contact electrodes as the source end and the drain end, etching the first SiN layer on the basis of the positions of the concave holes of the original AlGaN layer, leaving a plurality of concave holes with larger size than the original concave holes, and growing SiO in the larger concave holes by adopting a PECVD method2To preserve the positions of the gate dielectric and the gate electrode;
(10) etching of SiO2Growing gate Al by ALD2O3A dielectric layer, and manufacturing a GaN HEMT grid end on the basis;
(11) growing a second SiN layer with the thickness of 300nm on the basis of the structure by adopting a PECVD method;
(12) mixing Al2O3Etching the dielectric layer, the first SiN layer and the second SiN layer to form a through hole, depositing Ti/Al/Ni/Au and other metals, leading out the source electrode and the drain electrode, leaving Pad points above the SiN layer, etching the SiN layer in the corresponding areas of the gate electrode, the source electrode and the drain electrode, depositing Ti/Al/Ni/Au and other metals, and leading out the gate endThe electrode metal and the source and drain electrode metal are upwards, and a second SiN layer is grown by using a PECVD method;
(13) etching the position corresponding to the IGZO transistor, etching a concave hole on the second SiN layer which grows originally, and manufacturing the IGZO transistor in the concave hole area;
(14) and etching the channel region to form a concave hole, wherein the left position is used for an IGZO base layer: in0.52Ga0.29Zn0.19O and IGZO Boost layer: in0.82Ga0.08Zn0.10Manufacturing O; and growing SiO in the surrounding area2The shielding layer is used for ensuring that the IGZO basic layer and the IGZO Boost layer are manufactured in the area near the channel;
(15) removing peripheral redundant SiO2A masking layer followed by growing the Al2O3A buffer layer, grown by ALD, for the purpose of improving the interface problem;
(16) on the basis of the structure, the HfO is grown by ALD2A dielectric layer with a thickness of 50 nm;
(17) etching the corresponding channel region to a certain degree, leaving a pit, wherein the gate end of the IGZO transistor is an ITO medium, growing by adopting ALD, and manufacturing a T-shaped gate at the position due to the reserved pit;
(18) for HfO2Dielectric layer and Al2O3Etching the buffer layer to form a through hole, manufacturing Ti/Al/Ni/Au multilayer metal, manufacturing a second lead-out metal wire, ensuring that second SiN layers of the two devices are close to the same height, manufacturing a metal wire with the width capable of meeting the maximum current drive, and connecting the source end of the IGZO transistor with the drain end of the GaN HEMT;
(19) on the basis, the second SiN layer continues to grow and serves as a passivation layer and an isolation layer of the protection device;
(20) etching the source and drain ends of the GaN HEMT and the area corresponding to the drain end of the IGZO transistor to form a concave hole, manufacturing a metal electrode in the concave hole, and manufacturing an external metal wire connected with the source and drain of the GaN HEMT and a second metal wire led out from the drain end of the IGZO transistor. It is worth mentioning that the external metal line and the second metal wire of the source-drain connection of the GaN HEMT do not overlap in three-dimensional space.
Further, the SiO2The layer is grown by thermal oxidation.
Further, the ITO layer is grown by ALD and is about 10nm thick to serve as a gate terminal and a drain terminal of the IGZO transistor.
Further, the actual component distribution ratio of the IGZO base layer is In0.52Ga0.29Zn0.19And O, growing by ALD with the thickness of 10 nm.
Further, In the IGZO Boost layer 115, the actual composition ratio is In0.82Ga0.08Zn0.10O, grown with ALD thickness of 3 nm.
The invention has the advantages that:
(1) the invention provides an integrated grid control circuit structure based on growth of a GaN HEMT, an IGZO transistor and a diamond substrate, wherein the IGZO transistor is used for controlling a high-power GaN HEMT and is integrated on the substrate, and the GaN HEMT device is a high-power device, so that the problem of how to radiate heat to ensure normal work is a hot point of research. The diamond material has good heat-conducting property, and can be introduced as a substrate to better enhance the heat-dissipating capability of devices and circuits.
(2) The IGZO transistor is widely applied to the field of mobile end display screens and is a representative device of a low-power consumption circuit. The device introduced as the control circuit can well reduce the power consumption of the control circuit. In the field of display screen application, the excellent turn-off performance of the IGZO transistor is proved, and the good turn-off effect can be ensured when the IGZO transistor is applied to a control circuit.
(3) The mobility of the IGZO transistor is at least ten times that of alpha-Si amorphous silicon, and the IGZO transistor can be used as a control circuit device to ensure the working frequency of a circuit to a certain extent.
(4) When the power supply of the control circuit is from a low-capacity direct-current battery, the IGZO transistor is used as a control circuit device under the condition, so that the control power consumption can be greatly saved, and a scheme is provided for controlling a high-power device by a mobile small power supply.
Drawings
FIG. 1 is a schematic structural diagram of the present invention.
Wherein: 101 substrate, 102AlGaN buffer layer, 103GaN layer, 104AlN layer, 105Al0.2Ga0.8N layer, 106AlGaN layer, 107 first SiN layer, 108 source terminal, drain terminal electrode, 109Al2O3Dielectric layer, 110GaN HEMT gate terminal, 111SiO2Layer 112ITO layer 113Al2O3Buffer layer, 114IGZO base layer, 115IGZO Boost layer, 116HfO2A dielectric layer, a 117IGZO transistor gate terminal, a 118 second SiN layer, a 119 leading-out electrode, a 120 external metal wire, a 121 first leading-out metal wire, a 122 second leading-out metal wire, a 123 third metal leading-out wire, a 124 first metal lead wire, a 125 second metal lead wire
Detailed Description
In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further described with the specific embodiments.
Example 1
(1) Growing a thicker SiN layer 118 on the substrate 101, and etching the position area of the corresponding GaN HEMT device to form a concave hole;
(2) on the basis of the structure, an AlGaN buffer layer 102 is grown by adopting a metal organic source chemical vapor deposition method;
(3) forming a GaN buffer layer 103 by adopting a metal organic source chemical vapor deposition method or other methods on the basis of the structure in an unintentional doping growth mode, wherein the thickness of the GaN buffer layer is 1 um;
(4) forming an AlN layer 104 by adopting a metal organic source chemical vapor deposition method through unintended doping growth on the basis of the structure;
(5) al is formed by adopting a metal organic source chemical vapor deposition method and unintentionally doping growth on the basis of the structure0.2Ga0.8 An N layer 105;
(6) forming an AlGaN layer 106 by adopting a metal organic source chemical vapor deposition method on the basis of the structure through unintentional doping growth;
(7) etching is performed on the AlGaN layer 106Leaving a recess and growing SiO in the recess by PECVD2To preserve the positions of the gate dielectric and the gate electrode;
(8) a first SiN layer 107 is grown on the basis of the structure by adopting a PECVD method, and the thickness is 100 nm;
(9) adopting magnetron sputtering to manufacture ohmic contact electrodes as the source end and the drain end, etching the first SiN layer 107 on the basis of the position of the concave hole of the original AlGaN layer 106, leaving a plurality of concave holes with larger size than the original concave hole, and growing SiO in the larger concave holes by adopting a PECVD method2To preserve the positions of the gate dielectric and the gate electrode;
(10) etching of SiO2Growing gate Al by ALD2O3A dielectric layer 109, on the basis of which a GaN HEMT gate terminal 110 is manufactured;
(11) a second SiN layer 118 is grown on the basis of the structure by a PECVD method, and the thickness of the second SiN layer is 300 nm;
(12) mixing Al2O3Etching the dielectric layer 109, the first SiN layer 107 and the second SiN layer 118 to form a through hole, depositing Ti/Al/Ni/Au and other metals, leading out a source electrode and a drain electrode, leaving Pad points above the SiN layer 111, etching the SiN layer 111 in the corresponding areas of the gate electrode 110 and the source electrode 108 and the drain electrode 108, depositing Ti/Al/Ni/Au and other metals, leading out a gate electrode metal 121 and source and drain electrode metals 119, and then upwards growing the SiN layer 118 by using a PECVD method;
(13) etching the position corresponding to the IGZO transistor, etching a concave hole on the SiN layer 118 which originally grows, and manufacturing the IGZO transistor in the concave hole area;
(14) etching is then performed in the channel region to form a recess, leaving a location for the IGZO base layer 114: in0.52Ga0.29Zn0.19O and IGZO Boost layer 115: in0.82Ga0.08Zn0.10Manufacturing O; and growing SiO in the surrounding area2A masking layer to ensure that the IGZO base layer 114 and the IGZO Boost layer 115 are fabricated in the region near the channel;
(15) removing peripheral redundant SiO2A masking layer followed by growing the Al2O3 A buffer layer 113 grown by ALD for the purpose of improving the interface problem;
(16) on the basis of the structure, the HfO is grown by ALD2A dielectric layer 116 having a thickness of 50 nm;
(17) etching the corresponding channel region to a certain degree to leave a pit, wherein the gate end 117 of the IGZO transistor is an ITO medium, and growing by adopting ALD (atomic layer deposition) and the reserved pit is made into a T-shaped gate;
(18) for HfO2Dielectric layer 116 and Al2O3Etching the buffer layer 113 to form a through hole, manufacturing Ti/Al/Ni/Au multilayer metal, manufacturing a second lead-out metal wire 122, ensuring that the second SiN layers 118 of the two devices are close to the same height, manufacturing a metal wire 124 with the width capable of meeting the maximum current drive, and connecting the source end of the IGZO transistor with the drain end of the GaN HEMT;
(19) on the basis, the second SiN layer 118 continues to grow to serve as a passivation layer and an isolation layer of the protection device;
(20) etching is carried out on two ends of a source drain of the GaN HEMT and a region corresponding to a drain end of the IGZO transistor to form a concave hole, a metal electrode is manufactured in the concave hole, and an external metal wire 120 connected with the source drain of the GaN HEMT and a second metal wire 125 led out from the drain end of the IGZO transistor are manufactured. It is worth mentioning that the GaN HEMT source-drain connected outer metal line 120 and the connected metal wire 124 do not overlap in three-dimensional space.
Example 2
The rest is the same as example 1, except that: the thickness of the GaN buffer layer 103 in step (3) is 100 nm.
Example 3
The rest is the same as example 1, except that: the thickness of the GaN buffer layer 103 in step (3) is 10 um.
It will be appreciated by those skilled in the art that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The embodiments disclosed above are therefore to be considered in all respects as illustrative and not restrictive. All changes which come within the scope of or equivalence to the invention are intended to be embraced therein.

Claims (4)

1. An integrated structure of an IGZO transistor and a GaN HEMT gate control circuit is characterized in that the integrated structure is divided into two parts, wherein one part is a GaN HEMT structure, the other part is an IGZO transistor, and the two parts are grown on a substrate (101);
the GaN HEMT structure is provided with a substrate (101), an AlGaN buffer layer (102), a GaN layer (103), an AlN layer (104) and Al in sequence from bottom to top0.2Ga0.8An N layer (105), an AlGaN layer (106), a first SiN layer (107), a source/drain electrode (108), and Al2O3A dielectric layer (109) and a GaN HEMT gate end (110);
the IGZO transistor is sequentially provided with a substrate (101) and SiO from bottom to top2Layer (111), ITO layer (112) (as source, drain, gate), Al2O3A buffer layer (113), an IGZO base layer (114), an IGZO Boost layer (115), HfO2A dielectric layer (116), an IGZO transistor gate terminal (117);
after the two parts are manufactured, a second SiN layer (118), an extraction electrode (119) connected with the source/drain electrode (107), an external metal wire (120) connected with the source/drain extraction electrode (119) of the GaN HEMT, a first extraction metal wire (121) connected with a grid end (110) of the GaN HEMT, a second extraction metal wire (122) connected with the ITO layer (112), a third metal extraction wire (123), a first metal lead wire (124) and a second metal lead wire (125) which are respectively connected with the grid end extraction metal wire (121) of the GaN HEMT, and the source/drain extraction metal wire (122) of the IGZO transistor are further arranged on the two parts.
2. An integrated structure of an IGZO transistor and a GaN HEMT gate control circuit according to claim 1, characterized in that the substrate (101) is made of a diamond material of an epitaxial GaN film and has a size in the range of 2-8 inch.
3. The integrated structure of an IGZO transistor and a GaN HEMT gate control circuit as claimed in claim 1, wherein a layer of SiN is grown on the substrate (101), and then etched in the region corresponding to the GaN HEMT device to form a recess, in which the GaN HEMT device is fabricated.
4. The method for manufacturing an integrated structure of an IGZO transistor and a GaN HEMT gate control circuit according to claim 1, which comprises the following steps:
(1) growing a thicker SiN layer (118) on a substrate (101), and etching the position region of a corresponding GaN HEMT device to form a concave hole;
(2) on the basis of the structure, an AlGaN buffer layer (102) is grown by adopting a metal organic source chemical vapor deposition method;
(3) adopting a metal organic source chemical vapor deposition method or other methods to grow and form a GaN buffer layer (103) in an unintentional doping way on the basis of the structure, wherein the thickness of the GaN buffer layer is 100nm-10 um;
(4) adopting a metal organic source chemical vapor deposition method to grow and form an AlN layer (104) by unintentional doping on the basis of the structure;
(5) al is formed by adopting a metal organic source chemical vapor deposition method and unintentionally doping growth on the basis of the structure0.2Ga0.8An N layer (105);
(6) forming an AlGaN layer (106) by adopting a metal organic source chemical vapor deposition method on the basis of the structure through unintentional doping growth;
(7) etching is performed on the AlGaN layer (106) to leave recesses, and SiO is grown in the recesses by PECVD2To preserve the positions of the gate dielectric and the gate electrode;
(8) growing a first SiN layer (107) on the basis of the structure by adopting a PECVD method, wherein the thickness of the first SiN layer is 100 nm;
(9) the method comprises the steps of manufacturing ohmic contact electrodes serving as a source end electrode and a drain end electrode by magnetron sputtering, etching a first SiN layer (107) on the basis of the positions of concave holes of an original AlGaN layer (106), leaving a plurality of concave holes with sizes larger than those of the original concave holes, and growing SiO in the larger concave holes by a PECVD method2To preserve the positions of the gate dielectric and the gate electrode;
(10) etching of SiO2By ALD ofLong-grid Al2O3A dielectric layer (109) on which a GaN HEMT gate terminal (110) is manufactured;
(11) growing a second SiN layer (118) on the basis of the structure by adopting a PECVD method, wherein the thickness of the second SiN layer is 300 nm;
(12) mixing Al2O3Etching the dielectric layer (109), the first SiN layer (107) and the second SiN layer (118) to form a through hole, depositing metals such as Ti/Al/Ni/Au, leading out a source electrode and a drain electrode, leaving a Pad point above the first SiN layer (107), etching the first SiN layer (107) in a region corresponding to the gate electrode (110) and the source electrode and the drain electrode (108), depositing metals such as Ti/Al/Ni/Au, leading out a gate end electrode metal (121) and source and drain end electrode metals (119), and growing the second SiN layer (118) upwards by using a PECVD method;
(13) etching the position corresponding to the IGZO transistor, etching a concave hole on the second SiN layer (118) which is originally grown, and manufacturing the IGZO transistor in the concave hole area;
(14) and etching the channel region to form a concave hole, wherein the position left for the IGZO base layer (114): in0.52Ga0.29Zn0.19O and IGZO Boost layer (115): in0.82Ga0.08Zn0.10Manufacturing O; and growing SiO in the surrounding area2A masking layer to ensure that the IGZO base layer (114) and the IGZO Boost layer (115) are fabricated in the vicinity of the channel;
(15) removing peripheral redundant SiO2A masking layer followed by growing the Al2O3A buffer layer (113);
(16) on the basis of the structure, the HfO is grown by ALD2A dielectric layer (116) having a thickness of 50 nm;
(17) etching the corresponding channel region to a certain degree, leaving a pit, wherein the gate end (117) of the IGZO transistor is an ITO medium, growing by adopting ALD, and manufacturing a T-shaped gate at the position due to the reserved pit;
(18) for HfO2Dielectric layer (116 and Al)2O3Etching the buffer layer (113) to form a through hole, manufacturing Ti/Al/Ni/Au multilayer metal, manufacturing a second lead-out metal wire (122) and ensuring the second lead-out metal wire of the two devicesThe two SiN layers (118) are arranged near the same height, a metal conducting wire (124) which can meet the width of maximum current driving is manufactured at the time, and the source end of the IGZO transistor is connected with the drain end of the GaN HEMT;
(19) on the basis, continuing to grow the second SiN layer (118) to serve as a passivation layer and an isolation layer of the protection device;
(20) etching is carried out on two ends of a source drain of the GaN HEMT and a region corresponding to a drain end of the IGZO transistor to form a concave hole, a metal electrode is manufactured in the concave hole, an external metal wire (120) connected with the source drain of the GaN HEMT and a second metal lead (125) led out from the drain end of the IGZO transistor are manufactured, and the external metal wire (120) connected with the source drain of the GaN HEMT and the first metal lead (124) are not overlapped in a three-dimensional space.
CN202111419995.1A 2021-11-26 2021-11-26 Integrated structure of IGZO transistor and GaN HEMT gate control circuit and preparation method thereof Pending CN114141767A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115663015A (en) * 2022-10-19 2023-01-31 上海新微半导体有限公司 Semiconductor device structure and preparation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115663015A (en) * 2022-10-19 2023-01-31 上海新微半导体有限公司 Semiconductor device structure and preparation method thereof
CN115663015B (en) * 2022-10-19 2023-12-15 上海新微半导体有限公司 Semiconductor device structure and preparation method thereof

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