CN114138581A - Mainboard test method and system - Google Patents
Mainboard test method and system Download PDFInfo
- Publication number
- CN114138581A CN114138581A CN202111459464.5A CN202111459464A CN114138581A CN 114138581 A CN114138581 A CN 114138581A CN 202111459464 A CN202111459464 A CN 202111459464A CN 114138581 A CN114138581 A CN 114138581A
- Authority
- CN
- China
- Prior art keywords
- test
- target
- function
- motherboard
- file
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010998 test method Methods 0.000 title description 5
- 238000012360 testing method Methods 0.000 claims abstract description 305
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000011990 functional testing Methods 0.000 claims abstract description 14
- 230000008569 process Effects 0.000 claims abstract description 9
- 238000013507 mapping Methods 0.000 claims description 36
- 230000006353 environmental stress Effects 0.000 claims description 19
- 238000005316 response function Methods 0.000 claims description 18
- 230000004044 response Effects 0.000 claims description 12
- 238000001514 detection method Methods 0.000 claims description 10
- 230000002159 abnormal effect Effects 0.000 claims description 9
- 239000011159 matrix material Substances 0.000 claims description 9
- 238000006073 displacement reaction Methods 0.000 claims description 6
- 230000007613 environmental effect Effects 0.000 claims description 5
- 230000009286 beneficial effect Effects 0.000 description 8
- 230000003044 adaptive effect Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 230000005284 excitation Effects 0.000 description 4
- 238000011156 evaluation Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000010230 functional analysis Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Prevention of errors by analysis, debugging or testing of software
- G06F11/3698—Environments for analysis, debugging or testing of software
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
本发明公开了一种主板测试方法及系统，其方法包括：接收预设服务器对于目标主板的功能测试指令；根据所述功能测试指令从预设数据库中调取其对应的目标引导文件；通过所述目标引导文件构建功能测试指令对应目标功能的测试环境；利用所述测试环境对目标主板的目标功能进行测试，获取测试结果，根据所述测试结果确定目标主板的故障情况。过利用目标引导文件构建虚拟的测试环境可以无需借助外力设备，简化了测试流程的同时也提高了测试的精度和效率，同时也保证了测试环境的稳定性，进一步地提高了测试效率。
The invention discloses a mainboard testing method and system. The method includes: receiving a function test instruction of a preset server for a target motherboard; retrieving a corresponding target boot file from a preset database according to the functional test instruction; The target guide file constructs a test environment corresponding to the target function of the function test instruction; the target function of the target motherboard is tested by using the test environment, the test result is obtained, and the fault condition of the target motherboard is determined according to the test result. By using the target boot file to build a virtual test environment, no external equipment is needed, which simplifies the test process and improves the accuracy and efficiency of the test, and also ensures the stability of the test environment and further improves the test efficiency.
Description
Technical Field
The invention relates to the technical field of electronic element testing, in particular to a mainboard testing method and system.
Background
When various electronic devices such as computers, televisions, POS machines and handheld communication devices (mobile phones, interphones and the like) are produced, key components on products need to be tested, such as signal testing, performance testing and the like, and components with unqualified quality are screened out through testing, so that the quality of the products is ensured. In all tests, the number of the test of the mainboard is large, the test points are many, and the test is basically performed by adopting a manual test method in the past. Because manual testing is time-consuming and labor-consuming, the efficiency is low, the cost is high, missing detection or error detection is caused, the product quality is influenced, and when the complicated and fine mainboard is involved, the mainboard is easy to damage.
At present, when a mainboard is tested, a test environment of the mainboard needs to be built, an external test device is usually developed, and the external test device is used as a bridge between the mainboard and a computer display. The test equipment is provided with a programmable logic device, the programmable logic device is manually controlled to output excitation signals of all test cases to the mainboard, the mainboard generates corresponding response signals after receiving the excitation signals, the programmable logic device analyzes whether the response signals generated by the mainboard are consistent with preset response signals or not, and the test results are output to a computer display for display. However, the above method has the following problems: the test environment and the test process are complex due to the need of additional test equipment, the test efficiency of the mainboard is affected, and the test efficiency of the mainboard is low.
Disclosure of Invention
In view of the above-mentioned problems, the present invention provides a motherboard testing method and system to solve the problem of low motherboard testing efficiency due to complicated testing environment and testing process, which are caused by the need of additional testing equipment in the testing environment mentioned in the background art.
A mainboard test method comprises the following steps:
receiving a function test instruction of a preset server for a target mainboard;
calling a corresponding target guide file from a preset database according to the function test instruction;
constructing a test environment of a function test instruction corresponding to a target function through the target guide file;
and testing the target function of the target mainboard by using the test environment, acquiring a test result, and determining the fault condition of the target mainboard according to the test result.
Preferably, before receiving a function test instruction of a preset server for a target motherboard, the method further includes:
acquiring a configuration file written in advance by a target mainboard;
testing each configuration file to obtain a test result, and determining the operation behavior data of each configuration file according to the test result;
performing function classification on the configuration files according to the operation behavior data of each configuration file to obtain a classification result;
and constructing a functional analysis model of the target mainboard according to the classification result and the configuration file.
Preferably, the receiving a function test instruction of the preset server for the target motherboard includes:
receiving a current test instruction sent by the preset server, and judging whether the first test instruction is reasonable or not, if so, not needing subsequent operation, and otherwise, sending an unreasonable prompt of the current test instruction;
analyzing the current test instruction to obtain a corresponding test vector;
inputting the test vector into the function analysis model to determine a test function corresponding to the current test instruction;
and combining the test function with the current test instruction to generate the function test instruction.
Preferably, the calling of the target guidance file corresponding to the functional test instruction from the preset database according to the functional test instruction includes:
determining a configuration file to be detected of the target mainboard according to the function test instruction;
acquiring a test script file corresponding to the configuration file to be detected, and carrying out integrity detection on the test script file;
when the test script file passes the integrity detection, calling a plurality of first guide files corresponding to the test script file from the preset database;
and selecting an adaptive second boot file from the plurality of first boot files as the target boot file according to the working parameters of the target mainboard.
Preferably, the constructing a test environment of the functional test instruction corresponding to the target function through the target boot file includes:
acquiring the hardware specification and the operating parameter of the target mainboard;
determining environmental parameters of a required test environment according to the hardware specification and the operating parameters;
matching in a big database to obtain a plurality of first test environments based on the environment parameters;
determining a first topological mapping frame according to the file content of the target guide file, and calculating the fitting degree of the first topological mapping frame and a second topological mapping frame of each first test environment;
and taking the second test environment with the maximum fitting degree as a sample frame, acquiring a script factor corresponding to the target guide file, and constructing a test environment of a target function corresponding to the functional test instruction by using the script factor based on the sample frame.
Preferably, the testing the target function of the target motherboard by using the test environment to obtain the test result, and determining the fault condition of the target motherboard according to the test result includes:
setting multilayer environmental stress according to the test environment;
determining test parameters under each layer of environmental stress, and testing the target function of the target mainboard under the layer of environmental stress by using the test parameters to obtain a plurality of test results;
and comprehensively evaluating whether the target function of the target mainboard is abnormal according to the plurality of test results, if so, determining the fault type of the target mainboard according to the environment test result, and otherwise, confirming that the target function of the target mainboard is normal.
Preferably, the comprehensively evaluating whether the target function of the target motherboard is abnormal according to the plurality of test results includes:
determining a serial number of the target mainboard, and determining standard working parameters of the target mainboard according to the serial number;
determining an expected result of the target function under each layer of environmental stress according to the standard working parameters;
comparing the expected result under each layer of environmental stress with the test result under the layer of environmental stress, if the comparison result is that the expected result and the test result are consistent, determining that the target function of the target mainboard is normal, and if the expected result and the test result are inconsistent, calculating the difference degree of the target mainboard and the test result;
and judging whether the difference degree is within a preset range, if so, confirming that the target function of the target mainboard is normal, and otherwise, confirming that the target function of the target mainboard is abnormal.
Preferably, the calculating the fitting degree of the first topological mapping frame and the second topological mapping frame of each first test environment comprises:
acquiring a generation sequence of the first topological mapping frame;
solving the parameter vector of the generated sequence, and constructing a frame response function expression according to the parameter vector;
acquiring an impulse response function matrix of each structure in a first topological mapping frame;
testing the change condition of matrix factors in the impulse response function matrix of each structure of the first topological mapping framework in the working process;
establishing a motion equation of each structure according to the change condition;
determining an environment variable offset value of a test environment to be constructed according to the motion equation of each structure;
determining a frame response function analytic expression according to the environment variable offset value and the frame response function expression;
modeling the frame response function analytic expression to obtain a frame model;
testing the frame model by using preset data to obtain a displacement response sequence of a first topological mapping frame;
determining a first dynamic sequence of a first topological mapping frame according to the displacement response sequence;
obtaining a second dynamic sequence of a second topological mapping frame for each first test environment,
calculating a fitness of the first dynamic sequence to each second dynamic sequence;
and taking a second test environment corresponding to a target second dynamic sequence with the highest fitting degree with the first dynamic sequence in the plurality of second dynamic sequences as a sample frame.
A motherboard testing system, the system comprising:
the receiving module is used for receiving a function test instruction of a preset server for a target mainboard;
the calling module is used for calling a corresponding target guide file from a preset database according to the function test instruction;
the building module is used for building a test environment of a function test instruction corresponding to a target function through the target guide file;
and the test module is used for testing the target function of the target mainboard by using the test environment, acquiring a test result and determining the fault condition of the target mainboard according to the test result.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and drawings.
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention.
FIG. 1 is a flowchart illustrating a method for testing a motherboard according to the present invention;
FIG. 2 is another flowchart of a motherboard testing method according to the present invention;
FIG. 3 is a flowchart illustrating a method for testing a motherboard according to another embodiment of the present invention;
fig. 4 is a schematic structural diagram of a motherboard testing system provided in the present invention.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.
When various electronic devices such as computers, televisions, POS machines and handheld communication devices (mobile phones, interphones and the like) are produced, key components on products need to be tested, such as signal testing, performance testing and the like, and components with unqualified quality are screened out through testing, so that the quality of the products is ensured. In all tests, the number of the test of the mainboard is large, the test points are many, and the test is basically performed by adopting a manual test method in the past. Because manual testing is time-consuming and labor-consuming, the efficiency is low, the cost is high, missing detection or error detection is caused, the product quality is influenced, and when the complicated and fine mainboard is involved, the mainboard is easy to damage.
At present, when a mainboard is tested, a test environment of the mainboard needs to be built, an external test device is usually developed, and the external test device is used as a bridge between the mainboard and a computer display. The test equipment is provided with a programmable logic device, the programmable logic device is manually controlled to output excitation signals of all test cases to the mainboard, the mainboard generates corresponding response signals after receiving the excitation signals, the programmable logic device analyzes whether the response signals generated by the mainboard are consistent with preset response signals or not, and the test results are output to a computer display for display. However, the above method has the following problems: in order to solve the above problem, the present embodiment discloses a motherboard testing method, in which an additional testing device is required in a testing environment, so that the testing environment and the testing process are complex, the testing efficiency of the motherboard is affected, and the testing efficiency of the motherboard is low.
A motherboard testing method, as shown in fig. 1, includes the following steps:
step S101, receiving a function test instruction of a preset server to a target mainboard;
step S102, calling a corresponding target guide file from a preset database according to the function test instruction;
step S103, constructing a test environment of a target function corresponding to the function test instruction through the target guide file;
and step S104, testing the target function of the target mainboard by using the test environment, obtaining a test result, and determining the fault condition of the target mainboard according to the test result.
The working principle of the technical scheme is as follows: receiving a function test instruction of a preset server for a target mainboard, calling a corresponding target boot file from a preset database according to the function test instruction, constructing a test environment of the target function corresponding to the function test instruction through the target boot file, testing the target function of the target mainboard by using the test environment, obtaining a test result, and determining the fault condition of the target mainboard according to the test result.
The beneficial effects of the above technical scheme are: the virtual testing environment is constructed by utilizing the target guide file, so that external force equipment is not needed, the testing precision and efficiency are improved while the testing process is simplified, the stability of the testing environment is ensured, the testing efficiency is further improved, and the problems that the testing environment and the testing process are complex, the testing efficiency of a mainboard is influenced and the testing efficiency of the mainboard is lower due to the fact that additional testing equipment is needed in the testing environment in the prior art are solved.
In an embodiment, as shown in fig. 2, before receiving a function test instruction of a preset server for a target motherboard, the method further includes:
step S201, obtaining a configuration file written in advance by a target mainboard;
step S202, testing each configuration file to obtain a test result, and determining the operation behavior data of each configuration file according to the test result;
step S203, performing function classification on the configuration files according to the operation behavior data of each configuration file to obtain a classification result;
and S204, constructing a functional analysis model of the target mainboard according to the classification result and the configuration file.
The beneficial effects of the above technical scheme are: the function analysis model is built according to the configuration file of the target mainboard, so that the realized function of the target mainboard can be quickly determined according to the operation parameters of the target mainboard, manual testing is not needed, the working efficiency is improved, and a foundation is laid for determining a subsequent function testing instruction.
In an embodiment, as shown in fig. 3, receiving a function test instruction of a preset server for a target motherboard includes:
step S301, receiving a current test instruction sent by the preset server, and judging whether the first test instruction is reasonable or not, if so, not needing to perform subsequent operation, otherwise, sending an unreasonable prompt of the current test instruction;
step S302, analyzing the current test instruction to obtain a corresponding test vector;
step S303, inputting the test vector into the function analysis model to determine a test function corresponding to the current test instruction;
and step S304, combining the test function with the current test instruction to generate the function test instruction.
The beneficial effects of the above technical scheme are: the test function can be accurately determined by rapidly determining the test function corresponding to the test instruction by obtaining the test vector corresponding to the current test instruction according to the current test instruction and utilizing the function analysis model, so that the condition of function misrecognition is avoided, and the function judgment precision is improved.
In one embodiment, the retrieving the corresponding target boot file from the preset database according to the functional test instruction includes:
determining a configuration file to be detected of the target mainboard according to the function test instruction;
acquiring a test script file corresponding to the configuration file to be detected, and carrying out integrity detection on the test script file;
when the test script file passes the integrity detection, calling a plurality of first guide files corresponding to the test script file from the preset database;
and selecting an adaptive second boot file from the plurality of first boot files as the target boot file according to the working parameters of the target mainboard.
The beneficial effects of the above technical scheme are: the stability and the complete test of the target function of the target mainboard can be effectively guaranteed by detecting the integrity of the test script file, the test efficiency is improved, meanwhile, the test stability is also improved, further, the best guide file can be obtained according to the real-time working parameters of the target mainboard by selecting the adaptive second guide file, and the accuracy of the test result is further guaranteed.
In one embodiment, building a test environment of a functional test instruction corresponding to a target function through the target boot file includes:
acquiring the hardware specification and the operating parameter of the target mainboard;
determining environmental parameters of a required test environment according to the hardware specification and the operating parameters;
matching in a big database to obtain a plurality of first test environments based on the environment parameters;
determining a first topological mapping frame according to the file content of the target guide file, and calculating the fitting degree of the first topological mapping frame and a second topological mapping frame of each first test environment;
and taking the second test environment with the maximum fitting degree as a sample frame, acquiring a script factor corresponding to the target guide file, and constructing a test environment of a target function corresponding to the functional test instruction by using the script factor based on the sample frame.
The beneficial effects of the above technical scheme are: through obtaining the sample frame that test environment corresponds and utilizing and can need not newly-built sample frame again, further improved work efficiency, further, establish test environment through utilizing script factor and can both guarantee test environment's stability and also can make test environment accord with the needs of target mainboard more simultaneously, improved the practicality.
In an embodiment, the testing the target function of the target motherboard by using the test environment to obtain a test result, and determining a fault condition of the target motherboard according to the test result includes:
setting multilayer environmental stress according to the test environment;
determining test parameters under each layer of environmental stress, and testing the target function of the target mainboard under the layer of environmental stress by using the test parameters to obtain a plurality of test results;
and comprehensively evaluating whether the target function of the target mainboard is abnormal according to the plurality of test results, if so, determining the fault type of the target mainboard according to the environment test result, and otherwise, confirming that the target function of the target mainboard is normal.
The beneficial effects of the above technical scheme are: the target function of the target mainboard can be tested by setting multiple layers of environmental stress, so that the service condition of the target function of the target mainboard under the action of external force of multiple layers can be obtained, whether the target function of the target mainboard is normal or not can be comprehensively evaluated, and the accuracy of an evaluation result is improved.
In an embodiment, the comprehensively evaluating whether the target function of the target motherboard is abnormal according to the plurality of test results includes:
determining a serial number of the target mainboard, and determining standard working parameters of the target mainboard according to the serial number;
determining an expected result of the target function under each layer of environmental stress according to the standard working parameters;
comparing the expected result under each layer of environmental stress with the test result under the layer of environmental stress, if the comparison result is that the expected result and the test result are consistent, determining that the target function of the target mainboard is normal, and if the expected result and the test result are inconsistent, calculating the difference degree of the target mainboard and the test result;
and judging whether the difference degree is within a preset range, if so, confirming that the target function of the target mainboard is normal, and otherwise, confirming that the target function of the target mainboard is abnormal.
The beneficial effects of the above technical scheme are: whether the target function of the target mainboard is normal or not can be quickly determined by comparing the test result with the expected result, the evaluation efficiency is improved, furthermore, accurate evaluation is realized by judging whether the difference degree is within a preset range or not and providing a normal working range, and the fault tolerance rate is improved.
In one embodiment, the calculating a degree of fit of the first topological mapping frame to a second topological mapping frame of each first test environment comprises:
acquiring a generation sequence of the first topological mapping frame;
solving the parameter vector of the generated sequence, and constructing a frame response function expression according to the parameter vector;
acquiring an impulse response function matrix of each structure in a first topological mapping frame;
testing the change condition of matrix factors in the impulse response function matrix of each structure of the first topological mapping framework in the working process;
establishing a motion equation of each structure according to the change condition;
determining an environment variable offset value of a test environment to be constructed according to the motion equation of each structure;
determining a frame response function analytic expression according to the environment variable offset value and the frame response function expression;
modeling the frame response function analytic expression to obtain a frame model;
testing the frame model by using preset data to obtain a displacement response sequence of a first topological mapping frame;
determining a first dynamic sequence of a first topological mapping frame according to the displacement response sequence;
obtaining a second dynamic sequence of a second topological mapping frame for each first test environment,
calculating a fitness of the first dynamic sequence to each second dynamic sequence;
and taking a second test environment corresponding to a target second dynamic sequence with the highest fitting degree with the first dynamic sequence in the plurality of second dynamic sequences as a sample frame.
The beneficial effects of the above technical scheme are: the first dynamic sequence of the first topological mapping frame obtained by constructing the frame model can accurately obtain the second test environment adapted to the specific parameters of the first topological mapping frame and experimental tests, and is more adaptive and practical compared with the mapping frame directly compared with coding in the prior art.
This embodiment also discloses a mainboard test system, as shown in fig. 4, the system includes:
a receiving module 401, configured to receive a function test instruction of a preset server for a target motherboard;
a calling module 402, configured to call a target guidance file corresponding to the function test instruction from a preset database according to the function test instruction;
a building module 403, configured to build, through the target boot file, a test environment of a target function corresponding to the function test instruction;
the test module 404 is configured to test a target function of the target motherboard by using the test environment, obtain a test result, and determine a fault condition of the target motherboard according to the test result.
The working principle and the advantageous effects of the above technical solution have been explained in the method claims, and are not described herein again.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111459464.5A CN114138581B (en) | 2021-12-02 | 2021-12-02 | Mainboard test method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111459464.5A CN114138581B (en) | 2021-12-02 | 2021-12-02 | Mainboard test method and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114138581A true CN114138581A (en) | 2022-03-04 |
| CN114138581B CN114138581B (en) | 2022-08-05 |
Family
ID=80387215
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111459464.5A Active CN114138581B (en) | 2021-12-02 | 2021-12-02 | Mainboard test method and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114138581B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114740401A (en) * | 2022-03-24 | 2022-07-12 | 深圳市三一联光智能设备股份有限公司 | Novel test method and system |
| CN118244746A (en) * | 2024-05-30 | 2024-06-25 | 国网山东省电力公司枣庄供电公司 | An automatic test system for function parameters of refrigeration and insulation box controller |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080163001A1 (en) * | 2006-12-29 | 2008-07-03 | Inventec Corporation | Method for facilitating BIOS testing |
| CN103424683A (en) * | 2012-05-18 | 2013-12-04 | 鸿富锦精密工业（深圳）有限公司 | Mainboard test system and method |
| CN103678130A (en) * | 2013-12-17 | 2014-03-26 | 中国联合网络通信集团有限公司 | Automated performance test method and platform |
| CN107273249A (en) * | 2016-04-06 | 2017-10-20 | 龙芯中科技术有限公司 | Motherboard test method, processor and main board testing system |
| CN107992409A (en) * | 2017-11-21 | 2018-05-04 | 平安养老保险股份有限公司 | Method for generating test case, device, computer equipment and storage medium |
-
2021
- 2021-12-02 CN CN202111459464.5A patent/CN114138581B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080163001A1 (en) * | 2006-12-29 | 2008-07-03 | Inventec Corporation | Method for facilitating BIOS testing |
| CN103424683A (en) * | 2012-05-18 | 2013-12-04 | 鸿富锦精密工业（深圳）有限公司 | Mainboard test system and method |
| CN103678130A (en) * | 2013-12-17 | 2014-03-26 | 中国联合网络通信集团有限公司 | Automated performance test method and platform |
| CN107273249A (en) * | 2016-04-06 | 2017-10-20 | 龙芯中科技术有限公司 | Motherboard test method, processor and main board testing system |
| CN107992409A (en) * | 2017-11-21 | 2018-05-04 | 平安养老保险股份有限公司 | Method for generating test case, device, computer equipment and storage medium |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114740401A (en) * | 2022-03-24 | 2022-07-12 | 深圳市三一联光智能设备股份有限公司 | Novel test method and system |
| CN118244746A (en) * | 2024-05-30 | 2024-06-25 | 国网山东省电力公司枣庄供电公司 | An automatic test system for function parameters of refrigeration and insulation box controller |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114138581B (en) | 2022-08-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111026645B (en) | User interface automatic test method and device, storage medium and electronic equipment | |
| CN114138581A (en) | Mainboard test method and system | |
| CN101272580B (en) | Self-adapting mobile base station system reliability estimation method based on feedback | |
| CN110405388A (en) | Predict the method, apparatus and electronic equipment of welding quality | |
| CN111190827A (en) | Interface automation test method and device, storage medium and electronic equipment | |
| CN113838480B (en) | Washing machine abnormal sound detection method and device and electronic equipment | |
| CN114255784A (en) | A fault diagnosis method and related device for substation equipment based on voiceprint recognition | |
| CN112148591A (en) | Office software compatibility test system and method | |
| CN114741284B (en) | Task reliability evaluation method, device, computer equipment and storage medium | |
| CN107562621A (en) | The method and apparatus for determining manual test use-case and tested code incidence relation | |
| CN102426089B (en) | Method and device for realizing quick stress screen of product | |
| CN118408582B (en) | Contact encoder qualified detection method and system | |
| CN115328689A (en) | Fault diagnosis method, device, equipment and program product | |
| CN114218078A (en) | UI page testing method, device and equipment and readable storage medium | |
| CN114154799A (en) | Material quality inspection method and device and incoming material quality visual inspection system | |
| JP6644577B2 (en) | Testing system | |
| CN116453437B (en) | Display screen module testing method, device, equipment and storage medium | |
| JP7062936B2 (en) | Quality prediction program, quality prediction method and quality prediction device | |
| CN110765680A (en) | Intelligent damage identification method and device for engineering structure and electronic equipment | |
| CN117054517A (en) | Ultrasonic line detection method for display device | |
| CN115269240A (en) | Detection method and device of storage hardware, terminal equipment and computer medium | |
| CN114113900A (en) | GIL detection system and using method thereof | |
| CN115473831B (en) | Reliability verification method and system for Internet of things chip | |
| CN116627700A (en) | Memory fault detection and processing method, device, equipment and storage medium | |
| CN111680392B (en) | Method and device for quantifying reliability of complex electronic system and computer equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |