CN114116355A

CN114116355A - Memory test method and device and electronic equipment

Info

Publication number: CN114116355A
Application number: CN202111448794.4A
Authority: CN
Inventors: 卢双堂; 许志豪
Original assignee: New H3C Technologies Co Ltd Hefei Branch
Current assignee: New H3C Technologies Co Ltd Hefei Branch
Priority date: 2021-11-30
Filing date: 2021-11-30
Publication date: 2022-03-01

Abstract

The invention relates to the technical field of memory testing, in particular to a memory testing method, a device and electronic equipment, wherein the method comprises the steps of obtaining a fault physical address and a preset address offset of a target memory; determining a fault physical address range based on the fault physical address and the preset address offset; setting the attributes of all physical addresses in the fault physical address range to be locked; converting the failed physical address range to a virtual address range; and performing memory test on the target memory based on the virtual address range. By screening the test objects in the target memory by using the fault physical address, the test is only carried out aiming at the fault physical address range without integral test, the memory test range is reduced, and the memory fault coupling and multiple write-in fault performance enable the memory fault to occur in the adjacent line range, so the reliability of the test result can be ensured by testing aiming at the fault physical address range.

Description

Memory test method and device and electronic equipment

Technical Field

The invention relates to the technical field of memory testing, in particular to a memory testing method, a memory testing device and electronic equipment.

Background

The memory is a precise high-speed server component, and has the characteristics of various faults and complex types. As memory speed is upgraded and manufacturing technology is improved, the granularity is more and more precise and the single memory capacity is larger, such as 128G DDR4 in the latest 12-14nm technology. The precision is accompanied by the increase of interference type faults, some faults of the types need to be excited by a specific sensitizing sequence, and some faults need to be excited by repeated high-strength reading and writing for many times, so that the faults are reflected on production test, and the memory faults are difficult to discover and reappear.

In the prior art, the memtest algorithm is used for reading, writing and pressurizing all virtual addresses in the memory on the server. Because all the virtual addresses are tested, one complete fault recurrence test takes long time, one 32G memory needs nearly half an hour, the recurrence time of the fault is long, and the efficiency is low.

Disclosure of Invention

In view of this, embodiments of the present invention provide a memory testing method, a memory testing device, and an electronic device, so as to solve the problem of low efficiency of memory testing.

According to a first aspect, an embodiment of the present invention provides a memory test method, including:

acquiring a fault physical address and a preset address offset of a target memory;

determining a fault physical address range based on the fault physical address and the preset address offset;

setting the attributes of all physical addresses in the fault physical address range to be locked;

converting the failed physical address range to a virtual address range;

and performing memory test on the target memory based on the virtual address range.

According to the memory test method provided by the embodiment of the invention, the test object in the target memory is screened by using the fault physical address, only the fault physical address range is tested without integral test, the memory test range is reduced, and the memory fault coupling and multiple write-in faults are expressed to enable the memory fault to occur in the adjacent row and column ranges, so that the fault physical address range is determined by the fault physical address, and the reliability of the test result can be ensured by testing the fault physical address range; meanwhile, the attributes of all physical addresses in the fault address range are set to be locked, so that the mapping failure of the subsequent virtual address range mapping caused by the mapping of an operating system to the fault physical addresses in the test process can be avoided, and the normal operation of the test is ensured.

With reference to the first aspect, in a first implementation manner of the first aspect, the converting the failed physical address range into a virtual address range includes:

converting the failure physical address range into a target physical address range which can be identified by an operating system;

converting the target physical address range to the virtual address range.

The memory test method provided by the embodiment of the invention converts the fault physical address range into the virtual address range which can be identified by the operating system, so that the memory read-write can be used for replacing the I/O read-write, higher performance can be obtained, and the test efficiency can be improved.

With reference to the first implementation manner of the first aspect, in a second implementation manner of the first aspect, the converting the target physical address range into the virtual address range includes:

acquiring the CPU type and topology information;

and converting the target physical address range into the virtual address range based on the CPU type and the topology information.

The memory test method provided by the embodiment of the invention can be used for accurately converting the virtual address range by acquiring the CPU type and the topology information, thereby ensuring the reliability of the virtual address range conversion.

With reference to the first aspect, in a third implementation manner of the first aspect, before the step of obtaining the faulty physical address and the preset address offset of the target memory, the method further includes:

closing memory interleaving to make the physical addresses of the target memory continuous.

In the memory test method provided by the embodiment of the invention, because the memory address is discrete and is not suitable for continuous reading and writing in the memory interleaving mode, interleaving needs to be closed to ensure the continuity of the physical address of the memory.

With reference to the third implementation manner of the first aspect, in a fourth implementation manner of the first aspect, the closing memory interleaving includes:

and calling and modifying the BIOS configuration file to close the memory interleaving, and restarting the target memory.

According to the memory testing method provided by the embodiment of the invention, the automatic closing of the memory interleaving is realized by automatically calling the BIOS configuration file, and the target memory is restarted to ensure that the memory after the memory interleaving is closed is available.

With reference to the first aspect, in a fifth implementation manner of the first aspect, the performing a memory test on the target memory based on the virtual address range includes:

acquiring the quantity of the target memories to open threads corresponding to the target memories one by one;

and performing memory test on the corresponding target memory based on each thread.

According to the memory test method provided by the embodiment of the invention, the memory test is parallel through the threads corresponding to the target memories one by one, and the test efficiency is improved.

With reference to the fifth implementation manner of the first aspect, in a sixth implementation manner of the first aspect, the performing a memory test on the corresponding target memory based on each thread includes:

acquiring a virtual address range corresponding to each fault physical address in each target memory;

and performing circular memory test on each virtual address range based on the corresponding thread.

According to a second aspect, an embodiment of the present invention further provides a memory test apparatus, including:

the acquisition module is used for acquiring a fault physical address and a preset address offset of the target memory;

the determining module is used for determining a fault physical address range based on the fault physical address and the preset address offset;

the setting module is used for setting the attributes of all physical addresses in the fault physical address range to be locked;

a translation module to translate the failed physical address range to a virtual address range;

and the testing module is used for carrying out memory testing on the target memory based on the virtual address range.

According to the memory test device provided by the embodiment of the invention, the test objects in the target memory are screened by using the fault physical address, only the fault physical address range is tested without integral test, the memory test range is reduced, and the memory fault coupling and multiple write-in faults are expressed to enable the memory fault to occur in the adjacent row and column ranges, so that the fault physical address range is determined by the fault physical address, and the reliability of the test result can be ensured by testing the fault physical address range; meanwhile, the attributes of all physical addresses in the fault address range are set to be locked, so that the mapping failure of the subsequent virtual address range mapping caused by the mapping of an operating system to the fault physical addresses in the test process can be avoided, and the normal operation of the test is ensured.

According to a third aspect, an embodiment of the present invention provides an electronic device, including: the memory device comprises a memory and a processor, wherein the memory and the processor are communicatively connected with each other, the memory stores computer instructions, and the processor executes the computer instructions to execute the memory test method of the first aspect or any one of the embodiments of the first aspect.

According to a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, which stores computer instructions for causing a computer to execute the memory test method described in the first aspect or any one of the implementation manners of the first aspect.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a flow chart of a memory test method according to an embodiment of the invention;

FIG. 2 is a flow chart of a memory test method according to an embodiment of the invention;

FIG. 3 is a flow chart of a memory test method according to an embodiment of the invention;

FIG. 4 is a block diagram of a memory test apparatus according to an embodiment of the invention;

fig. 5 is a schematic hardware structure diagram of a sub device according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The memory test method provided by the embodiment of the invention reduces the memory test range through the recording of the fault physical address so as to achieve the effect of shortening the fault recurrence time. For example, for a 32G memory, in order to meet the requirement of fault recurrence in the prior art, 32G needs to be run full, and as long as a fault physical address range corresponding to each fault physical address is run, the fault recurrence time is shortened by more than one hundred times. Due to the great improvement of the testing efficiency, an algorithm with high complexity can be used, and the fault recurrence probability is improved; in addition, in a short time, the test cycle times of the executed algorithm are increased, and the recurrence probability can be theoretically increased; based on the fault physical address of the memory, the fault memory position can be accurately determined.

In accordance with an embodiment of the present invention, there is provided an embodiment of a memory test method, it should be noted that the steps illustrated in the flowchart of the accompanying drawings may be executed in a computer system such as a set of computer-executable instructions, and that although a logical order is illustrated in the flowchart, in some cases, the steps illustrated or described may be executed in an order different than that illustrated or described herein.

In this embodiment, a memory testing method is provided, which can be used in electronic devices, such as servers, computers, tablet computers, and the like, and fig. 1 is a flowchart of the memory testing method according to the embodiment of the present invention, as shown in fig. 1, the flowchart includes the following steps:

and S11, acquiring the fault physical address and the preset address offset of the target memory.

If the memory fails in the operation process, the SPD in the memory records the failed physical address, which is called a failed physical address. Since the memory fault characteristic state is a Coupling fault (Coupling fault): a cell i is said to be coupled to a cell j if and only if the cell i is always at a certain determined value x (x {0, 1}) when the cell j is in a certain particular state y (y {0, 1 }). The coupling relationship is not necessarily symmetrical, that is, the cell i is coupled to the cell j, and not necessarily the cell j is also coupled to the cell i. That is, memory failure coupling and multiple write failures appear to cause memory failures to occur in adjacent rank ranges. Therefore, a preset address offset needs to be set, so as to perform subsequent memory detection by combining the preset address offset on the basis of the failed physical address. Typically 64 bits per row, so 20M above and below the physical address of the failure is sufficient to contain the failed cell due to coupling effects. Of course, the specific value of the address offset may be set according to actual requirements, and is not limited herein.

For each target memory, the number of the failed physical addresses may be one, two or more, and so on. Accordingly, for the electronic device, the target memory amount that can be tested simultaneously is set according to the actual requirement, and is not limited herein.

And S12, determining the fault physical address range based on the fault physical address and the preset address offset.

After the electronic equipment acquires the fault physical address, adding a preset address offset on the basis of the fault physical address to determine a fault physical address range. On the basis, after the fault physical address is used as a base address and is vertically offset by a preset address offset, a fault physical address range is determined.

For each failing physical address, the electronic device may obtain a corresponding failing physical address range. For example, there are 4 target memories, and each target memory corresponds to 2 faulty physical addresses, so that each target memory corresponds to 2 faulty physical address ranges.

S13, setting the attribute of all physical addresses in the fault physical address range as locking.

The physical address attribute is determined by the hardware BIOS and passed to the operating system via the E820 table. And then the operating system performs corresponding operation based on the attribute of each physical address. The physical address attributes include available Usable, locked Reserved, ACPI data, and ACPI NVS. Specifically, Usable: indicating a physical address that has been mapped to physical memory; reserved: the intervals are not mapped to any place and cannot be used as RAM, but Kernel can decide to map the intervals to other places, such as PCI devices, the mapping condition of the physical address space can be checked through reading/proc/iomem, and how the reserved space is further allocated to different devices for use can be known; ACPI data: indicating that the ACPI data is mapped to a RAM space for storing the ACPI data, and an operating system should read the ACPI Table into the interval; ACPI NVS: the representation maps to the non-volatile memory space used to store ACPI data, which is unusable by the operating system. The attribute of the physical address is set in the BIOS and passed to the operating system OS through the E820 table.

After the electronic device determines the faulty physical address range, the attributes of all physical addresses in the faulty physical address range are set to be locked, and the operating system does not allocate the faulty physical address range to other processes or the system itself for use, so that the virtual address range translation failure of subsequent S14 can be avoided. And setting the attribute of the failed physical address as reserved: indicating that these intervals are not mapped anywhere and cannot be used as RAM, so setting the reserved attribute address field does not affect system usage and using it to run memory algorithm read-write test fires the faulty cell.

S14, converting the failed physical address range to a virtual address range.

The electronic equipment sequentially maps the virtual addresses of all the physical addresses in the fault physical address range to determine the corresponding virtual address range.

S15, performing memory test on the target memory based on the virtual address range.

The electronic device performs a memory test on the virtual address range using a memory test algorithm, i.e., passes a stress test to reproduce a failure. The memory test algorithm may adopt some algorithms with high complexity, such as Data Retention, March SD, and the like.

Details about this step will be described later.

In the memory test method provided by this embodiment, the test object in the target memory is screened by using the faulty physical address, and only the faulty physical address range is tested without an integral test, so that the memory test range is narrowed, and the memory fault coupling and the multiple write-in fault performance cause the memory fault to occur in the adjacent row and column ranges, so that the faulty physical address range is determined by the faulty physical address, and the reliability of the test result can be ensured by testing the faulty physical address range; meanwhile, the attributes of all physical addresses in the fault address range are set to be locked, so that the mapping failure of the subsequent virtual address range mapping caused by the mapping of an operating system to the fault physical addresses in the test process can be avoided, and the normal operation of the test is ensured.

In this embodiment, a memory testing method is provided, which can be used in electronic devices, such as servers, computers, tablet computers, and the like, fig. 2 is a flowchart of the memory testing method according to the embodiment of the present invention, and as shown in fig. 2, the flowchart includes the following steps:

and S21, acquiring the fault physical address and the preset address offset of the target memory.

Please refer to S11 in fig. 1, which is not described herein again.

And S22, determining the fault physical address range based on the fault physical address and the preset address offset.

Please refer to S12 in fig. 1, which is not described herein again.

S23, setting the attribute of all physical addresses in the fault physical address range as locking.

Please refer to S13 in fig. 1, which is not described herein again.

S24, converting the failed physical address range to a virtual address range.

Specifically, S24 includes:

s241, converting the fault physical address range into a target physical address range which can be identified by an operating system.

The failure physical address is represented by a row and a column during recording, namely the failure physical address row and col recorded by the SPD. The physical address recognizable by the operating system is represented in other forms, for example, 0x28F 0000000. Therefore, the electronic device needs to convert the failed physical address range into the target physical address range based on the corresponding correspondence. The corresponding correspondence relationship is determined by hardware of the memory, for example, which physical address of the operating system corresponds to the first row and the first column of the physical address of the memory, and based on this, the electronic device can convert all the failed physical address range into a target physical address range recognizable by the operating system.

S242, converting the target physical address range into a virtual address range.

After determining the target physical address range, the electronic device converts the target physical address range into a virtual address range. The virtual address range can be obtained by mapping through a mmap function.

In some optional implementations of this embodiment, the step S242 may include:

(1) and acquiring the CPU type and topology information.

(2) Based on the CPU type and topology information, the target physical address range is converted to a virtual address range.

CPU types are obtained, for example, intel, AMD, ARM and intel have a plurality of generations of platforms, for example, Skylake Ikelake platform, and logic cores under the CPU are obtained to establish thread binding. The electronic equipment maps a target physical address range into a virtual address range on the basis of the CPU type and the topology information by using a mmap function, wherein the mapping aims to improve the read-write speed of a test memory address by using a mmap function mapping/dev/mem file so as to improve the test efficiency.

The CPU type and the topology information are obtained so as to accurately convert the virtual address range, and the reliability of virtual address range conversion is ensured.

S25, performing memory test on the target memory based on the virtual address range.

Please refer to S15 in fig. 1, which is not described herein again.

The memory test method provided by this embodiment converts the physical address range of the fault into the virtual address range recognizable by the operating system, so that the memory read-write can be used to replace the I/O read-write, thereby obtaining higher performance and improving the test efficiency.

In this embodiment, a memory testing method is provided, which can be used in electronic devices, such as servers, computers, tablet computers, and the like, fig. 3 is a flowchart of the memory testing method according to the embodiment of the present invention, and as shown in fig. 3, the flowchart includes the following steps:

s31, the memory interleave is closed so that the physical addresses of the target memory are consecutive.

Before testing, the electronic device calls and modifies the BIOS configuration file through the corresponding script to close interleaving, and then restarts the target memory to take effect. Alternatively, the BIOS interface may be manually started on the server or the computer to manually close the interleaving.

And S32, acquiring the fault physical address and the preset address offset of the target memory.

Please refer to S11 in fig. 1, which is not described herein again.

And S33, determining the fault physical address range based on the fault physical address and the preset address offset.

Please refer to S12 in fig. 1, which is not described herein again.

S34, setting the attribute of all physical addresses in the fault physical address range as locking.

Please refer to S13 in fig. 1, which is not described herein again.

S35, converting the failed physical address range to a virtual address range.

Please refer to S24 in fig. 2 for details, which are not described herein.

S36, performing memory test on the target memory based on the virtual address range.

Specifically, S36 includes:

s361, obtaining the number of the target memories to open the threads corresponding to the target memories one by one.

The amount of the target memory may be automatically obtained by the electronic device, may be set by a user on an interactive interface provided by the electronic device, or may be obtained by the electronic device in another manner, which is not limited herein.

After the quantity of the target memories is determined, the electronic equipment starts the corresponding quantity of threads so as to perform parallel testing on each target memory.

S362, performing a memory test on the corresponding target memory based on each thread.

The threads correspond to the target memories one by one, and the memory test of the corresponding target memories can be independently completed in each thread, namely, the memory test is performed on the virtual address range by using a corresponding memory algorithm according to the virtual address range determined by the fault physical address of the target memory.

In some optional implementations of this embodiment, the S362 may include:

(1) and acquiring a virtual address range corresponding to each fault physical address in each target memory.

(2) And performing circular memory test on each virtual address range based on the corresponding thread.

As described above, for each target memory, there may be at least one faulty physical address, a corresponding virtual address range is corresponding to each faulty physical address, and a cycle test is performed on the virtual address range corresponding to the target memory in the same thread, so as to implement a stress-enhanced test on the target memory. That is, the electronic device tests multiple failed target memories in parallel and simultaneously, and a single target memory tests the virtual address ranges corresponding to the failed physical addresses of the 3 SPDs in series.

As an optional implementation manner of this embodiment, while performing the memory test, the ECC and MCE detection is performed to determine whether the check is performed again, so as to determine whether the memory fails.

In the memory test method provided by this embodiment, since the memory addresses are discrete in the memory interleaving mode and are not suitable for continuous reading and writing, interleaving needs to be closed to ensure continuity of the physical addresses of the memory. The memory test is parallel through the threads corresponding to the target memories one by one, and the test efficiency is improved.

The memory testing method automatically acquires the SPD fault physical address, judges whether a fault memory bank exists under the server or not, automatically establishes threads according to the number of the fault memory banks to perform parallel testing on all the memory banks, and performs serial forced tightening testing on a single memory according to the SPD fault physical address. That is, based on the SPD fault address record, the memory test range is narrowed to achieve the effect of shortening the fault recurrence time, for example, 32G memory, the original recurrence needs to run full of 32G, and the fault recurrence time is shortened by more than one hundred times as long as each fault runs 20M.

Furthermore, the great improvement of the test efficiency can introduce algorithms with high complexity, such as Data Retention, March SD and the like, into the memory fault recurrence test; in addition, in a short time, the number of times of the executed algorithm test circulation is increased, and the recurrence probability can be increased.

Furthermore, the testing method is carried out based on the real fault physical address, and the fault memory position can be accurately determined.

In this embodiment, a memory test apparatus is further provided, and the apparatus is used to implement the foregoing embodiments and preferred embodiments, and the description of the apparatus is omitted for brevity. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.

The present embodiment provides a memory test apparatus, as shown in fig. 4, including:

an obtaining module 41, configured to obtain a failure physical address and a preset address offset of a target memory;

a determining module 42, configured to determine a faulty physical address range based on the faulty physical address and the preset address offset;

a setting module 43, configured to set attributes of all physical addresses in the failed physical address range as locked;

a translation module 44 for translating the failing physical address range to a virtual address range;

and a testing module 45, configured to perform a memory test on the target memory based on the virtual address range.

The memory test device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC circuit, a processor and a memory that execute one or more software or fixed programs, and/or other devices that can provide the above-mentioned functions.

Further functional descriptions of the modules are the same as those of the corresponding embodiments, and are not repeated herein.

An embodiment of the present invention further provides an electronic device, which has the memory testing apparatus shown in fig. 4.

Referring to fig. 5, fig. 5 is a schematic structural diagram of an electronic device according to an alternative embodiment of the present invention, and as shown in fig. 5, the electronic device may include: at least one processor 51, such as a CPU (Central Processing Unit), at least one communication interface 53, memory 54, at least one communication bus 52. Wherein a communication bus 52 is used to enable the connection communication between these components. The communication interface 53 may include a Display (Display) and a Keyboard (Keyboard), and the optional communication interface 53 may also include a standard wired interface and a standard wireless interface. The Memory 54 may be a high-speed RAM Memory (volatile Random Access Memory) or a non-volatile Memory (non-volatile Memory), such as at least one disk Memory. The memory 54 may alternatively be at least one memory device located remotely from the processor 51. Wherein the processor 51 may be in connection with the apparatus described in fig. 4, the memory 54 stores an application program, and the processor 51 calls the program code stored in the memory 54 for performing any of the above-mentioned method steps.

The communication bus 52 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The communication bus 52 may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one thick line is shown in FIG. 5, but this is not intended to represent only one bus or type of bus.

The memory 54 may include a volatile memory (RAM), such as a random-access memory (RAM); the memory may also include a non-volatile memory (english: non-volatile memory), such as a flash memory (english: flash memory), a hard disk (english: hard disk drive, abbreviated: HDD) or a solid-state drive (english: SSD); the memory 54 may also comprise a combination of the above types of memories.

The processor 51 may be a Central Processing Unit (CPU), a Network Processor (NP), or a combination of a CPU and an NP.

The processor 51 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof. The PLD may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or any combination thereof.

Optionally, the memory 54 is also used to store program instructions. The processor 51 may call program instructions to implement the memory test method as shown in any of the embodiments of the present application.

The embodiment of the invention also provides a non-transitory computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions can execute the memory test method in any method embodiment. The storage medium may be a magnetic Disk, an optical Disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a Flash Memory (Flash Memory), a Hard Disk (Hard Disk Drive, abbreviated as HDD), a Solid State Drive (SSD), or the like; the storage medium may also comprise a combination of memories of the kind described above.

Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A memory test method, comprising:

converting the failed physical address range to a virtual address range;

2. The method of claim 1, wherein translating the failing physical address range to a virtual address range comprises:

converting the target physical address range to the virtual address range.

3. The method of claim 2, wherein translating the target physical address range to the virtual address range comprises:

acquiring the CPU type and topology information;

4. The method according to claim 1, wherein the step of obtaining the faulty physical address and the preset address offset of the target memory further comprises:

5. The method of claim 4, wherein the closing memory interleaving comprises:

6. The method of claim 1, wherein the performing a memory test on the target memory based on the virtual address range comprises:

7. The method according to claim 6, wherein the performing a memory test on the corresponding target memory based on each of the threads comprises:

8. A memory test device, comprising:

9. An electronic device, comprising:

a memory and a processor, the memory and the processor being communicatively coupled to each other, the memory having stored therein computer instructions, the processor executing the computer instructions to perform the memory testing method of any one of claims 1-7.

10. A computer-readable storage medium having stored thereon computer instructions for causing a computer to perform the memory testing method of any one of claims 1-7.