CN114115720A - High frame rate low delay figure generating device based on FPGA - Google Patents
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Abstract
The invention provides a high frame rate and low delay graph generating device based on an FPGA (field programmable gate array), which comprises a graph drawing processor, the FPGA, a character memory, a graph display memory and an external video memory; the FPGA comprises a drawing command buffer unit, a graph drawing unit, a display memory read-write control unit, an ECC (error correction code) checking unit, an external video control unit, a display superposition unit and a display output adjusting unit. The invention is suitable for generating graphs in display systems of aviation military aircraft and civil aircraft, can effectively solve the design bottleneck brought by the application of commercial COTS display chips at present, has the remarkable advantages of high frame rate, low delay, high integration level and low power consumption, and powerfully supports the design and development work of the display system.
Description
Technical Field
The invention relates to a high frame rate and low delay graph generating device based on an FPGA (field programmable gate array), and belongs to the field of avionic design.
Background
The airborne display system is an important component of an aircraft avionics system and is a window for a pilot to acquire flight attitude parameters and control flight. The head-up display, the down-view display and other devices are used as important human-computer interface devices to convert flight parameter information into display information so as to provide visual flight guidance for pilots.
At present, a commercial COTS display chip is adopted in an airborne display system to complete the generation of graphs, but the following problems exist:
1. the delay is large, the real-time requirement of airborne display equipment is high, the delay of a commercial display chip is large, and the system delay index is restricted;
2. the frame rate is low, the frame rate of a complex display picture is low, and the timely display of flight parameter information is influenced;
3. the civil aircraft display product has less applicable airworthiness support data, and the application of commercial COTS devices in the product is restricted.
4. The external video superposition of a common commercial COTS display chip needs to be completed by additionally adding a design circuit.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides the high-frame-rate and low-delay graph generating device based on the FPGA, the FPGA device is used for completing the functions of receiving a drawing instruction, generating a graph, superposing external video and displaying, adjusting and outputting the graph, the device has the characteristics of high frame rate, low delay and low power consumption, and is beneficial to the heat dissipation design of a system.
The technical scheme of the invention is as follows:
the high frame rate and low delay graph generating device based on the FPGA comprises a graph drawing processor, the FPGA, a character memory, a graph display memory and an external video memory;
the FPGA comprises: the device comprises a drawing command buffer unit, a graphic drawing unit, a video memory read-write control unit, an ECC (error correction code) checking unit, an external video control unit, a display superposition unit and a display output adjusting unit;
the drawing command buffer unit buffers a drawing command sent by the graphic drawing processor to the FPGA and outputs the drawing command to the graphic drawing unit, wherein the drawing command comprises a setting command and a graphic command;
under the condition that the vertical synchronous instruction is started, the drawing command buffer unit adopts a three-level buffer arbitration mechanism to solve the asynchronous problem of drawing instruction transmission and ensure that the drawing instruction read by the drawing unit is a frame of complete data instruction; under the condition that the vertical synchronous instruction is closed, a second-level cache region of the third-level cache arbitration mechanism is changed from double-cache to single-cache, so that low-delay transmission of the drawing instruction is ensured; the read-write clock configurations at two ends of the second-level buffer area of the third-level cache arbitration mechanism have the same speed;
the graphics drawing unit analyzes the graphics command and draws graphics primitives by adopting a multi-channel parallel drawing mechanism according to different graphics primitives; after the primitive drawing is finished, storing the primitive in a direct result buffer area, an interpolation result buffer area, a filling result buffer area and a first interpolation result buffer area according to different characteristics of drawing results; the device comprises a direct result cache region, an interpolation result cache region, a filling result cache region and a first interpolation result cache region, wherein the direct result cache region is used for storing data of pixel points which are to be directly output and are unrelated to background colors, the interpolation result cache region is used for storing data of pixel points needing interpolation correction, the filling result cache region is used for storing data of filling triangles, filling rectangles and filling circles, and the first interpolation result cache region is used for storing data of single-side anti-aliasing at the outer edge of a graph when anti-aliasing is performed on the filling triangles, the filling rectangles and the filling circles;
the video memory read-write control unit writes the result of the drawing of the primitive into the graphic video memory and reads data in the graphic video memory along with the graphic data read-out time sequence of the display superposition unit; the video memory read-write control unit performs interrupt arbitration and judgment on data write-in and read-out operations of a direct result buffer area, an interpolation result buffer area, a filling result buffer area and a first interpolation result buffer area, wherein the priority is graph read > direct result buffer area write > interpolation result buffer area write > filling result buffer area write > first interpolation result buffer area write; the graphic data reading time sequence is determined according to the video time sequence which needs to be output finally;
the ECC check unit is used for carrying out ECC check on the data written into the graphic display memory and the drawing data read out of the display memory by taking a data frame as a unit;
under the condition that the external video overlapping function is started, after the external video control unit caches input external video data in an external video memory, the display overlapping unit reads out external video pixel data from the external video control unit according to the time sequence read out by the graphic data, performs pixel level overlapping on the external video pixel data and the graphic data, and sends the external video pixel data and the graphic data to the display output adjusting unit; under the condition that the external video overlapping function is closed, the display overlapping unit directly sends the graphic data read from the graphic display memory to the display output adjusting unit;
and the display output adjusting unit adjusts and outputs the input data according to the set output video protocol.
Further, the setting command comprises parameter settings of graphic resolution, windowing, block areas, background colors, vertical synchronization function opening and closing, and external video superposition function opening and closing.
Further, the graphics command includes a primitive type drawing instruction and a primitive drawing parameter; the primitive types comprise points, lines, circles, triangles, arcs and characters; the primitive drawing parameters comprise color and line width.
Furthermore, the drawing command buffer unit comprises three levels of buffer units, wherein the first level of buffer unit is an instruction receiving storage unit, the second level of buffer unit is provided with two instruction buffer areas, and the third level of buffer unit is an instruction sending storage unit;
after the instruction receiving and storing unit receives a frame of drawing instruction, the drawing instruction is sequentially and alternately written into two instruction cache regions of the second-level buffer unit by taking the frame as a unit under the condition that the vertical synchronous instruction is opened; under the condition that the vertical synchronous instruction is closed, writing the drawing instruction into a certain specified instruction cache region in the second-level buffer unit by taking a frame as a unit;
for the first frame drawing instruction after being electrified, directly reading the first frame drawing instruction from the second-level buffer unit to an instruction sending storage unit; for the following drawing instruction, after receiving a drawing completion signal sent by the drawing unit, reading the drawing instruction from the second-level buffer unit to the instruction sending storage unit according to the following reading rule:
in case of vertical synchronization command on:
when data in the first instruction cache region are to be read, judging a flag1 signal, if the flag1 signal is valid, reading the data in the first instruction cache region, otherwise, continuously reading the data in the second instruction cache region; the flag1 signal indicates whether the first instruction buffer is written with data again after the data of the first instruction buffer is read last time, wherein if the data is written with the first instruction buffer again, the flag1 signal is valid, otherwise, the flag1 signal is invalid;
when data in the second instruction cache region are to be read, judging a flag2 signal, if the flag2 signal is valid, reading the data in the second instruction cache region, otherwise, continuously reading the data in the first instruction cache region; the flag2 signal indicates whether the second instruction buffer is written with data again after the data of the second instruction buffer is read last time, wherein if the data is written into the second instruction buffer again, the flag2 signal is valid, otherwise, the flag2 signal is invalid;
in case of vertical synchronization instruction off:
and directly reading the drawing instruction from the specified instruction cache region to the instruction sending storage unit.
Further, the drawing channels comprise a point drawing channel, a horizontal straight line drawing channel, a diagonal line drawing channel, a circular drawing channel, an arc drawing channel, a triangle filling drawing channel, a rectangle filling drawing channel, a circular filling drawing channel and a character drawing channel.
Furthermore, except for drawing characters, drawing other primitives in real time by using an FPGA algorithm, and reading the characters to be drawn from a character memory.
Furthermore, a ping-pong buffer mechanism is adopted in the graphic display memory to solve the problem of reading and writing asynchronous complete frame data.
Further, the formula of the display superposition unit for pixel level superposition is as follows:
R(x,y)＝(255-gray(x,y))*bg_R(x,y)/255；
G(x,y)＝(255-gray(x,y))*bg_G(x,y)/255；
B(x,y)＝(255-gray(x,y))*bg_B(x,y)/255；
wherein, gray represents the gray value of the graphic data, bg _ R, bg _ G, and bg _ B represent the gray value of the external video.
Further, the output timing adjusted by the display output adjustment unit includes VESA timing, LVDS, digital RGB, ARINC818 timing.
Further, after the frame check instruction is started in the setting instruction, the display output adjusting unit completes CRC check of the whole frame output image, replaces the value of the last row and the last column of the output pixel point with a CRC check value, and transmits the value to a lower device to ensure the data safety of the transmission chain.
Advantageous effects
The invention provides a high-frame-rate low-delay graph generating device based on an FPGA (field programmable gate array), which is suitable for graph generation in aviation military aircraft and civil aircraft display systems. The implementation of the method can effectively solve the design bottleneck brought by the application of commercial COTS display chips at present, has the remarkable advantages of high frame rate, low delay, high integration level and low power consumption, and powerfully supports the design and development work of a display system.
Compared with the graph generating device in the conventional aviation display system, the method has the following advantages:
1. high frame rate, adopting multi-channel parallel drawing picture;
2. low latency, pipelined data transmission, storage mechanisms;
3. the integration level is high, and the video superposition function and the graphic generation function are seamlessly coupled;
4. the power consumption is low, and the power consumption of the FPGA device is low.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1: hardware functional block diagrams of device implementations;
FIG. 2: the drawing command buffer unit is constructed schematically;
FIG. 3: the graph drawing unit constitutes a schematic diagram:
FIG. 4: the video memory read-write control unit forms a schematic diagram.
Detailed Description
The following detailed description of embodiments of the invention is intended to be illustrative, and not to be construed as limiting the invention.
The embodiment provides a high-frame-rate low-delay graph generating device based on an FPGA, which is applied to an aviation display system and used for generating images of equipment such as a flat display, a multifunctional display and the like.
As shown in fig. 1, the high frame rate and low delay graphics generating apparatus based on FPGA includes a graphics rendering processor, an FPGA, a character memory, a graphics display memory, and an external video memory.
The FPGA comprises: the device comprises a drawing command buffer unit, a graph drawing unit, a video memory read-write control unit, an ECC (error correction code) checking unit, an external video control unit, a display superposition unit and a display output adjusting unit.
The drawing command buffer unit buffers drawing commands sent to the FPGA by the graphic drawing processor through an external bus and outputs the drawing commands to the graphic drawing unit, wherein the drawing commands comprise setting commands and graphic commands. The setting command comprises parameter settings such as graphic resolution, windowing, block areas, background colors, opening and closing of a vertical synchronization function, opening and closing of an external video superposition function, opening and closing of frame verification and the like; the graphics commands comprise primitive type drawing instructions such as points, lines, circles, triangles, arcs, characters and the like, and primitive drawing parameters such as colors, line widths and the like.
The external bus of the graphics drawing processor for sending the drawing instruction comprises a PCI, a PCIE, a high-speed LINK port and the like.
Under the condition that the vertical synchronous instruction is started, the drawing command buffer unit adopts a three-level buffer arbitration mechanism to solve the asynchronous problem of drawing instruction transmission and ensure that the drawing instruction read by the drawing unit is a frame of complete data instruction; under the condition that the vertical synchronous instruction is closed, a second-level cache region of the third-level cache arbitration mechanism is changed from double-cache to single-cache, so that low-delay transmission of the drawing instruction is ensured; the read-write clock configuration at the two ends of the second-level buffer area of the third-level cache arbitration mechanism has the same speed.
As shown in fig. 2, the drawing command buffer unit includes three stages of buffer units, a first stage of buffer unit is an instruction receiving and storing unit, a second stage of buffer unit has two instruction buffers, and a third stage of buffer unit is an instruction sending and storing unit.
After the instruction receiving and storing unit receives a frame of drawing instruction, the drawing instruction is sequentially and alternately written into two instruction cache regions of the second-level buffer unit by taking the frame as a unit under the condition that the vertical synchronous instruction is opened; in the case of closing the vertical synchronous instruction, the drawing instruction is written into a specified instruction cache area in the second-level buffer unit in a frame unit.
For the first frame drawing instruction after being electrified, directly reading the first frame drawing instruction from the second-level buffer unit to an instruction sending storage unit; for the following drawing instruction, after receiving a drawing completion signal sent by the drawing unit, reading the drawing instruction from the second-level buffer unit to the instruction sending storage unit according to the following reading rule:
in case of vertical synchronization command on:
when data in the first instruction cache region are to be read, judging a flag1 signal, if the flag1 signal is valid, reading the data in the first instruction cache region, otherwise, continuously reading the data in the second instruction cache region; the flag1 signal indicates whether the first instruction buffer is written with data again after the data of the first instruction buffer is read last time, wherein if the data is written with the first instruction buffer again, the flag1 signal is valid, otherwise, the flag1 signal is invalid;
when data in the second instruction cache region are to be read, judging a flag2 signal, if the flag2 signal is valid, reading the data in the second instruction cache region, otherwise, continuously reading the data in the first instruction cache region; the flag2 signal indicates whether the second instruction buffer is written with data again after the data of the second instruction buffer is read last time, wherein if the data is written into the second instruction buffer again, the flag2 signal is valid, otherwise, the flag2 signal is invalid;
in case of vertical synchronization instruction off:
and directly reading the drawing instruction from the specified instruction cache region to the instruction sending storage unit.
Under the condition that the vertical synchronous instruction is opened, the integrity of data frame transmission of the drawing instruction under a sending bus clock domain and a graphic drawing clock domain can be ensured; under the condition that the vertical synchronous instruction is closed, the second-level buffer unit only uses one instruction buffer area to transmit the drawing instruction, and low delay of data transmission is guaranteed.
The graphics drawing unit analyzes the graphics command and draws graphics primitives by adopting a multi-channel parallel drawing mechanism according to different graphics primitives; the drawing channels comprise a point drawing channel, a horizontal straight line drawing channel, a diagonal line drawing channel, a circular drawing channel, an arc drawing channel, a triangular filling drawing channel, a rectangular filling drawing channel, a circular filling drawing channel and a character drawing channel; besides character drawing, other graphic primitives are drawn in real time by an FPGA algorithm, and the character drawing is to read characters to be drawn from a character memory. And after the primitive drawing is finished, storing the primitive in a direct result buffer area, an interpolation result buffer area, a filling result buffer area and a first interpolation result buffer area according to different characteristics of drawing results.
As shown in fig. 3, after receiving the drawing instruction, the graphics drawing unit distinguishes drawing of different primitives according to different command words in the instruction, and the speed of drawing is increased by adopting a multi-channel parallel drawing mode. After the drawing is finished, the drawing result is stored in a buffer area: the direct result cache region is used for storing data of pixel points which are to be directly output and are unrelated to the background color; the interpolation result cache region is used for storing data of pixel points needing interpolation correction and is mainly used for drawing anti-aliasing graphs such as oblique lines, circles and arcs and anti-aliasing characters; the filling result cache region is used for storing data of filled triangles, filled rectangles and filled circles, and the filling result cache region is added, wherein when the filled triangles and the filled circles are anti-aliasing, the data of the triangles and the solid circles which are not anti-aliasing need to be covered on the data of the edges which are anti-aliasing, namely the writing data of the filling result cache region is executed after the writing data of the interpolation result cache region; the first interpolation result cache region is used for storing data of single-side anti-aliasing at the outer edge of the graph when filled triangles, filled rectangles and filled circles are anti-aliasing.
The video memory read-write control unit writes the result of the drawing of the primitive into the graphic video memory and reads data in the graphic video memory along with the graphic data read-out time sequence of the display superposition unit; the video memory read-write control unit performs interrupt arbitration and judgment on data write-in and read-out operations of the direct result buffer area, the interpolation result buffer area, the filling result buffer area and the first interpolation result buffer area, the arbitration mechanism of the image video memory write-in and read-out is shown in fig. 4, and the priority is graph read-out, direct result buffer area write, interpolation result buffer area write, filling result buffer area write and first interpolation result buffer area write; and the graphic data read-out timing is determined according to the video timing which is finally required to be output.
The problem of reading and writing asynchronous complete frame data is solved by adopting a ping-pong cache mechanism in the graphic display memory.
The ECC check unit performs ECC check on the data written into the graphic display memory and the drawing data read out of the display memory by taking a data frame as a unit, so as to ensure the correctness of the drawing data. And carrying out ECC coding when the graphic element drawing result is written into the graphic memory, simultaneously carrying out ECC decoding when the graphic memory is read out, and reporting errors to the graphic drawing processor once the monitoring decoding has errors.
Under the condition that the external video overlapping function is started, after the external video control unit caches input external video data in an external video memory, the display overlapping unit reads out external video pixel data from the external video control unit according to the time sequence read out by the graphic data, performs pixel level overlapping on the external video pixel data and the graphic data, and sends the external video pixel data and the graphic data to the display output adjusting unit; and under the condition that the external video overlapping function is closed, the display overlapping unit directly sends the graphic data read from the graphic display memory to the display output adjusting unit.
The formula for the display superimposing unit to perform pixel level superimposition is as follows:
R(x,y)＝(255-gray(x,y))*bg_R(x,y)/255；
G(x,y)＝(255-gray(x,y))*bg_G(x,y)/255；
B(x,y)＝(255-gray(x,y))*bg_B(x,y)/255；
wherein, gray represents the gray value of the graphic data, bg _ R, bg _ G, and bg _ B represent the gray value of the external video.
And the display output adjusting unit adjusts and outputs the input data according to the set output video VESA protocol.
Besides the VESA timing, the output timing adjusted by the display output adjustment unit may also adopt LVDS, digital RGB, ARINC818 timing.
And after the frame check instruction is started in the setting instruction, the display output adjusting unit finishes CRC check of the whole frame of output image, replaces the RGB 24-bit gray value of the last point of the whole frame of image with a CRC check result, and then outputs the result to ensure the data safety of the transmission chain.
For example, if the resolution of the video is 1280 × 1024, the CRC values of (1280 × 1024-1) pixels are calculated, and the CRC value of the last pixel is replaced with the calculation result of (1280 × 1024-1) pixels, as shown in the following table.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made in the above embodiments by those of ordinary skill in the art without departing from the principle and spirit of the present invention.
Claims (10)
1. A high frame rate low delay figure generating device based on FPGA is characterized in that: the system comprises a graph drawing processor, an FPGA, a character memory, a graph display memory and an external video memory;
the FPGA comprises: the device comprises a drawing command buffer unit, a graphic drawing unit, a video memory read-write control unit, an ECC (error correction code) checking unit, an external video control unit, a display superposition unit and a display output adjusting unit;
the drawing command buffer unit buffers a drawing command sent by the graphic drawing processor to the FPGA and outputs the drawing command to the graphic drawing unit, wherein the drawing command comprises a setting command and a graphic command;
under the condition that the vertical synchronous instruction is started, the drawing command buffer unit adopts a three-level buffer arbitration mechanism to solve the asynchronous problem of drawing instruction transmission and ensure that the drawing instruction read by the drawing unit is a frame of complete data instruction; under the condition that the vertical synchronous instruction is closed, a second-level cache region of the third-level cache arbitration mechanism is changed from double-cache to single-cache, so that low-delay transmission of the drawing instruction is ensured; the read-write clock configurations at two ends of the second-level buffer area of the third-level cache arbitration mechanism have the same speed;
the graphics drawing unit analyzes the graphics command and draws graphics primitives by adopting a multi-channel parallel drawing mechanism according to different graphics primitives; after the primitive drawing is finished, storing the primitive in a direct result buffer area, an interpolation result buffer area, a filling result buffer area and a first interpolation result buffer area according to different characteristics of drawing results; the device comprises a direct result cache region, an interpolation result cache region, a filling result cache region and a first interpolation result cache region, wherein the direct result cache region is used for storing data of pixel points which are to be directly output and are unrelated to background colors, the interpolation result cache region is used for storing data of pixel points needing interpolation correction, the filling result cache region is used for storing data of filling triangles, filling rectangles and filling circles, and the first interpolation result cache region is used for storing data of single-side anti-aliasing at the outer edge of a graph when anti-aliasing is performed on the filling triangles, the filling rectangles and the filling circles;
the video memory read-write control unit writes the result of the drawing of the primitive into the graphic video memory and reads data in the graphic video memory along with the graphic data read-out time sequence of the display superposition unit; the video memory read-write control unit performs interrupt arbitration and judgment on data write-in and read-out operations of a direct result buffer area, an interpolation result buffer area, a filling result buffer area and a first interpolation result buffer area, wherein the priority is graph read > direct result buffer area write > interpolation result buffer area write > filling result buffer area write > first interpolation result buffer area write; the graphic data reading time sequence is determined according to the video time sequence which needs to be output finally;
the ECC check unit is used for carrying out ECC check on the data written into the graphic display memory and the drawing data read out of the display memory by taking a data frame as a unit;
under the condition that the external video overlapping function is started, after the external video control unit caches input external video data in an external video memory, the display overlapping unit reads out external video pixel data from the external video control unit according to the time sequence read out by the graphic data, performs pixel level overlapping on the external video pixel data and the graphic data, and sends the external video pixel data and the graphic data to the display output adjusting unit; under the condition that the external video overlapping function is closed, the display overlapping unit directly sends the graphic data read from the graphic display memory to the display output adjusting unit;
and the display output adjusting unit adjusts and outputs the input data according to the set output video protocol.
2. The apparatus according to claim 1, wherein the apparatus for generating high frame rate and low delay pattern based on FPGA is further characterized in that: the setting command comprises parameter settings of graphic resolution, windowing, block areas, background color, opening and closing of a vertical synchronization function and opening and closing of an external video superposition function.
3. The apparatus according to claim 1, wherein the apparatus for generating high frame rate and low delay pattern based on FPGA is further characterized in that: the graphics command comprises a primitive type drawing instruction and a primitive drawing parameter; the primitive types comprise points, lines, circles, triangles, arcs and characters; the primitive drawing parameters comprise color and line width.
4. The apparatus according to claim 1, wherein the apparatus for generating high frame rate and low delay pattern based on FPGA is further characterized in that: the drawing command buffer unit comprises three levels of buffer units, wherein the first level of buffer unit is an instruction receiving storage unit, the second level of buffer unit is provided with two instruction buffer areas, and the third level of buffer unit is an instruction sending storage unit;
after the instruction receiving and storing unit receives a frame of drawing instruction, the drawing instruction is sequentially and alternately written into two instruction cache regions of the second-level buffer unit by taking the frame as a unit under the condition that the vertical synchronous instruction is opened; under the condition that the vertical synchronous instruction is closed, writing the drawing instruction into a certain specified instruction cache region in the second-level buffer unit by taking a frame as a unit;
for the first frame drawing instruction after being electrified, directly reading the first frame drawing instruction from the second-level buffer unit to an instruction sending storage unit; for the following drawing instruction, after receiving a drawing completion signal sent by the drawing unit, reading the drawing instruction from the second-level buffer unit to the instruction sending storage unit according to the following reading rule:
in case of vertical synchronization command on:
when data in the first instruction cache region are to be read, judging a flag1 signal, if the flag1 signal is valid, reading the data in the first instruction cache region, otherwise, continuously reading the data in the second instruction cache region; the flag1 signal indicates whether the first instruction buffer is written with data again after the data of the first instruction buffer is read last time, wherein if the data is written with the first instruction buffer again, the flag1 signal is valid, otherwise, the flag1 signal is invalid;
when data in the second instruction cache region are to be read, judging a flag2 signal, if the flag2 signal is valid, reading the data in the second instruction cache region, otherwise, continuously reading the data in the first instruction cache region; the flag2 signal indicates whether the second instruction buffer is written with data again after the data of the second instruction buffer is read last time, wherein if the data is written into the second instruction buffer again, the flag2 signal is valid, otherwise, the flag2 signal is invalid;
in case of vertical synchronization instruction off:
and directly reading the drawing instruction from the specified instruction cache region to the instruction sending storage unit.
5. The apparatus according to claim 1, wherein the apparatus for generating high frame rate and low delay pattern based on FPGA is further characterized in that: the drawing channels comprise a point drawing channel, a horizontal straight line drawing channel, a diagonal line drawing channel, a circular drawing channel, an arc drawing channel, a triangle filling drawing channel, a rectangle filling drawing channel, a circular filling drawing channel and a character drawing channel.
6. The apparatus according to claim 5, wherein the apparatus for generating high frame rate and low delay pattern based on FPGA comprises: besides character drawing, other graphic primitives are drawn in real time by an FPGA algorithm, and the character drawing is to read characters to be drawn from a character memory.
7. The apparatus according to claim 1, wherein the apparatus for generating high frame rate and low delay pattern based on FPGA is further characterized in that: the problem of reading and writing asynchronous complete frame data is solved by adopting a ping-pong cache mechanism in the graphic display memory.
8. The apparatus according to claim 1, wherein the apparatus for generating high frame rate and low delay pattern based on FPGA is further characterized in that: the formula for the display superimposing unit to perform pixel level superimposition is as follows:
R(x,y)＝(255-gray(x,y))*bg_R(x,y)/255；
G(x,y)＝(255-gray(x,y))*bg_G(x,y)/255；
B(x,y)＝(255-gray(x,y))*bg_B(x,y)/255；
wherein, gray represents the gray value of the graphic data, bg _ R, bg _ G, and bg _ B represent the gray value of the external video.
9. The apparatus according to claim 1, wherein the apparatus for generating high frame rate and low delay pattern based on FPGA is further characterized in that: the output timing adjusted by the display output adjusting unit comprises VESA timing, LVDS, digital RGB, ARINC818 timing.
10. The apparatus according to claim 1, wherein the apparatus for generating high frame rate and low delay pattern based on FPGA is further characterized in that: and after the frame check instruction is started in the setting instruction, the display output adjusting unit finishes CRC check of the whole frame output image, replaces the value of the last row and the last column of the output pixel point with a CRC check value, and transmits the value to a lower device to ensure the data safety of the transmission chain.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117077599A (en) * | 2023-09-18 | 2023-11-17 | 苏州异格技术有限公司 | Method and device for generating field programmable gate array view |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120176396A1 (en) * | 2011-01-11 | 2012-07-12 | Harper John S | Mirroring graphics content to an external display |
| CN103095997A (en) * | 2013-02-25 | 2013-05-08 | 袁琦睦 | Real-time picture-in-picture generating method based on field programmable gate array (FPGA) and device thereof |
| US20140366057A1 (en) * | 2013-06-06 | 2014-12-11 | Activevideo Networks, Inc. | Overlay Rendering of User Interface Onto Source Video |
| CN105426149A (en) * | 2015-11-10 | 2016-03-23 | 北京恒宇信通科技发展有限公司 | FPGA (Field Programmable Gate Array)-based graphic display card |
| CN105430303A (en) * | 2015-11-10 | 2016-03-23 | 北京恒宇信通科技发展有限公司 | Graphics accelerator based on FPGA in military airborne cockpit display system |
| CN108055478A (en) * | 2017-12-18 | 2018-05-18 | 天津津航计算技术研究所 | A kind of multi-channel video superposed transmission method based on FC-AV agreements |
| CN108280799A (en) * | 2017-01-06 | 2018-07-13 | 中航华东光电（上海）有限公司 | A kind of graphic generator and image generation method based on FPGA |
| CN110855907A (en) * | 2019-10-19 | 2020-02-28 | 中国航空工业集团公司洛阳电光设备研究所 | Low-delay video overlay frame buffer scheduler based on prediction |
-
2021
- 2021-10-07 CN CN202111167677.0A patent/CN114115720B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120176396A1 (en) * | 2011-01-11 | 2012-07-12 | Harper John S | Mirroring graphics content to an external display |
| CN103095997A (en) * | 2013-02-25 | 2013-05-08 | 袁琦睦 | Real-time picture-in-picture generating method based on field programmable gate array (FPGA) and device thereof |
| US20140366057A1 (en) * | 2013-06-06 | 2014-12-11 | Activevideo Networks, Inc. | Overlay Rendering of User Interface Onto Source Video |
| CN105426149A (en) * | 2015-11-10 | 2016-03-23 | 北京恒宇信通科技发展有限公司 | FPGA (Field Programmable Gate Array)-based graphic display card |
| CN105430303A (en) * | 2015-11-10 | 2016-03-23 | 北京恒宇信通科技发展有限公司 | Graphics accelerator based on FPGA in military airborne cockpit display system |
| CN108280799A (en) * | 2017-01-06 | 2018-07-13 | 中航华东光电（上海）有限公司 | A kind of graphic generator and image generation method based on FPGA |
| CN108055478A (en) * | 2017-12-18 | 2018-05-18 | 天津津航计算技术研究所 | A kind of multi-channel video superposed transmission method based on FC-AV agreements |
| CN110855907A (en) * | 2019-10-19 | 2020-02-28 | 中国航空工业集团公司洛阳电光设备研究所 | Low-delay video overlay frame buffer scheduler based on prediction |
Non-Patent Citations (1)
| Title |
|---|
| 王栋: "基于FPGA的飞机座舱综合显示系统关键技术研究", 中国优秀硕士学位论文全文数据库 工程科技Ⅱ辑 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117077599A (en) * | 2023-09-18 | 2023-11-17 | 苏州异格技术有限公司 | Method and device for generating field programmable gate array view |
| CN117077599B (en) * | 2023-09-18 | 2024-04-19 | 苏州异格技术有限公司 | Method and device for generating field programmable gate array view |
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|---|---|
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