CN114093294B - Pixel circuit, driving method thereof and display device - Google Patents

Abstract

The invention provides a pixel circuit, which comprises a driving transistor, a data writing sub-circuit, a first storage sub-circuit, a second storage sub-circuit and a first gating sub-circuit; the data writing sub-circuit, the driving transistor and the first storage sub-circuit are connected to a first node, the first storage sub-circuit, the second storage sub-circuit and the first gating sub-circuit are connected to a second node, and the data writing sub-circuit, the first gating sub-circuit and the driving transistor are connected to a third node; the data writing sub-circuit responds to the control of the first scanning signal end to conduct the first data signal end with the first node; switching on the second data signal terminal and the third node in response to control of the second scanning signal terminal; the first gating sub-circuit is used for conducting the second node and the third node in response to the control of the first gating signal terminal; the invention also provides a driving method of the pixel circuit and a display device.

Description

Pixel circuit, driving method thereof and display device

Technical Field

The invention relates to the technical field of display, in particular to a pixel circuit, a driving method thereof and a display device.

Background

At present, voltage Drop (IR Drop) exists in a pixel circuit, especially when a display panel displays a high-brightness picture, the voltage Drop is more obvious, and when a light-emitting control switch in the pixel circuit is turned on, the voltage Drop caused by instantaneous heavy current can reduce the voltage difference between two ends of a gate source of a driving transistor, so that the starting degree of the driving transistor is insufficient, and the uniformity of the overall brightness of the display panel is further affected.

Disclosure of Invention

The invention aims to at least solve one of the technical problems in the prior art, and provides a pixel circuit, a driving method thereof and a display device.

In order to achieve the above object, the present invention provides a pixel circuit including a driving transistor, wherein the pixel circuit has a first luminance mode and a second luminance mode, the pixel circuit further comprising: a reset sub-circuit, a data writing sub-circuit, a first storage sub-circuit, a second storage sub-circuit, a first strobe sub-circuit, a first light emitting control sub-circuit and a second light emitting control sub-circuit; the reset sub-circuit, the data writing sub-circuit, the gate of the driving transistor and the first end of the first storage sub-circuit are connected to a first node, the second end of the first storage sub-circuit, the first end of the second storage sub-circuit and the first gating sub-circuit are connected to a second node, and the data writing sub-circuit, the first gating sub-circuit, the first light emitting sub-circuit and the first pole of the driving transistor are connected to a third node;

the reset subcircuit is configured to: in response to control of the reset terminal, conducting a first signal terminal with the first node;

The data writing sub-circuit is configured to: in the first brightness mode, responding to the control of a first scanning signal end, and conducting a first data signal end with the first node; in the second brightness mode, responding to the control of a second scanning signal end, and conducting a second data signal end with the third node;

the first gating sub-circuit is configured to: in the first brightness mode, responding to the control of a first gating signal end, and conducting the second node and the third node; disconnecting the second node from the third node in the second brightness mode;

the first lighting control subcircuit is configured to: in response to control of the light emitting signal terminal, conducting the first voltage terminal with the third node;

the second light emission control sub-circuit is configured to: and responding to the control of the light-emitting signal terminal, and conducting the second electrode of the driving transistor with the light-emitting device.

Optionally, the pixel circuit further includes: a second gating sub-circuit;

the second gate sub-circuit is configured to turn on the second light emission control sub-circuit with the second signal terminal in response to control of the second gate signal terminal.

Optionally, the second gating sub-circuit includes: a second gating transistor;

the grid electrode of the second gating transistor is connected with the second gating signal end, the first electrode of the second gating transistor is connected with the second light-emitting control sub-circuit, and the second electrode of the second gating transistor is connected with the second signal end.

Optionally, the pixel circuit further includes: a compensation sub-circuit;

the compensation subcircuit is configured to: and responding to the control of the second scanning signal end, and conducting a second pole of the driving transistor with the first node.

Optionally, the compensation sub-circuit includes: a compensation transistor;

the grid electrode of the compensation transistor is connected with the second scanning signal end, the first electrode of the compensation transistor is connected with the second electrode of the driving transistor, and the second electrode of the compensation transistor is connected with the first node.

Optionally, the first gating sub-circuit includes a first gating transistor, a gate of the first gating transistor is connected to the first gating signal terminal, a first pole of the first gating transistor is connected to the third node, and a second pole of the first gating transistor is connected to the second node;

The first storage sub-circuit comprises a first capacitor, the second storage sub-circuit comprises a second capacitor, a first end of the first capacitor is connected with the first node, a second end of the first capacitor and a first end of the second capacitor are both connected with the second node, and a second end of the second capacitor is connected with the first voltage end;

the first light-emitting control sub-circuit comprises a first light-emitting control transistor, wherein a grid electrode of the first light-emitting control transistor is connected with the light-emitting signal end, a first electrode of the first light-emitting control transistor is connected with the first voltage end, and a second electrode of the first light-emitting control transistor is connected with the third node.

Optionally, the data writing sub-circuit includes a first writing transistor and a second writing transistor, where a gate of the first writing transistor is connected to the first scanning signal end, a first pole of the first writing transistor is connected to the first data signal end, a second pole of the first writing transistor is connected to the first node, a gate of the second writing transistor is connected to the second scanning signal end, a first pole of the second writing transistor is connected to the second data signal end, and a second pole of the second writing transistor is connected to the third node;

The second light-emitting control sub-circuit comprises a second light-emitting control transistor, wherein the grid electrode of the second light-emitting control transistor is connected with the light-emitting signal end, the first electrode of the second light-emitting control transistor is connected with the second electrode of the driving transistor, and the second electrode of the second light-emitting control transistor is connected with the light-emitting device;

the reset sub-circuit comprises a reset transistor, wherein a gate electrode of the reset transistor is connected with the reset end, a first electrode of the reset transistor is connected with the first signal end, and a second electrode of the reset transistor is connected with the first node.

The present invention also provides a display device, including: a light emitting device and the pixel circuit described above.

Optionally, the display device further includes a judging module configured to: and judging whether the pixel circuit is in a first brightness mode or a second brightness mode according to the gray scale of the image to be displayed.

The invention also provides a driving method of the pixel circuit, wherein the pixel circuit is the pixel circuit, and when the pixel circuit is in the first brightness mode, the driving method of the pixel circuit comprises the following steps:

In a reset stage, providing an effective level signal to the first gating signal terminal so that the first gating sub-circuit conducts the second node and the third node;

in a data writing stage, an invalid level signal is provided for the first gating signal terminal, and an effective level signal is provided for the first scanning signal terminal, so that the first gating sub-circuit disconnects the second node from the third node, and the data writing sub-circuit writes the data signal of the first data signal terminal into the first node;

when the pixel circuit is in the second brightness mode, the driving method of the pixel circuit includes:

in a reset stage, an invalid level signal is provided to the first gating signal terminal so that the first gating sub-circuit disconnects the second node from the third node;

and in the data writing stage, an invalid level signal is provided for the first gating signal terminal, and an effective level signal is provided for the second scanning signal terminal, so that the data writing sub-circuit writes the data signal of the second data signal terminal into the third node.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate the invention and together with the description serve to explain, without limitation, the invention. In the drawings:

FIG. 1a is a schematic diagram of a conventional pixel circuit;

FIG. 1b is a timing diagram of a conventional pixel circuit;

fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 3a is a driving timing chart of a pixel circuit according to an embodiment of the present invention in a first brightness mode;

FIG. 3b is a driving timing chart of the pixel circuit according to the embodiment of the invention in the second brightness mode;

FIG. 3c is a driving timing chart of the pixel circuit according to the embodiment of the invention;

FIG. 4a is an equivalent circuit diagram of a pixel circuit in a first brightness mode according to an embodiment of the present invention;

FIG. 4b is a diagram illustrating an equivalent circuit of the pixel circuit in the second brightness mode according to the embodiment of the present invention;

fig. 5 is a schematic diagram of a judging module according to an embodiment of the present invention.

Detailed Description

The following describes specific embodiments of the present invention in detail with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.

Unless defined otherwise, technical or scientific terms used in the embodiments of the present invention should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present invention belongs. The terms "first," "second," and the like, as used herein, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

Micro LEDs (Micro light emitting diodes) are technologies which are used for transferring the addressing huge quantity to a circuit substrate after the traditional LEDs are arrayed and miniaturized to form ultra-small-space LEDs, and further shrinking the length of the millimeter-level LEDs to the micrometer level so as to achieve ultra-high pixels and ultra-high resolution, and can be theoretically suitable for screens with various sizes. The Micro LED has the advantages of high efficiency, high brightness, high resolution, long service life, low power consumption and the like, and is currently becoming a serious issue for various enterprises and high-efficiency researches at home and abroad.

The typical Micro LED structure is a PN junction diode, which is made of a direct bandgap semiconductor material, and when a forward bias is applied to the upper and lower electrodes of the Micro LED, electrons and holes recombine with respect to the active region and emit monochromatic light when a current is passed. The driving mode of Micro LED display is current driving, and specifically, the driving current can be improved for the Micro LED through a pixel circuit.

Fig. 1a is a schematic structural diagram of a conventional pixel circuit, as shown in fig. 1a, the conventional pixel circuit includes: the first reset transistor M1', the compensation transistor M2', the driving transistor M3', the data writing transistor M4', the first light emitting control transistor M5', the second light emitting control transistor M6', the second reset transistor M7', and the first capacitor C1'. The gate of the first Reset transistor M1 'is connected to the Reset terminal Reset', the first pole of the first Reset transistor M1 'is connected to the first signal terminal Vint', and the second pole of the first Reset transistor M1 'is connected to the first node N1'. The Gate of the compensation transistor M2 'is connected to the scan terminal Gate', the first pole of the compensation transistor M2 'is connected to the second pole of the driving transistor M3', and the second pole of the compensation transistor M2 'is connected to the first node N1'. The gate of the driving transistor M3 'is connected to the first node N1', the first pole of the driving transistor M3 'is connected to the first voltage terminal Vdd', and the second pole of the driving transistor M3 'is connected to the first pole of the second light emission control transistor M6'. The Gate of the Data writing transistor M4 'is connected to the scan terminal Gate', the first electrode of the Data writing transistor M4 'is connected to the Data signal terminal Data', and the second electrode of the Data writing transistor M4 'is connected to the second node N2'. The gate of the first light emitting control transistor M5 'is connected to the light emitting control terminal EM', the first pole of the first light emitting control transistor M5 'is connected to the second signal terminal Vref', and the second pole of the first light emitting control transistor M5 'is connected to the second node N2'. The gate of the second light emission control transistor M6 'is connected to the light emission control terminal EM', the second electrode of the second light emission control transistor M6 'is connected to the first electrode of the light emitting device L', and the second electrode of the light emitting device L 'is connected to the second voltage terminal Vss'. The gate of the second Reset transistor M7 'is connected to the Reset terminal Reset', the first pole of the second Reset transistor M7 'is connected to the second signal terminal Vref', and the second pole of the second Reset transistor M7 'is connected to the second node N2'. One end of the first capacitor C1' is connected to the first node N1', and the other end is connected to the second node N2 '.

Fig. 1b is a timing chart of a conventional pixel circuit, as shown in fig. 1b, in a Reset phase T1', an active level signal is provided to a Reset terminal Reset', and both the first Reset transistor M1 'and the second Reset transistor M7' are turned on, at this time, the voltage of the first node N1 'is V1', the voltage of the second node N2 'is V2', where V1 'is the voltage of the first signal terminal Vint', and V2 'is the voltage of the second signal terminal Vref'.

In the Data writing period T2', an invalid level signal is provided to the Reset terminal Reset', an valid level signal is provided to the scan terminal Gate ', the first Reset transistor M1' and the second Reset transistor M7 'are turned off, the compensation transistor M2' and the Data writing transistor M4 'are turned on, at this time, the voltage of the first node N1' is V3'+vth', the voltage of the second node N2 'is V4', where V3 'is the voltage of the first voltage terminal Vdd', vth 'is the threshold voltage of the driving transistor M3', and V4 'is the voltage of the Data signal terminal Data'.

In the emission control period T3', an inactive level signal is provided to the scan terminal Gate', an active level signal is provided to the emission control terminal EM ', both the compensation transistor M2' and the data writing transistor M4 'are turned off, both the first emission control transistor M5' and the second emission control transistor M6 'are turned on, and at this time, the voltage of the first node N1' is V3'+vth' +v2'-V4', and the voltage of the second node N2 'is V2'. The driving transistor M3 'supplies a driving current I, i=1/2*k (V3' +vth '+v2' -v4'-v2' -Vth ') ∈2=1/2*k (V3' -V4 ') ∈2, where k is a constant, to the light emitting device L' according to a voltage difference between the first node N1 'and the second node N2'.

In the conventional pixel circuit, when the second light emission control transistor M6 'is turned on, the first voltage terminal Vdd' is turned on with the light emitting device L ', the instantaneous current fluctuation will cause a voltage drop on the line between the first voltage terminal Vdd' and the light emitting device L ', especially when a high brightness picture is displayed, the voltage drop is very obvious, and the voltage drop on the line will cause the voltage of the first pole of the driving transistor M3' to be lower than the target voltage, so that the voltage difference between the gate (i.e., the first node N1 ') and the first pole of the driving transistor M3' is reduced, thereby causing the insufficient turn-on degree of the driving transistor M3', and the light emitting device L' cannot reach the target brightness.

In view of the foregoing, an embodiment of the present invention provides a pixel circuit, and fig. 2 is a schematic structural diagram of the pixel circuit according to the embodiment of the present invention, where the pixel circuit has a first luminance mode and a second luminance mode. As shown in fig. 2, the pixel circuit includes a driving transistor M1, a reset sub-circuit 21, a data writing sub-circuit 22, a first memory sub-circuit 23, a second memory sub-circuit 24, a first gate sub-circuit 25, a first light emission control sub-circuit 26, and a second light emission control sub-circuit 27. The reset sub-circuit 21, the data writing sub-circuit 22, the gate of the driving transistor M1 and the first terminal of the first memory sub-circuit 23 are connected to the first node N1, the second terminal of the first memory sub-circuit 23, the first terminal of the second memory sub-circuit 24 and the first gate sub-circuit 25 are connected to the second node N2, and the data writing sub-circuit 22, the first gate sub-circuit 25, the first light emitting sub-circuit 26 and the first pole of the driving transistor M1 are connected to the third node N3.

Wherein the reset sub-circuit 21 is configured to: in response to the control of the Reset terminal Reset, the first signal terminal Vref is turned on with the first node N1, thereby resetting the first node N1. The data write sub-circuit 22 is configured to: in the first brightness mode, the first Data signal terminal Data1 is turned on with the first node N1 in response to the control of the first scan signal terminal Gata1, so that the Data signal of the first Data signal terminal Data1 is written into the first node N1. In the second brightness mode, the second Data signal terminal Data2 is turned on with the third node N3 in response to the control of the second scan signal terminal Gata2, so that the Data signal of the second Data signal terminal Data2 is written into the third node N3. The first gating sub-circuit 25 is configured to: in the first brightness mode, the second node N2 is turned on with the third node N3 in response to the control of the first gate signal terminal GM, and in the second brightness mode, the second node N2 is turned off with the third node N3. The first light emitting control sub-circuit 26 is configured to: the first voltage terminal Vdd is turned on with the third node N3 in response to the control of the light emitting signal terminal EM. The second light emission control sub-circuit 27 is configured to: in response to the control of the light emitting signal terminal EM, the second electrode of the driving transistor M1 is turned on with the light emitting device L. The light emitting device L may be a light emitting diode, for example, a micro-LED.

In the embodiment of the present invention, the first luminance mode may refer to an operation mode of the pixel circuit when the overall luminance of the image to be displayed is high (for example, the luminance is 4000nits to 8000 nits), and the second luminance mode may refer to an operation mode of the pixel circuit when the overall luminance of the image to be displayed is low (for example, the luminance is 0nits to 1500 nits). The duty cycle of the pixel circuit includes: a reset phase, a data writing phase and a light emitting phase. The operation of the pixel circuit according to the embodiment of the present invention will be described below.

When the pixel circuit is in the second brightness mode, the first gate signal terminal GM is supplied with the inactive level signal to cause the first gate sub-circuit 25 to disconnect the second node N2 from the third node N3.

In the Reset phase, an active level signal may be supplied to the Reset terminal Reset to cause the Reset sub-circuit 21 to turn on the first signal terminal Vref with the first node N1. At this time, the first storage sub-circuit 23 and the second storage sub-circuit 24 are connected in series, and the reference voltage of the first signal terminal Vref is transmitted to the first node N1.

In the Data writing stage, an active level signal may be provided to the second scan signal terminal Gata2 to enable the Data writing sub-circuit 22 to turn on the second Data signal terminal Data2 and the third node N3. At this time, the Data voltage of the second Data signal terminal Data2 can be transmitted to the first node N1 through the driving transistor M1.

In the light emitting stage, an active level signal may be provided to the light emitting signal terminal EM to cause the first light emitting control sub-circuit 26 to turn on the first voltage terminal Vdd and the third node N3, and the second light emitting control sub-circuit 27 to turn on the second electrode of the driving transistor M1 and the light emitting device L. At this time, the voltage of the first voltage terminal Vdd is transmitted to the third node N3, and the driving transistor M1 supplies the driving current to the light emitting device L according to the voltage difference between the first node N1 and the third node N3.

The reset phase may include a first sub-phase and a second sub-phase when the pixel circuit is in the first brightness mode.

In the first sub-stage, an active level signal may be provided to the light emitting signal section EM and an active level signal may be provided to the first gate signal terminal GM to cause the first light emitting control sub-circuit 26 to conduct the first voltage terminal Vdd to the third node N3, and the first gate sub-circuit 25 to conduct the second node N2 to the third node N3 to thereby transmit the voltage of the first voltage terminal Vdd to the second node N2.

In the second sub-stage, an inactive level signal may be provided to the light emitting signal terminal EM, at this time, the driving transistor M1 leaks electricity until the voltage difference between the first node N1 and the third node N3 turns off the driving transistor M1, so that the voltage difference between the first node N1 and the third node N3 is equal to the threshold voltage of the driving transistor M1, the voltage of the second node N2 is equal to the voltage of the third node N3, and the voltage difference between the first node N1 and the second node N2 is also equal to the threshold voltage of the driving transistor M1.

In the Data writing stage, an active level signal may be provided to the first scan signal terminal Gata1 to cause the Data writing sub-circuit 22 to write the Data signal of the first Data signal terminal Data1 to the first node N1. The first gate signal terminal GM is supplied with an inactive level signal to cause the first gate sub-circuit 25 to disconnect the second node N2 from the third node N3. At this time, the first storage sub-circuit 23 is connected in series with the second storage sub-circuit 24, the voltage of the second node N2 jumps with the first node N1, and the voltage magnitude of the second node N2 after the jump is related to the storage capacities of the first storage sub-circuit 23 and the second storage sub-circuit 24.

In the light emitting stage, an active level signal may be provided to the light emitting signal terminal EM to cause the first light emitting control sub-circuit 26 to turn on the first voltage terminal Vdd and the third node N3, and the second light emitting control sub-circuit 27 to turn on the second electrode of the driving transistor M1 and the light emitting device L. The first gate signal terminal GM is supplied with an active level signal to cause the first gate sub-circuit 25 to turn on the second node N2 and the third node N3. At this time, the voltage of the first voltage terminal Vdd is transmitted to the second node N2 and the third node N3, and the voltage of the first node N1 jumps with the second node N2. Since the voltage level of the second node N2 is related to the storage capacities of the first and second storage sub-circuits 23 and 24 in the data writing stage, the voltage level after the first node N1 jumps in the light emitting stage is also related to the storage capacities of the first and second storage sub-circuits 23 and 24. Therefore, the voltage of the first node N1 in the light emitting stage can be adjusted by reasonably setting the storage capacities of the first storage sub-circuit 23 and the second storage sub-circuit 24, so as to increase the voltage difference between the first node N1 and the third node N3, thereby improving the problem of insufficient turn-on of the driving transistor M1.

In summary, by adopting the pixel circuit of the embodiment of the invention, the switching between the low-brightness working mode and the high-brightness working mode can be performed, and when the brightness of the picture to be displayed is lower, the pixel circuit can be switched to the second brightness mode so as to reduce the power consumption; when the brightness of the picture to be displayed is higher, the pixel circuit can be switched to the first brightness mode, so that when the voltage of the first pole of the driving transistor M1 is influenced by the voltage drop on the circuit, the driving transistor M1 can still be normally turned on, and the problem that the light emitting device L cannot reach the target brightness due to insufficient turning-on degree of the driving transistor M1 is avoided.

The specific structure of the pixel circuit provided in the embodiment of the present invention is described below with reference to fig. 2 to 4b, and it should be noted that the transistor in the embodiment of the present invention may be a thin film transistor or a field effect transistor or other switching devices with the same characteristics. Transistors generally comprise three poles: the gate, source and drain, the source and drain in the transistor are symmetrical in structure, and the two are interchangeable as desired. In an embodiment of the present invention, one of the first pole and the second pole is a source and the other is a drain.

Further, the transistors can be classified into N-type transistors and P-type transistors according to transistor characteristics. In the present invention, "active level signal" (or "active level potential") means a voltage signal (or potential) capable of controlling the turn-on of the corresponding transistor, and "inactive level signal" (or "inactive level potential") means a voltage signal (or potential) capable of controlling the turn-off of the corresponding transistor; therefore, when the transistor is an N-type transistor, the active level signal means a high level signal and the inactive level signal means a low level signal; when the transistor is a P-type transistor, the active level signal is a low level signal, and the inactive level signal is a high level signal. The embodiment of the invention is described by taking a transistor as a P-type transistor as an example.

In some embodiments, the pixel circuit further comprises: a second gating sub-circuit 28. The second gate sub-circuit 28 is configured to turn on the second light emission control sub-circuit 27 with the second signal terminal Data3 in response to the control of the second gate signal terminal Test.

In some embodiments, the second gating sub-circuit 28 includes: and a second gating transistor M3. The gate of the second gating transistor M3 is connected to the second gating signal terminal Test, the first pole of the second gating transistor M3 is connected to the second emission control sub-circuit 27, and the second pole of the second gating transistor M3 is connected to the second signal terminal Data 3.

In some embodiments, the pixel circuit further comprises: the compensation sub-circuit 29. The compensation sub-circuit 29 is configured to: in response to the control of the second scan signal terminal Gata2, the second pole of the driving transistor M1 is turned on with the first node N1.

In some embodiments, the compensation subcircuit 29 includes: compensating transistor M4. The gate of the compensation transistor M4 is connected to the second scan signal terminal Gata2, the first pole of the compensation transistor M4 is connected to the second pole of the driving transistor M1, and the second pole of the compensation transistor M4 is connected to the first node N1.

In some embodiments, the first gating sub-circuit 25 includes a first gating transistor M2, the gate of the first gating transistor M2 is connected to the first gating signal terminal GM, the first pole of the first gating transistor M2 is connected to the third node N3, and the second pole of the first gating transistor M2 is connected to the second node N2. The first storage sub-circuit 23 includes a first capacitor C1, the second storage sub-circuit 24 includes a second capacitor C2, a first end of the first capacitor C1 is connected to the first node N1, a second end of the first capacitor C1 and a first end of the second capacitor C2 are both connected to the second node N2, and a second end of the second capacitor C2 is connected to the first voltage terminal Vdd. The first light emitting control sub-circuit 26 includes a first light emitting control transistor M5, a gate electrode of the first light emitting control transistor M5 is connected to the light emitting signal terminal EM, a first electrode of the first light emitting control transistor M5 is connected to the first voltage terminal Vdd, and a second electrode of the first light emitting control transistor M5 is connected to the third node N3.

In some embodiments, the Data writing sub-circuit 22 includes a first writing transistor M7 and a second writing transistor M8, the gate of the first writing transistor M7 is connected to the first scan signal terminal Gata1, the first pole of the first writing transistor M7 is connected to the first Data signal terminal Data1, the second pole of the first writing transistor M7 is connected to the first node N1, the gate of the second writing transistor M8 is connected to the second scan signal terminal Gata2, the first pole of the second writing transistor M8 is connected to the second Data signal terminal Data2, and the second pole of the second writing transistor M8 is connected to the third node N3. The second emission control sub-circuit 27 includes a second emission control transistor M6, a gate of the second emission control transistor M6 is connected to the emission signal terminal EM, a first electrode of the second emission control transistor M6 is connected to a second electrode of the driving transistor M1, and a second electrode of the second emission control transistor M6 is connected to the light emitting device L. The Reset sub-circuit 21 includes a Reset transistor M9, a gate of the Reset transistor M9 is connected to the Reset terminal Reset, a first pole of the Reset transistor M9 is connected to the first signal terminal Vref, and a second pole of the Reset transistor M9 is connected to the first node N1.

Fig. 3a is a driving timing diagram when the pixel circuit provided in the embodiment of the present invention is in the first luminance mode, fig. 3b is a driving timing diagram when the pixel circuit provided in the embodiment of the present invention is in the second luminance mode, fig. 3c is a driving timing diagram when the pixel circuit provided in the embodiment of the present invention performs detection, fig. 4a is an equivalent circuit diagram when the pixel circuit provided in the embodiment of the present invention is in the first luminance mode, and fig. 4b is an equivalent circuit diagram when the pixel circuit provided in the embodiment of the present invention is in the second luminance mode. Table 1a is a table of operating states of transistors when the pixel circuit provided in the embodiment of the present invention is in the first luminance mode, table 1b is a table of voltages when the pixel circuit provided in the embodiment of the present invention is in the first luminance mode, table 2a is a table of operating states of transistors when the pixel circuit provided in the embodiment of the present invention is in the second luminance mode, table 2b is a table of voltages when the pixel circuit provided in the embodiment of the present invention is in the second luminance mode, table 3a is a table of operating states of transistors when the pixel circuit provided in the embodiment of the present invention is detected, table 3b is a table of voltages when the pixel circuit provided in the embodiment of the present invention is detected, and the operation process of the pixel circuit according to the embodiment of the present invention is described below with reference to fig. 3a to fig. 4b and table 1a to table 3 b.

As shown in fig. 3a, 4a, table 1a and table 1b, when the pixel circuit is in the first brightness mode, the reset phase T1 includes a first sub-phase T1a and a second sub-phase T1b.

In the first sub-stage T1a, an active level signal is provided to the Reset terminal Reset, an active level signal is provided to the first gate signal terminal GM, and an active level signal is provided to the emission control terminal EM, at this time, the Reset transistor M9, the first gate transistor M2, the first emission control transistor M5, and the second emission control transistor M6 are all turned on, the voltage at the node N1 is V1, the voltage at the node N2 is V2, and the voltage at the node N3 is V2, where V1 is the reference voltage provided by the first signal terminal Vref, and V2 is the voltage provided by the first voltage terminal Vdd.

In the second sub-stage T1b, an inactive level signal is provided to the light emitting signal terminal EM, at this time, the first light emitting control transistor M5 and the second light emitting control transistor M6 are both turned off, the voltage of the node N1 is V1, the driving transistor M1 leaks electricity until the voltage of the third node N3 is V1-vth_m1, and the second node N2 is turned on with the third node N3, so that the voltage of the second node N2 is also V1-vth_m1, where vth_m1 is the threshold voltage of the driving transistor M1.

In the Data writing stage T2, an active level signal is provided to the first scan signal terminal Gate1, an inactive level signal is provided to the first Gate signal terminal GM, and an inactive level signal is provided to the Reset terminal Reset, at this time, the first write transistor M7 is turned on, the first Gate transistor M2 and the Reset transistor M9 are both turned off, the voltage of the node N1 is V3, the voltage of the node N2 is V1-vth_m1+c (V3-V1), the voltage of the node N3 is V1-vth_m1, where V3 is the voltage of the first Data signal terminal Data1, c=c2 '/(c1 ' +c2 '), C1' is the capacitance value of the first capacitor C1, and C2' is the capacitance value of the second capacitor C2.

In the light emitting stage T3, an effective level signal is provided to the light emitting signal terminal EM, and an effective level signal is provided to the first gate signal terminal GM, at this time, the first gate transistor M2, the first light emitting control transistor M5 and the second light emitting control transistor M6 are all turned on, the first node N1 has a node voltage of v3+v2- (v1—vth_m1+c (V3-V1)), the second node N2 has a voltage of V2, and the third node N3 has a voltage of V2, so that the gate voltage of the driving transistor M1 is v3+v2- (v1—vth_m1+c (V3-V1)), the first pole voltage of the driving transistor M1 is V2, and the driving current i=k/2 (v3+v2- (v1—vth_m1+c (V3-V1)) -v2=k/2 ((1-C)) ((V3-V1))2), wherein k is V1, so that the driving current M1 is a threshold voltage of the driving transistor is compensated for the threshold voltage of the driving transistor M1.

In the embodiment of the present invention, in the light emitting stage T3 of the first luminance mode, the gate voltage of the driving transistor M1 is v3+v2- (V1-vth_m1+c (V3-V1)), where c=c2 '/(C1 ' +c2 '), so that the gate voltage of the driving transistor M1 is related to the capacitance values of the first capacitor C1 and the second capacitor C2, the capacitance values of the first capacitor C1 and the second capacitor C2 can be reasonably set to adjust the magnitude of the gate voltage of the driving transistor M1 in the light emitting stage T3, for example, when (V3-V1) is negative, the capacitance value of the second capacitor C2 can be increased, so that the voltage of the gate of the driving transistor M1 is sufficiently low, and the driving transistor M1 can still be normally turned on when the voltage of the first pole of the driving transistor M1 is reduced due to the voltage drop on the line, so that the light emitting device L can reach the target luminance.

As shown in fig. 3b, 4b, table 2a and table 2b, when the pixel circuit is in the second brightness mode, the first gate signal terminal GM is supplied with the inactive level signal to turn off the first gate transistor M2.

In the Reset phase T1, an active level signal is provided to the Reset terminal Reset, at this time, the Reset transistor M9 is turned on, and the voltage at the first node N1 is V4, where V4 is the reference voltage provided by the first signal terminal Vref.

In the Data writing stage T2, an active level signal is provided to the second scan signal terminal Gate2, and an inactive level signal is provided to the Reset terminal Reset, at this time, the Reset transistor M9 is turned off, both the second writing transistor M8 and the compensation transistor M4 are turned on, and the voltage of the first node N1 is v5+vth_m1, where V5 is the Data voltage provided by the second Data signal terminal Data 2.

In the light emitting stage T3, an active level signal is provided to the light emitting signal terminal EM, an inactive level signal is provided to the second scanning signal terminal Gate2, at this time, both the first light emitting control transistor M5 and the second light emitting control transistor M6 are turned on, both the second writing transistor M8 and the compensating transistor M4 are turned off, the voltage of the first node N1 is v5+vth_m1, and the voltage of the third node N3 is V6. Therefore, the gate voltage of the driving transistor M1 is v5+vth_m1, the first pole voltage of the driving transistor M1 is V6, and the driving current i=k/2 (v5+vth_m1-v6-vth_m1)/(2=k/2 (V5-V6)/(2) provided by the driving transistor M1 compensates the threshold voltage of the driving transistor M1, wherein V6 is the voltage provided by the first voltage terminal Vdd.

In some embodiments, the second signal terminal Data3 may be connected to a detecting device for detecting the current passing through the driving transistor M1, the first light emitting control transistor M5 and the second light emitting control transistor M6, so as to determine whether the device on the line between the first voltage terminal Vdd and the second voltage terminal Vss is damaged; in addition, the driving current can be better compensated according to the detected current.

As shown in fig. 3c, table 3a and table 3b, the pixel circuit is tested including a first test stage Tx, a second test stage Ty and a third test stage Ty. In the first detection stage Tx, an active level signal is provided to the Reset terminal Reset, at this time, the Reset transistor M9 is turned on, and the voltage at the first node N1 is V7, where V7 is the reference voltage provided by the first signal terminal Vref.

In the second detection stage Ty, an inactive level signal is provided to the Reset terminal Reset and an active level signal is provided to the emission control terminal EM, at this time, the Reset transistor M9 is turned off, and the first emission control transistor M5 and the second emission control transistor M6 are both turned on, and the detection device detects the current passing through the driving transistor M1, the first emission control transistor M5, and the second emission control transistor M6.

In the third detection stage Tz, an invalid level signal is provided to the emission control terminal EM, and at this time, both the first emission control transistor M5 and the second emission control transistor M6 are turned off, and the detection device performs processing analysis on the detected current, so as to determine whether there is a damage to a device on a line between the first voltage terminal Vdd and the second voltage terminal Vss.

In other embodiments, the second signal terminal Data3 may be connected to the reset signal terminal, as shown in fig. 3b, table 2a and table 2b, and the active level signal is provided to the second gate signal terminal Test in the reset phase T1, at this time, the second gate transistor M3 is turned on, so as to reset the potential of one terminal of the light emitting device L.

TABLE 1a

Transistor/stage	T1a	T1b	T2	T3
					M2	Opening the valve	Opening the valve	Cut-off	Opening the valve
M3	Cut-off	Cut-off	Cut-off	Cut-off
					M4	Cut-off	Cut-off	Cut-off	Cut-off
M5	Opening the valve	Cut-off	Cut-off	Opening the valve
					M6	Opening the valve	Cut-off	Cut-off	Opening the valve
M7	Cut-off	Cut-off	Opening the valve	Cut-off
					M8	Cut-off	Cut-off	Cut-off	Cut-off
M9	Opening the valve	Opening the valve	Cut-off	Cut-off

TABLE 1b

TABLE 2a

Transistor/stage	T1	T2	T3
				M2	Cut-off	Cut-off	Cut-off
M3	Cut-off	Cut-off	Cut-off
				M4	Cut-off	Opening the valve	Cut-off
M5	Cut-off	Cut-off	Opening the valve
				M6	Cut-off	Cut-off	Opening the valve
M7	Cut-off	Cut-off	Cut-off
				M8	Cut-off	Opening the valve	Cut-off
M9	Opening the valve	Cut-off	Cut-off

TABLE 2b

Node/phase	T1	T2	T3
				N1	-3	V5+Vth_M1	V5+Vth_M1
Vdd	8v	8v	8v
				Vss	-3	-3	-3
Data1	-	V7	-
				Data2	0	0	0
Data3	-3	-3	-3
				Vref	-3	-3	-3
Gate1	5	5	5
				Gate2	5	-5	5
Test	5	-5	5
				Reset	-5	5	5
EM	5	5	-5
				GM	5	5	5

TABLE 3a

Transistor/stage	T1	T2	T3
				M1	Opening the valve	Opening the valve	Cut-off
M2	Cut-off	Cut-off	Cut-off
				M3	Cut-off	Opening the valve	Cut-off
M4	Cut-off	Cut-off	Cut-off
				M5	Cut-off	Opening the valve	Cut-off
M6	Cut-off	Opening the valve	Cut-off
				M7	Cut-off	Cut-off	Cut-off
M8	Cut-off	Cut-off	Cut-off
				M9	Opening the valve	Cut-off	Cut-off

TABLE 3b

The embodiment of the invention also provides a display device, which comprises: a light emitting device and the pixel circuit described above.

The display device may be: electronic paper, OLED panel, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc.

By adopting the display device provided by the embodiment of the invention, the pixel circuit can be switched between the low-brightness working mode and the high-brightness working mode, and when the brightness of a picture to be displayed is higher, the problem that the light emitting device cannot reach the target brightness due to insufficient opening degree of the driving transistor can be avoided, so that the display uniformity of the display device is improved.

Fig. 5 is a schematic diagram of a judging module provided in an embodiment of the present invention, as shown in fig. 5, in some embodiments, the display device further includes a judging module 3, where the judging module 3 is configured to: and judging whether the pixel circuit is in a first brightness mode or a second brightness mode according to the gray scale of the image to be displayed.

The judging module 3 includes a first detecting sub-module 31, a second detecting sub-module 32, and a judging sub-module 33, where the first detecting module 31 can judge whether the average gray level meets a first preset condition according to the average gray level of all pixels in the image to be displayed, for example, the first preset condition is: the average gray scale of each pixel of the picture to be displayed is greater than 64. The second detection module may determine whether the brightness uniformity satisfies a second preset condition according to brightness uniformity of all pixels in the frame to be displayed, for example, the second preset condition is: the brightness uniformity of the picture to be displayed is greater than 2. The judging module 33 is configured to judge whether the pixel circuit is in the first luminance mode or the second luminance mode according to the judging results of the first detecting module and the second detecting module, and determine that the pixel circuit is in the first luminance mode when the average gray level satisfies the first preset condition and/or the luminance uniformity satisfies the second preset condition. In the embodiment of the invention, the average gray level of a part of brighter pixels (for example, the pixels with the brightness of 10% at the front) and the average gray level of a part of darker pixels (for example, the pixels with the darkness of 20% at the front) in the image to be displayed can be calculated, and the ratio of the difference value of the two to the average gray level of all pixels is taken as the brightness uniformity.

In summary, in the embodiment of the present application, the pixel circuit in the display device may be switched between the first luminance mode and the second luminance mode according to the luminance of the image to be displayed, for example, when the display device performs indoor display, the image to be displayed may be displayed with lower luminance due to less interference of ambient light in the indoor environment, and at this time, the pixel circuit in the display device may be in the second luminance mode, and the second luminance mode may be controlled with lower voltage, so that the power consumption of the display device may be reduced. When the display device is used for outdoor display, the image to be displayed can be displayed with higher brightness due to larger influence of external environment light, and the pixel circuit can improve the problem of insufficient starting of the driving transistor, so that the display device can still keep good display uniformity even if the display device is used for displaying with higher brightness.

The embodiment of the application also provides a driving method of the pixel circuit, wherein the pixel circuit is the pixel circuit, and when the pixel circuit is in the first brightness mode, the driving method of the pixel circuit comprises the following steps:

In the reset stage, an active level signal is provided to the first strobe signal terminal so that the first strobe sub-circuit conducts the second node with the third node.

In the data writing stage, an invalid level signal is provided for the first strobe signal end, and an effective level signal is provided for the first scanning signal end, so that the first strobe sub-circuit disconnects the second node from the third node, and the data writing sub-circuit conducts the first data signal end with the first node.

When the pixel circuit is in the second brightness mode, the driving method of the pixel circuit includes:

an inactive level signal is provided to the first strobe signal terminal to cause the first strobe sub-circuit to disconnect the second node from the third node.

In the data writing stage, an active level signal is provided to the second scanning signal end so that the data writing sub-circuit conducts the second data signal end with the third node.

By adopting the driving method of the embodiment of the invention, the pixel circuit can be switched between two working modes of low brightness and high brightness, and when the brightness of the picture to be displayed is higher, the problem that the light-emitting device cannot reach the target brightness due to insufficient opening degree of the driving transistor can be avoided.

It is to be understood that the above embodiments are merely illustrative of the application of the principles of the present invention, but not in limitation thereof. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the invention, and are also considered to be within the scope of the invention.

Claims (10)

1. A pixel circuit comprising a drive transistor, wherein the pixel circuit has a first luminance mode and a second luminance mode, the pixel circuit further comprising: a reset sub-circuit, a data writing sub-circuit, a first storage sub-circuit, a second storage sub-circuit, a first strobe sub-circuit, a first light emitting control sub-circuit and a second light emitting control sub-circuit; the reset sub-circuit, the data writing sub-circuit, the gate of the driving transistor and the first end of the first storage sub-circuit are connected to a first node, the second end of the first storage sub-circuit, the first end of the second storage sub-circuit and the first gating sub-circuit are connected to a second node, and the data writing sub-circuit, the first gating sub-circuit, the first light emitting sub-circuit and the first pole of the driving transistor are connected to a third node;

the reset subcircuit is configured to: in response to control of the reset terminal, conducting a first signal terminal with the first node;

the data writing sub-circuit is configured to: in the first brightness mode, responding to the control of a first scanning signal end, and conducting a first data signal end with the first node; in the second brightness mode, responding to the control of a second scanning signal end, and conducting a second data signal end with the third node;

The first gating sub-circuit is configured to: in the first brightness mode, responding to the control of a first gating signal end, and conducting the second node and the third node; disconnecting the second node from the third node in the second brightness mode;

the first lighting control subcircuit is configured to: in response to control of the light emitting signal terminal, conducting the first voltage terminal with the third node;

the second light emission control sub-circuit is configured to: and responding to the control of the light-emitting signal terminal, and conducting the second electrode of the driving transistor with the light-emitting device.

2. The pixel circuit of claim 1, wherein the pixel circuit further comprises: a second gating sub-circuit;

the second gate sub-circuit is configured to turn on the second light emission control sub-circuit with the second signal terminal in response to control of the second gate signal terminal.

3. The pixel circuit of claim 2, wherein the second gating sub-circuit comprises: a second gating transistor;

the grid electrode of the second gating transistor is connected with the second gating signal end, the first electrode of the second gating transistor is connected with the second light-emitting control sub-circuit, and the second electrode of the second gating transistor is connected with the second signal end.

4. The pixel circuit of claim 1, wherein the pixel circuit further comprises: a compensation sub-circuit;

the compensation subcircuit is configured to: and responding to the control of the second scanning signal end, and conducting a second pole of the driving transistor with the first node.

5. The pixel circuit of claim 4, wherein the compensation sub-circuit comprises: a compensation transistor;

the grid electrode of the compensation transistor is connected with the second scanning signal end, the first electrode of the compensation transistor is connected with the second electrode of the driving transistor, and the second electrode of the compensation transistor is connected with the first node.

6. The pixel circuit according to any one of claims 1 to 5, wherein,

the first gating sub-circuit comprises a first gating transistor, wherein the grid electrode of the first gating transistor is connected with the first gating signal end, the first electrode of the first gating transistor is connected with the third node, and the second electrode of the first gating transistor is connected with the second node;

the first storage sub-circuit comprises a first capacitor, the second storage sub-circuit comprises a second capacitor, a first end of the first capacitor is connected with the first node, a second end of the first capacitor and a first end of the second capacitor are both connected with the second node, and a second end of the second capacitor is connected with the first voltage end;

The first light-emitting control sub-circuit comprises a first light-emitting control transistor, wherein a grid electrode of the first light-emitting control transistor is connected with the light-emitting signal end, a first electrode of the first light-emitting control transistor is connected with the first voltage end, and a second electrode of the first light-emitting control transistor is connected with the third node.

7. The pixel circuit according to any one of claims 1 to 5, wherein,

the data writing sub-circuit comprises a first writing transistor and a second writing transistor, wherein the grid electrode of the first writing transistor is connected with the first scanning signal end, the first pole of the first writing transistor is connected with the first data signal end, the second pole of the first writing transistor is connected with the first node, the grid electrode of the second writing transistor is connected with the second scanning signal end, the first pole of the second writing transistor is connected with the second data signal end, and the second pole of the second writing transistor is connected with the third node;

the second light-emitting control sub-circuit comprises a second light-emitting control transistor, wherein the grid electrode of the second light-emitting control transistor is connected with the light-emitting signal end, the first electrode of the second light-emitting control transistor is connected with the second electrode of the driving transistor, and the second electrode of the second light-emitting control transistor is connected with the light-emitting device;

The reset sub-circuit comprises a reset transistor, wherein a gate electrode of the reset transistor is connected with the reset end, a first electrode of the reset transistor is connected with the first signal end, and a second electrode of the reset transistor is connected with the first node.

8. A display device, comprising: a light-emitting device and a pixel circuit according to any one of claims 1 to 7.

9. The display device of claim 8, further comprising a determination module configured to: and judging whether the pixel circuit is in a first brightness mode or a second brightness mode according to the gray scale of the image to be displayed.

10. A driving method of a pixel circuit, characterized in that the pixel circuit is the pixel circuit according to any one of claims 1 to 7, the driving method of the pixel circuit when the pixel circuit is in the first luminance mode comprising:

in a reset stage, providing an effective level signal to the first gating signal terminal so that the first gating sub-circuit conducts the second node and the third node;

in a data writing stage, an invalid level signal is provided for the first gating signal terminal, and an effective level signal is provided for the first scanning signal terminal, so that the first gating sub-circuit disconnects the second node from the third node, and the data writing sub-circuit writes the data signal of the first data signal terminal into the first node;

When the pixel circuit is in the second brightness mode, the driving method of the pixel circuit includes:

in a reset stage, an invalid level signal is provided to the first gating signal terminal so that the first gating sub-circuit disconnects the second node from the third node;

and in the data writing stage, an invalid level signal is provided for the first gating signal terminal, and an effective level signal is provided for the second scanning signal terminal, so that the data writing sub-circuit writes the data signal of the second data signal terminal into the third node.