CN114090196A

CN114090196A - Coroutine switching method, coroutine switching device and coroutine switching equipment

Info

Publication number: CN114090196A
Application number: CN202010859901.1A
Authority: CN
Inventors: 程宏才; 崔英利; 郭海涛; 张斌; 周罗青
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-08-24
Filing date: 2020-08-24
Publication date: 2022-02-25
Also published as: WO2022042127A1

Abstract

A method, a device and equipment for coroutine switching are provided, which comprises: the timeout protocol is identified, for example, by starting a timer when a first protocol currently running is started, triggering an interrupt signal when the timer reaches a first threshold, and switching to a second protocol as the currently running protocol in response to the interrupt signal. According to the method, when the overtime coroutine is identified, the overtime coroutine can be switched forcibly to be switched to the second coroutine to operate, the phenomenon that the operating time of one coroutine is too long, other coroutines cannot obtain the execution opportunity is avoided, fair and stable operation among the coroutines is achieved, and the system performance is improved.

Description

Coroutine switching method, coroutine switching device and coroutine switching equipment

Technical Field

The present application relates to the field of computer technologies, and in particular, to a method, an apparatus, and a device for coroutine switching.

Background

The operating system supports multi-thread mode operation, and a large number of concurrent threads may be set in one business process in order to improve business performance. And the plurality of concurrent threads are sequentially executed in a polling scheduling mode in the time slice. One thread comprises one or more coroutine tasks, and the coroutine tasks contained in the thread are executed alternately in sequence in the time slice to which the thread belongs. Coroutine tasks are used to execute a group of functions that includes sub-functions, and each coroutine task may be used to execute one or more sub-functions. Because the current coroutine task is processed in a sequential manner, different coroutine tasks and different subfunctions of the same coroutine task need to be completed in sequence, that is, for the same coroutine task, only the current subfunction completes the execution, the execution process of the next subfunction continues, when the execution time process of a certain subfunction is caused by network and other reasons, the execution time of the coroutine task is too long, and other coroutine tasks or subfunctions of the same coroutine task cannot be executed, which affects the performance of thread scheduling processing in the whole system.

Disclosure of Invention

The application provides a coroutine switching method and device, which are used for realizing fair switching between coroutine tasks and improving the running stability of a system.

In a first aspect, the present application provides a coroutine handover method, including: determining that the first protocol is an overtime protocol, wherein the overtime protocol is a protocol with the operation duration reaching a first threshold; interrupting the first coroutine; and switching the second coroutine as the current execution coroutine.

Through the design, the overtime coroutines the program, and the overtime coroutines the program forcibly, and switches to the second coroutines the program to operate, so that the phenomenon that the operating time of a certain coroutine program is too long and other coroutines the program can not obtain the execution opportunity is avoided, fair and stable operation between the coroutines is realized, and the system performance is improved.

In a possible implementation method, the determining that the first protocol is a timeout protocol includes: starting timing when the first protocol is started; and when the running time of the first protocol reaches a first threshold, determining that the first protocol is an overtime protocol.

Through the design, when the coroutine is started, timing is started, when the timing time reaches a first threshold value, the overtime coroutine of the coroutine is determined, the running time of each coroutine can be switched when the running time reaches the first threshold value, and fair running among the coroutines is guaranteed.

In a possible implementation method, the switching the second coroutine as a current execution coroutine includes: selecting the second coroutine, wherein the second coroutine is a coroutine adjacent to the first coroutine in a task queue; and taking the second coroutine as a current execution coroutine.

Through the design, the first coroutine is determined to be overtime coroutine, and then the first coroutine is switched to the second coroutine, so that the phenomenon that the running time of the first coroutine is too long is avoided, other coroutines except the first coroutine are given running opportunities, and fair switching among the coroutines is ensured.

In a possible implementation method, the selecting the second coroutine includes any one of the following manners: the second coroutine is a coroutine randomly selected from coroutines to be executed and contained in the first thread; or the second coroutine is a coroutine with the highest priority in coroutines to be executed contained in the first thread; or, the second coroutine is a coroutine with the top sequence at the current time in coroutines to be executed contained in the first thread.

In one possible implementation, the interrupting the first coroutine includes: triggering interrupt processing, the interrupt processing comprising: and saving the context when the first coroutine is interrupted according to the thread state of the first coroutine, wherein the context is used for indicating the running information when the first thread is interrupted.

Through the design, the priority of the interrupt processing is higher, so that when the first coroutine is the overtime coroutine, the first coroutine can be forcibly interrupted, and the other coroutines are switched. Further, the context in which the first coroutine was interrupted is saved, so that the current context can be restored to continue running the coroutine when the first coroutine is scheduled again.

In a possible implementation method, the saving a context when the first thread is interrupted according to the state of the first coroutine includes: when a first thread where the first coroutine is located is in an interrupt state, storing a register value of the first thread to a kernel shared space, wherein the kernel shared space is a kernel storage space corresponding to the first thread, and the register value is used for recording the running information of the first thread.

In one possible implementation, the method further includes: modifying the context returned by the interruption into the context of the coroutine processing program; executing interrupt return and running the coroutine processing program; and running the coroutine processing program to generate a recovery coroutine corresponding to the first coroutine in an application layer, and executing the recovery coroutine to recover the field when the first coroutine is interrupted.

Through the design, the interrupt return address is modified, so that the coroutine processing program of the application layer is directly jumped to when the interrupt return is executed, the coroutine processing program can generate the recovery coroutine corresponding to the first coroutine, when the scheduler schedules the recovery coroutine again, the context running when the first coroutine is interrupted can be recovered, and the CPU does not need to be switched to the running authority level corresponding to the kernel state.

In a possible implementation method, the saving a context when the first thread is interrupted according to the state of the first coroutine includes: when a first thread in which the first coroutine is located is in a waiting state, storing a context of the first thread stored in the first thread control block to a kernel shared space, wherein the kernel shared space is a kernel storage space corresponding to the first thread, and the register value is used for recording the running information of the first thread.

Through the design, if the first coroutine is in a waiting state, the context in the first thread control block is stored in the kernel shared space, and the context of the thread control block is modified into the context of the coroutine processing program, so that when the first thread is scheduled again, the context operation of the coroutine processing program is recovered according to the context stored in the thread control block of the first thread, a recovery coroutine corresponding to the first thread is generated, when the scheduler schedules the recovery coroutine again, the context operation when the first coroutine is interrupted can be recovered, and the CPU does not need to be switched to the operation permission level corresponding to the kernel state.

In one possible implementation, the method further includes: modifying the context stored in the first thread control block into the context of a coroutine processing program so as to restore the context of the coroutine processing program and run the coroutine processing program when the first thread is scheduled again; and running the coroutine processing program to generate a recovery coroutine corresponding to the first coroutine in an application layer, and executing the recovery coroutine to recover the field when the first coroutine is interrupted.

In one possible implementation method, running the coroutine processing program includes: acquiring a register value of the first thread from the kernel shared space, and storing the register value of the first coroutine to a data structure corresponding to the first coroutine according to a preset format; the preset format is used for indicating the storage sequence of the register values of the first coroutine; and generating the recovery coroutine corresponding to the first coroutine according to the stored data structure.

In one possible implementation, the method further includes: and running the recovery coroutine: and reading the register value of the first coroutine from the data structure corresponding to the first coroutine according to a preset format, and writing the register value into a corresponding register.

In a possible implementation method, after the register value of the first coroutine is stored in the data structure corresponding to the first coroutine according to a preset format, and before the recovery coroutine corresponding to the first coroutine is generated, the method further includes: saving the context of the coroutine recovery program to the data structure; running the recovery coroutine, further comprising: and reading the context of the coroutine recovery program from the data structure, and operating the coroutine recovery program, wherein the coroutine recovery program is used for reading the register value of the first coroutine from the data structure corresponding to the first coroutine according to a preset format, and writing the register value into a corresponding register.

In a second aspect, the present application further provides an apparatus, where the apparatus includes multiple functional units, and the functional units may perform functions performed by the steps in the method of the first aspect. These functional units may be implemented by hardware or software. In one possible design, the apparatus includes a detection unit and a processing unit. For the beneficial effects achieved by the apparatus, please refer to the description of the first aspect, which is not described herein again.

In a third aspect, an embodiment of the present application further provides an apparatus, which includes a processor and a memory, where the memory stores program instructions, and the processor executes the program instructions in the memory to implement the method provided in the first aspect. For the beneficial effects achieved by the apparatus, please refer to the description of the first aspect, which is not described herein again.

In a fourth aspect, the present application further provides a computer-readable storage medium having stored therein instructions, which, when executed on a computer, cause the computer to perform the method provided by the first aspect.

In a fifth aspect, the present application further provides a computer chip, where the chip is connected to a memory, and the chip is used to read and execute a software program stored in the memory, and execute the method provided in the first aspect.

Drawings

Fig. 1 is a schematic view of a scenario of multi-thread concurrent execution according to this embodiment;

fig. 2 is a schematic view of a scenario of a thread active application switching provided in this embodiment;

FIG. 3 is a diagram illustrating a relationship between a thread and a coroutine according to this embodiment;

fig. 4 is a schematic structural diagram of a possible network system provided in this embodiment;

fig. 5 is a schematic diagram of a CPU work flow provided in this embodiment;

fig. 6 is a schematic view of a stack operation scenario provided in this embodiment;

fig. 7 is a schematic structural diagram of an assist range switching apparatus provided in this embodiment;

fig. 8 is a schematic flow chart of protocol switching according to this embodiment;

fig. 9 is a schematic flowchart corresponding to a coroutine switching method provided in this embodiment;

fig. 10 is a schematic structural diagram of a coroutine switching device provided in this embodiment;

fig. 11 is a schematic structural diagram of a coroutine switching device provided in this embodiment.

Detailed Description

In order to make the present application easier to understand, some basic concepts related to the embodiments of the present application are explained first below. It should be noted that these explanations are for the convenience of those skilled in the art, and do not limit the scope of protection claimed in the present application.

A process may refer to a running activity of a program with a certain independent function, and is a carrier for running an application program, or may refer to a process as a running instance of an application program, and is a dynamic execution of the application program. For example, when a user runs a Notepad program (Notepad), the user creates a process to accommodate the code that makes up Notepad. The process is an independent unit for resource allocation and scheduling of the system, each process has a memory space of the process, and different processes are independent of each other.

Threads, which are contained in the processes and created in the processes, can share the resources of the processes, one process contains at least one thread, and the thread is a basic unit of a system for allocating processor time resources, or a unit of independent execution in the processes. The threads have concurrency, that is, a single process supports and executes a plurality of concurrent threads, the memory space of the process is shared among the threads, and each thread concurrently executes different tasks. For example, one thread may be used to write a file to a disk, and another thread may be used to receive a key operation of a user and react in time, and the threads do not interfere with each other.

Referring to fig. 1, a schematic diagram of concurrent execution of threads is shown, as shown in the figure, each thread runs for a fixed time in sequence, and each thread is executed in turn, because the execution efficiency of a Central Processing Unit (CPU) is very high, a time slice can be very short, and the CPU can rapidly switch among the threads, thereby exhibiting an effect that multiple tasks are performed simultaneously, which is called concurrency of threads. The period of time (fixed duration) for executing the thread may be referred to as a time slice, and the state in which the thread is executing is recorded as a running state; when a time slice runs out, a thread is dispatched out of a running state, which can also be understood as a thread being suspended, and waiting for the arrival of the next time slice belonging to the thread, and the state of the thread can be marked as a ready state (or a waiting state). For example, in one possible scenario, within a time slice in which a thread runs, the thread may also be temporarily interrupted by a task with a higher priority, and after the task with the higher priority is completed, the state of the interrupted thread is resumed to continue running until the time slice user, and the state of the interrupted thread may be recorded as an interrupted state.

And 3, coroutine can be a lightweight thread, the thread is a coroutine carrier, a plurality of coroutines can share one thread, different coroutines also have different independent context environments, and the coroutine comprises code segments and stacks, and is sequentially executed in the thread through a coroutine framework. Similarly, the context of coroutines mainly includes register values.

In order to better understand the technical solution of the present application, the scheduling manner of the thread and coroutine is described next.

The thread is scheduled and managed by an operating system, and currently, most operating systems schedule threads in two triggering modes: a preemptive scheduling mode of time slice rotation and a mode of actively applying for scheduling by a thread.

The scheduling mode of the time slice rotation means that the thread running time reaches the preset time and is forcibly switched by the operating system. The mode that the thread actively applies for scheduling means that the thread actively informs the operating system to switch, and the operating system determines to switch to a new thread. Taking the active application and scheduling of the thread as an example, the switching process of the thread is introduced below, please refer to fig. 2, which is a schematic flow diagram of active request and scheduling of the thread, assuming that the user program a is the currently executing thread, the user program a can actively apply for scheduling, notify the operating system kernel to abandon the current CPU resource (e.g., register and memory resource), apply for using the operating system to provide a service program to complete the thread switching work, and at the same time, the operating system controls the CPU to switch from the operation authority corresponding to the user mode to the operation authority corresponding to the kernel mode, execute the interrupt processing, and suspend the user program a, where the interrupt processing includes, for example: the method comprises the steps of storing a context (the context comprises a register value and is used for indicating running information when a thread is suspended) of a current user program A (namely a certain thread of the user program A) into a memory (such as a thread control block), then selecting a next thread to be executed from a task queue, such as an application program B, recovering the context of the thread B from the memory, controlling a CPU to switch back to a running authority corresponding to a user mode from a running authority corresponding to a kernel mode, and executing the application program B.

The user state and the kernel state refer to the operating state of the operating system. At present, hierarchical protection is generally implemented in computer systems, i.e. according to the severity of the affected operation in the computer system, some operations must be executed by some roles with corresponding permissions, for example, operations such as direct access to hardware and modification of hardware working mode require the highest permission to execute.

The protection of the computer needs to be completed by the cooperation of a CPU and an operating system, the modern CPU generally provides multiple operation permission levels, the operating system is generally divided into multiple operation states to be matched with the CPU, the common states of the operating system are a user state and a kernel state, wherein the kernel state generally has the highest permission, and all instructions and operations are allowed to be executed by the CPU; the user mode is generally a lower authority, in this state, the software program can only execute limited instructions and operations, and the high-risk operations are not allowed by the CPU hardware, such as configuring the internal control register of the CPU, accessing the memory address of the kernel portion, and the like. When an operating system needs to execute programs under different permissions, the permission state of the CPU is usually switched to a corresponding state, and then the corresponding program is executed.

The scheduling method of the coroutine is described below. Referring to fig. 3, a schematic diagram of a relationship between a thread and a coroutine, as shown in the figure, for example, a coroutine may be regarded as a function group, a relatively independent task is formed by a plurality of sub-functions, there is a call relationship between functions within the coroutine task, there is also a jump call relationship between coroutine tasks, but the call address of the next task is not specified by the current coroutine task but is determined by selection of a scheduler, the scheduler may be regarded as a special task, the scheduler will always exist without exiting, after the current coroutine task is completed, a jump is automatically made to the context of the scheduler to run, and the scheduler selects an appropriate coroutine task from the coroutine tasks waiting to run currently and jumps to the context of the coroutine task to run. In an implementation manner, the metadata of each coroutine task may include a coroutine control block, where the coroutine control block is used to identify the coroutine task and record the context (e.g., related register values) of the coroutine task, and the scheduler obtains the context of the coroutine task from the metadata of the coroutine task.

The conditions for triggering the scheduler to perform the coroutine handover include active coroutine application scheduling, and in order to prevent a coroutine from occupying a long time, currently, the prior art further provides a coroutine handover mode of timeout detection. For example: setting overtime detection at a calling entry of a subfunction of the coroutine, calculating the total running time of the current coroutine each time the function is called, and actively calling a coroutine switching interface to carry out coroutine switching if the total running time exceeds the set time.

However, if the thread does not make a sub-function call, for example, a malicious loop executes a sub-function, or the execution time in the sub-function is too long, in this case, other coroutine tasks may not get an execution opportunity, and may therefore not get an execution opportunity and be starved, which affects the normal and stable operation of other coroutines.

In view of this, in order to improve the processing performance of the entire system, the application provides a coroutine task timeout switching method, which specifically determines whether a coroutine currently being executed is a timeout coroutine, where the timeout coroutine is a coroutine whose operation duration reaches a first threshold, forcibly interrupts the first coroutine, and cuts off a second coroutine as the currently executed coroutine.

Next, the coroutine task switching method provided by the present application is described in detail with reference to the accompanying drawings. Fig. 4 is a schematic architecture diagram of a network system to which the method is applied according to an embodiment of the present application, and as shown in the drawing, the network system includes a server, a network device, and a storage device. Wherein the server may be capable of communicating with the memory via a network device, illustratively including but not limited to: and the network connection equipment between the equipment such as the switch and the router.

The servers, storage devices, and network adapters may include processors, memory, storage, and network adapters, to illustrate the functionality of the components.

First, storage

The memory may mainly include a program storage area and a data storage area. Wherein, the storage program area can store an operating system, various application programs (such as a camera application), and the like; the stored data area may store data created from use of the application (e.g., images captured by a camera application, video), etc.

The memory includes an internal memory (also called as a memory, and may also be called as a main memory) and an external memory. The external memory comprises a nonvolatile memory, such as at least one disk memory device, a flash memory device or other volatile solid state memory devices, has the characteristics of large capacity, slow speed, no data loss after power failure and the like, and is used for storing programs and data for a long time or permanently.

The memory may include registers, high speed random access memory, has features of small capacity, fast speed, power down volatility, etc. for storing data and programs currently being executed. It is understood that the internal memory is a channel between the CPU and the external memory, and can be used to first read the program and data stored in the external memory into the internal memory, and then the program in the internal memory is read by one of the processors to be executed. Generally, the registers may be integrated into the processor as part of the processor, as will be described in more detail below.

Second, the processor

The processor may be a Central Processing Unit (CPU), an Application Specific Integrated Circuit (ASIC), or a Field Programmable Gate Array (FPGA).

The following describes a processor with a CPU as an example. Illustratively, the CPU is mainly composed of an arithmetic unit, a control unit, a storage unit, and a bus, wherein the arithmetic unit, the control unit, and the storage unit are connected to each other through the bus.

The control unit is used for analyzing the program instruction and generating a control instruction. Specifically, the control unit includes a program register (PC), an Instruction Register (IR), an Instruction Decoder (ID), an operation control unit (OC), and the like. The program register PC is used for storing the address of the instruction to be read, and the control unit acquires the instruction of the corresponding address according to the value of the program register PC and puts the instruction in the instruction register IR based on a pre-programmed program. The operation code of the instruction is sent to the instruction decoder ID for decoding, the operation control unit OC generates a control instruction of all actions required for realizing the instruction function according to the decoding of the instruction operation code by the instruction decoder ID, and sends the control instruction to the corresponding component according to the determined execution time sequence of the control instruction, wherein the control instruction is used for indicating the operation required to be carried out. After the current instruction is executed, the address of the next instruction is calculated and sent to a program counter PC.

And the operation unit is used for responding to the control instruction sent by the control unit and executing corresponding operation operations, such as various arithmetic operations and/or logic operations.

The memory unit includes a register group, and the register has the characteristics of less stored information, high access speed and the like, and is generally used for temporarily storing data, such as data waiting for processing or data already processed, in the CPU. Because the access speed of the register is high, the time for accessing the register by the CPU is shorter than the time for accessing the memory. By adopting the register, the times of accessing the memory by the CPU can be effectively reduced, and the working speed of the CPU is improved. The register group includes a special register and a general register.

Specifically, the processor is used for executing an operating system and an application program. In this embodiment of the application, the operating system and the application program may be executed on the same CPU, or may be executed on different CPUs, for example, when the computer is a multi-core processor, a single processor may be used to execute the operating system, and another processor is used to run the application program.

Referring to fig. 5, a schematic diagram of the CPU workflow is shown. A process may refer to an application program running in an operating system, and as shown in the figure, when a process is running, the operating system allocates resources such as a CPU, a memory, and the like to the process, wherein the memory is used for storing codes (such as code segments in the figure) and data (such as data segments in the figure) of the process. It should be understood that the data section contains the data required to complete the instructions of the code section.

The program counter of the CPU is used to record a code address (instruction address in the figure) in progress, and the code address may be, for example, a segment number and/or a line number of a code segment, or the like. The instruction register is used for realizing the function of a program counter, and is particularly used for recording instructions corresponding to instruction addresses. The control unit reads the instruction corresponding to the instruction address in the memory according to the instruction address of the program counter and stores the instruction in the instruction register.

Then, the control unit decodes the instruction, determines a control instruction corresponding to the operation required by the instruction according to the operation code, and sends the control instruction to a corresponding unit, such as a storage unit and/or an arithmetic unit. It should be understood that each instruction has an opcode that identifies what nature of the operation the instruction should perform. In short, it indicates what the CPU needs to do.

Illustratively, the control unit issues a control instruction 1 to the storage unit and a control instruction 2 to the arithmetic unit. For example, the control instruction 1 is used for instructing the storage unit to read data of an operand address from the memory, and the data can be temporarily stored in a corresponding register after being read by the storage unit, so that the arithmetic unit performs an operation according to the data in the register. The control instruction 2 is used for instructing the arithmetic unit to acquire data from the storage unit for operation. Illustratively, the data structure in the data storage area in the memory may be a stack, the storage unit may further include a Stack Pointer (SP) for storing address information of data in the stack of the currently running application program, and the storage unit obtains the data in the stack corresponding to the address information in the memory according to address confidence recorded by the stack pointer.

The stack is a data structure with data items arranged in sequence, and is composed of stack frames, each stack frame can correspond to a function call, and the stack frames can contain parameter values, local variables (including register values), some temporary data and the like of the function. Data is stored to the stack in a manner that inserts and deletes data items only at one end of the stack, called the top of stack (top). The position of the stack top at the current time can be indicated by using a pointer or other forms, when new data needs to be stored, the data or the information of the data is stored to the position of the stack top, and at the moment, the pointer indicating the stack top can point to the position of the new stack top. It should be understood that the storage manner of the stack is a logical structure, and the stack can be simply understood as a data structure with one end fixed and the other end floating, all data in the stack can be stored or fetched only at one floating end (called the top of the stack), and the storage and reading manner of the data can be processed according to the principle of "first-in first-out". Referring to FIG. 6, a diagram of some stack operations defined, operations that are stored on the stack (i.e., inserts) are referred to as Pushes (PUSH) and operations that are popped from the stack are referred to as POPs (POPs). As shown, the push operation includes: a Stack Pointer (SP) initially indicates the location where si is stored, and when there is new data bp stored in the stack, the pointer is incremented by 1, at which time the pointer points to the location where bp is stored. The pop operation (i.e., delete) process is the reverse of the push operation process, and the pop process determines the current position of the stack top, and then feeds the contents of the internal memory (e.g., ram unit) indicated by the pointer to the destination position (e.g., unit addressed by the direct address), and then decrements the Stack Pointer (SP) by 1.

Optionally, the manner of storing or reading data in a stack may also adopt a principle of "first in and then out", and may be set according to a service requirement in specific implementation.

The above is a schematic flow chart of executing one instruction, and after one instruction is executed, the program counter +1 points to the next instruction, and the next instruction is continuously executed through the above flow chart.

In summary, the work flow of the CPU includes: and sequentially reading each instruction and corresponding data from the memory, and performing operation processing on the data according to the specification of the instruction operation code until the program is executed.

For example, the operating system may further control the CPU to read data stored in a specified stack address, for example, a PC value, and fill the acquired PC value into a PC register, and the CPU reads and executes a program instruction corresponding to the PC register value, thereby implementing program switching. In this embodiment of the present application, an operating system and an application program may be executed on the same CPU, or may be executed on different CPUs, for example, when a computer is a multi-core processor, a single processor may be used to execute the operating system, and another processor is used to run a service, such as an application program (including a process, a thread, and a coroutine).

Illustratively, the coroutine task queue stores a coroutine task control block to be executed, the coroutine task control block records a context after the coroutine is executed last time, the context includes register values, such as a current PC value, an SP value, and the like, when switching to a coroutine task, the CPU restores the context of the coroutine according to the coroutine task control block of the coroutine, for example, writes the PC value recorded by the coroutine task control block into a PC register, writes the SP value into a stack pointer, and continues execution from a position where the coroutine has last run stopped. It should be understood that the above is only an example, and actually the context of coroutine may also include register values, which is not limited by the embodiment of the present application.

The network adapter refers to a device or equipment with a communication interface, and may also be referred to as a network card, for implementing connection between the equipment, for example, a server may implement connection with a storage device through the network adapter.

It should be noted that the network system shown in fig. 4 is only an example, and the network system may further include more or less network devices, for example, a computing server (not shown in fig. 4). Each network device in the network system may also include more or fewer components. In addition, the number of network devices such as a server, a gateway device, and a storage server included in the network system is not limited in the present application.

The coroutine switching method provided by the embodiment of the present application may be deployed in the network system shown in fig. 4, and specifically, may be deployed in one of the devices in the network system, for example: a server, a network device, or a storage device.

The embodiment of the present application does not limit the form of the processor in the deployed device, for example, the processor may be a CPU, an FPGA, or the like, where the CPU may adopt an ARM or an X86 architecture, and the embodiment of the present application does not limit this. Among them, ARM is a 32-bit Reduced Instruction Set (RISC) processor architecture, and is suitable for devices in the field of mobile communications, such as portable devices (mobile phones, multimedia players, palmtop electronic games and computers), computer peripherals (hard disks, desktop routers), and the like. The X86 architecture is a set of computer language instructions executed by a microprocessor, referred to as the standard numbered acronym for the intel general computer column, which also identifies a common set of computer instructions.

It should be understood that under different architectures, the kind, number, name of registers within a CPU may be completely different, or not completely the same. For example, in an X86 CPU, registers include, but are not limited to: program Counter (PC), Stack Pointer (SP), radix pointer (BP), general purpose registers, timers. In an X86 CPU, general purpose registers include, but are not limited to, bp, si, di, and the like. Among them, the program counter may also be called an Instruction Pointer (IP) or an Instruction Address Register (IAR) in the x86 CPU. BP, which is generally used in functions to store the stack top base address of an SP when entering a function, is usually used in conjunction with an SP, and may be considered to record the stack bottom of the stack of BP and the stack top of the stack of SP, and a range of data in the stack may be determined from BP and SP.

For convenience of description, the technical solution provided by the embodiment of the present application is specifically described below by taking a CPU with an X86 architecture as an example.

Referring to fig. 7, a schematic structural diagram of an assist range switching apparatus provided in an embodiment of the present application is shown, where the apparatus includes: a clock module 700, an interrupt handling module 701, a timeout coroutine handling module 702, and a scheduler module 703. The timeout coroutine processing module 702 specifically includes a coroutine saving module 7021 and a coroutine restoring module 7022.

The clock module 700 is configured to time the running time of the current coroutine, and trigger an interrupt signal when the time reaches a set time. Illustratively, the clock module may be a hardware timer, such as a CPU clock.

The interrupt processing module 701 stores an interrupt handler for executing an interrupt process in response to an interrupt signal. Illustratively, the interrupt handling module 701 performs different processes according to the state of the thread in which the timeout coroutine is located. Illustratively, the interrupt processing includes saving the context of the timeout coroutine to the kernel shared space, and modifying the address to resume execution of the thread in which the timeout coroutine is located, and jumping to the coroutine saving module 7021.

The coroutine saving module 7021 is configured to generate a recovery coroutine corresponding to the overtime coroutine, re-suspend the recovery coroutine in the task queue, and jump to the scheduler module 703.

The scheduler module 703 is configured to select a second coroutine in the task queue, where the second coroutine is a new coroutine to be executed, and switch the second coroutine to a currently running coroutine.

The apparatus further includes a coroutine recovering module 7022, where the coroutine recovering module 7022 is configured to start the execution coroutine recovering module 7022 to recover the context when the overtime coroutine is interrupted when the scheduler schedules the recovery coroutine corresponding to the overtime coroutine again.

By the mode, the overtime coroutines can be switched forcibly when the overtime coroutines are identified, so that fair and stable operation among the coroutines is realized.

It should be noted that the module may be a hardware module or a logic module, and when the apparatus is deployed in a virtual machine, the module may also be a virtual module, which is not limited in this embodiment of the present application.

The protocol switching process of the embodiment of the present application is described below with reference to the apparatus and the specific embodiment shown in fig. 7.

In this embodiment, a complete handover procedure of the timeout protocol will be described by the apparatus shown in fig. 7, and the complete handover procedure may exemplarily include: initialization process, coroutine switching process and coroutine restoring process. The above processes are described below by taking the first thread as an example, and taking the coroutine currently operated by the first thread as the first coroutine.

Referring to fig. 8, a schematic diagram of a complete handover procedure of the timeout routine provided in the embodiment of the present application is shown, where the procedure includes:

firstly, initializing.

Before the first thread starts running (which may be, for example, when the first thread is created), the first thread is initialized, which includes, but is not limited to, the following operations:

1) and creating a shared memory space corresponding to the first thread.

Illustratively, each thread has a shared memory space corresponding to it, which is shared by all coroutines of that thread. In one embodiment, coroutines in the same thread correspond to different areas of the shared memory space, and a context of the coroutine can be stored in each area. For example, the current thread includes coroutine a, coroutine B, and coroutine C, and the shared memory space may be divided into coroutine a area, coroutine B area, and coroutine C area. In another embodiment, coroutines within the same thread may share the same region of the shared memory space, which may be used to store coroutine contexts. For example, for all coroutines of the same thread, since coroutines in the thread run in a serial manner, the shared memory space can be used in the coroutine switching process, and after the coroutine switching is completed, information in the shared memory space can be covered for reuse. For example, the first thread includes coroutine a, coroutine B and coroutine C, and the running process of the first thread may be, for example, coroutine a, then switch to coroutine B, execute coroutine B, and finally switch to coroutine C, execute coroutine C. If coroutine A is overtime coroutine, the context of coroutine A can be stored in the shared memory space of the first thread in the process of switching coroutine A. After the coroutine A is switched, when the coroutine B is executed, the coroutine B is determined to be an overtime coroutine, and at the moment, the context of the coroutine A is stored in the shared storage space of the first thread, so that the context of the coroutine B can cover the context of the coroutine A.

2) A clock module of the first thread is initialized.

The timing time of the clock module 700, i.e., the first threshold in the embodiment of the present application, is set. When the timing duration of the clock module 700 reaches the first threshold, an interrupt signal is triggered.

In one practical way, the threads correspond to the clock modules one to one, that is, each thread has a clock module corresponding to one. For example, the clock module name corresponding to the first thread is clock a, the clock module name corresponding to the second thread is clock B, the interrupt signal triggered by clock a is triggered when the first thread is detected as the timeout phase, and the interrupt signal triggered by clock B is triggered when the second thread is detected as the timeout phase. In another implementable manner, some or all of the threads share a clock module. For example, the first thread and the second thread each correspond to one clock module. After the clock module triggers the interrupt signal, the timeout co-thread processing module needs to determine which thread the interrupt signal is triggered for when responding to the interrupt signal. Therefore, during the initialization process, an Identifier (ID) of the protocol to be executed may also be configured to the interrupt processing module 701, and when the response signal is received, which protocol is the timeout protocol is determined according to the identifier. See in particular the introduction to 3) below.

3) The interrupt handling module 701 is initialized.

Specifically, the relevant information of the protocol saving module 7021 is configured to the interrupt processing module 701 corresponding to the configuration clock module 700. The information related to the protocol saving module 7021 includes, but is not limited to: the code entry address (e.g. PC value) of the timeout protocol saving module 702, and the stack address (e.g. SP value at stack top) corresponding to the timeout protocol saving module 702. In addition, if a plurality of threads share one clock module, the Identifier (ID) of the first thread may be configured to the interrupt processing module 701, and other information may also be configured, which is not limited in the present application.

It should be noted that, if the threads correspond to the clock modules one to one, an Identifier (ID) of the first thread may also be configured to the interrupt processing module 701, so as to reduce the thread identification time in response to the interrupt signal, or the interrupt processing module 701 identifies the threads according to the clock module that sends the interrupt signal, which is not limited in this embodiment of the present application.

And secondly, starting to execute the first coroutine.

The scheduler module 703 stores a task queue, where the task queue includes all coroutines to be executed of the first thread. Assuming that the scheduler module 703 selects the first coroutine as the coroutine to be executed in the task queue, the scheduler module 703 records information of the first coroutine, which mainly includes location information of a coroutine control block of the first coroutine. It should be noted that each coroutine has a corresponding coroutine control block, and exemplarily, similar to the thread control block, the coroutine control block is configured to record information of the coroutine task, for example, an sp value of the coroutine task, and may further include information such as a stack size of the coroutine task, and the coroutine control block may be configured to uniquely identify the coroutine, that is, determine the currently running coroutine according to the coroutine control block. For example, the location information of the coroutine control block of the first coroutine may be an index value of the coroutine control block, and the scheduler module 703 may find the coroutine control block according to the index value and determine the coroutine currently running in the first thread according to the coroutine control block.

The scheduler module 703 starts executing the first routine and simultaneously starts the clock module 700 to start timing. Illustratively, the clock module 700 is turned off when the first protocol actively applies for scheduling.

And thirdly, triggering an interrupt signal when the first protocol is detected to be overtime protocol.

Illustratively, when the timing duration of the clock module 700 reaches a first threshold, it is determined that the first protocol is a timeout protocol, and an interrupt signal is triggered.

Fourthly, responding to the interrupt signal, jumping to an interrupt processing module 701 to execute interrupt processing.

Specifically, when the interrupt handler is running, the interrupt handling module 701 executes the following interrupt handling:

according to the state of the thread where the current coroutine is located, the context of the current coroutine is saved by different methods, and illustratively, as described above, the state of the thread includes: the execution state, the ready state and the interrupt state, in the specific implementation process, any one of the following ways may be adopted to store the context of the current coroutine, including:

mode 1: and when the thread of the first coroutine is in an interrupt state, storing the context of the first coroutine in the interrupt state to the shared memory space.

Illustratively, the thread in which the first coroutine is located is still in a running state, but because the running time of the first coroutine is overtime, other coroutines needing to be switched to the first thread are required to run, and therefore the thread is interrupted. It can be understood that the thread may still run, and the running time does not reach the duration of the time slice, for example, the thread is still in its own time slice, but the running time of the first coroutine exceeds the first threshold, the first coroutine needs to be suspended, and the process is switched to other coroutines of the thread, and the state where the thread is suspended by the interrupt signal is the interrupt state.

Correspondingly, the interrupt processing module 102 executes a first handler, including:

1) and storing the context when the first thread is interrupted into a shared storage space corresponding to the first thread, wherein the context information comprises values of registers such as a PC (personal computer), an SP (service provider) and the like. The interrupt processing program is located in the kernel space, the coroutine runs in the user space, and when the interrupt signal is responded, the coroutine which is being executed by the user space is forcibly interrupted, and then the interrupt processing program is executed. Correspondingly, the shared storage space may also be located in the kernel space, and the size of the shared storage space may be dynamically adjusted or may be a fixed size, for example, a maximum memory value required when storing the context information when the coroutine is interrupted.

2) The interrupt return address is modified to the entry PC address of the protocol saving module 7021, and the interrupt return stack address is modified to the stack top SP address of the protocol saving module 7021.

Generally, at the end of each interrupt handler, there is an instruction for returning the interrupt to the previous program, such as iret (or iretd), and when the return of the interrupt is required, the interrupt returns to restore the context when the current coroutine is interrupted, so as to continue executing the interrupted program. For example, if coroutine a is executing when the current thread is interrupted, the context when coroutine a was interrupted is restored when the interrupt returns.

3) And (4) executing interrupt return, recovering the context of the coroutine saving module 7021, and jumping to the context of the coroutine saving module 7021 for running. Here, the context returned by the interrupt is modified to the context of the coroutine saving module 7021, and the interrupt return is executed, so that the program can jump to the code segment and the data segment of the coroutine saving module 7021 to run the program of the coroutine saving module 7021.

Mode 2: when the first thread is in the ready state, the context of the first thread recorded in the first thread control block is saved in the shared memory space.

If the first thread is in the ready state when the interrupt signal is triggered, correspondingly, the interrupt processing module 102 executes a second processing program, which includes:

1) and storing the register context information stored in the thread control block of the first thread into the shared memory space corresponding to the first thread.

It should be understood that the first thread may have been scheduled out of execution before the clock module 700 completes its timing, and in order to allow the first subsequent thread to resume execution of the current task, the CPU records the context of the first thread when it was suspended into the first thread control block, and when the first thread is scheduled again, restores the context recorded in the first thread control block and continues execution of the first thread.

Therefore, in response to the interrupt signal, the register value of the first coroutine cannot be obtained from the register of the CPU, but the context information of the first coroutine is obtained from the thread control block of the first thread.

2) The PC address recorded in the thread control block is modified to the entry PC address of the protocol storage module 7021, and the SP address recorded in the thread control block is modified to the stack top SP address of the protocol storage module 7021.

In the embodiment of the present application, the context recorded in the first thread control block is modified to the context of the coroutine saving module 7021, and by the modification, when the first thread is scheduled again, the coroutine saving module 7021 is skipped to according to the modified context recorded in the first thread control block, so that the program stored in the coroutine saving module 7021 is executed, and subsequent coroutine switching is realized.

3) An interrupt return is performed. If the thread running before responding to the interrupt signal is the second thread, the second thread is suspended when jumping to the interrupt processing module 701 in response to the interrupt signal, and when the interrupt processing module 701 executes the interrupt return, if the relevant information of the interrupt return is not modified, the context of the suspended second thread is restored to continue executing the second thread. It should be understood that, when the first thread is scheduled again, the coroutine saving module 7021 is skipped according to the PC value and the SP value recorded in the thread control block of the first thread.

And fifthly, transferring to a coordination program storage module 7021.

After jumping to the coroutine saving module 7021, the following operations are executed:

1) and generating a recovery coroutine corresponding to the overtime coroutine.

The coroutine that was executing when the first thread was interrupted (i.e., the first coroutine) is queried, illustratively, the first coroutine is determined from coroutine control block information. The context of the first protocol is obtained from the shared memory space, and is illustratively one or more register values, including for example, a PC value, an SP value. As shown in fig. 8, first, the one or more acquired register values are saved in a first space of a stack of a first coroutine according to a preset storage format, and then the context of the coroutine restoring module 7022 is saved in a second space of the stack, where the first space is adjacent to the second space.

For example, assume that the context when the first routine is interrupted includes the value of register A, the value of register B, and the value of register C. For example, the predetermined storage format may be that the value of register a, the value of register B, and the value of register C are pushed onto the stack in sequence. For another example, the predetermined storage format may be that the value of the register C, the value of the register B, and the value of the register a are sequentially pushed onto the stack.

It should be understood that, since the first thread is interrupted by the interrupt signal, the number of registers that the first thread needs to store is different from the normal way that the first thread actively applies for scheduling, and generally, the number of registers that the first thread needs to store is greater than that of the second thread. Therefore, in the embodiment of the present application, the context information is stored in the preset storage format, that is, the context information is stored in the stack according to the number of registers that may be included when the first coroutine is interrupted and in a self-defined storage manner, and then the coroutine restoring module 7022 may sequentially read one or more register values of the coroutine from the stack according to the preset storage format, so as to restore the context of the first thread. The storage format of the context of the coroutine restoring module 7022 may be stored according to the storage format of the coroutine task when actively applying for scheduling in the prior art, or may be in another format, which is not limited in the embodiment of the present application.

And generating a recovery coroutine corresponding to the overtime coroutine according to the updated data stack, hanging the recovery coroutine into the task queue again, and waiting for subsequent scheduling execution again.

2) Jump to the context running of the scheduler module 703.

The protocol saving module 7021 further stores the address of the scheduler module 703, and adjusts the flow to the scheduler module 703 after the flow is executed.

And sixthly, jumping to a scheduler module 703, selecting a second coroutine, and switching to the current running coroutine.

The scheduler module 703 selects a new coroutine (denoted as a second coroutine) in the task queue according to the scheduling policy, that is, a coroutine other than the recovery coroutine, records information of the new coroutine, and starts to execute the new coroutine.

For example, the scheduling policy may be to select a coroutine with the highest priority from coroutines to be executed according to the priority of the coroutines, or sequentially select a coroutine with the highest position in a queuing manner, or randomly select one coroutine, which is not limited in the embodiment of the present application.

In one possible embodiment, in response to the interrupt signal, a logic exception may also be generated, and the interrupt handling module 701 may directly perform an interrupt return to the interrupted thread to continue running. Alternatively, before the clock module 700 times out, the first protocol actively applies for scheduling, and then the clock module 700 is turned off.

While the above describes the switching process of the timeout protocol, it should be understood that the recovery protocol corresponding to the timeout protocol may also be scheduled, and the following describes the process of scheduling execution of the recovery protocol.

As described above, the stack data of the recovery coroutine includes the first space and the second space, and when the recovery coroutine is scheduled again by the scheduler module 703, as shown in fig. 8, first, each register value of the coroutine recovery module 7022 is sequentially read from the second space of the recovery coroutine, each register value is written into the corresponding CPU register, when a BP value is read, the stack bottom address of the second space is determined according to the BP value, then, a PC value is read, the PC value is the code entry PC address of the coroutine recovery module 7022, the PC value is written into the program counter of the CPU, and the code segment of the coroutine recovery module 7022 is skipped to execute the coroutine recovery module 7022.

The coroutine restoring module 7022 sequentially reads one or more register values of the first coroutine from the first space of the stack according to a preset storage format, and if the value of the register C, the value of the register B, and the value of the register a are sequentially stored in the first space, the coroutine restoring module 7022 may determine, according to the preset storage format, the value of the register a, the value of the register B, and the value of the register C, which are sequentially read from the stack, and sequentially write the read values of the registers into corresponding CPU registers, thereby restoring a field when the coroutine is interrupted. Illustratively, the coroutine restoration module 7022 writes the SP value read from the first space into the SP register; determining the stack bottom of the first space according to the read BP value; and writing the read PC value into a program counter, wherein the PC value is a code address when the first co-program is interrupted when the first thread runs, and jumping to the code address to restore and execute the first co-program.

For convenience of describing the coroutine switching method provided by the present embodiment, the coroutine switching method of the present embodiment will be described below by using components related to the coroutine switching method provided by the present embodiment.

Referring to fig. 9, a flow diagram of a coroutine switching method provided in this embodiment is shown, where the method may be applied to the apparatus shown in fig. 7, and in fig. 9, a specific switching manner when a thread in which a timeout coroutine is located is in an interrupt state is described, where the method includes the following steps:

step 901 initializes the thread.

Step 902, determining a first protocol to be executed, and the scheduler module recording information of the first protocol.

In step 903, the scheduler module starts to execute the coroutine and simultaneously starts the clock module.

The timeout value of the clock module may be fixed or set before each turn-on.

Please refer to the above description for the specific execution flow of steps 901 to 903, which is not described herein again.

In step 904, the clock module 700 times out, and the first coroutine does not actively apply for scheduling, and sends an interrupt signal to the interrupt processing module 701.

In step 905, in response to the interrupt signal, if the first thread is in the interrupt state, the interrupt processing module 701 saves the context of the interrupted first thread to the shared memory space.

Optionally, after the clock module sends the interrupt signal, the interrupt processing module 701 may further control the clock module to close, and clear the interrupt signal.

In step 906, the interrupt processing module 701 modifies the relevant information returned by the interrupt to relevant information corresponding to the program saving module 7021.

In step 907, the interrupt processing module 701 executes an interrupt return, restores the context of the coroutine saving module 7021, and jumps to the coroutine saving module 7021.

In step 908, the coroutine saving module 7021 determines that the first thread is running when interrupted according to the coroutine control block information.

As described above, the scheduler module records therein the location information of the coroutine control block of the coroutine being executed by the first thread, and the location information of the coroutine control block indexes the coroutine control block, so as to determine the coroutine being executed before the first thread is interrupted, in this case, the first coroutine, according to the coroutine control block.

In step 909, the coroutine saving module 7021 obtains the context of the first coroutine from the shared memory space.

Step 910: the timeout routine processing module 702 stores the context acquired from the shared memory space into the stack corresponding to the first routine according to a preset storage format.

Step 911: the timeout subroutine processing module 702 saves the context sequence of the subroutine recovery module 7022 to the stack of the first subroutine.

Step 912: the timeout coroutine processing module 702 generates a recovery coroutine corresponding to the first coroutine and adds the recovery coroutine to the task queue.

Step 913: and restoring the context of the scheduler module and jumping to the scheduler module.

Step 914: the scheduler module selects a new coroutine in the task queue and starts executing the new coroutine.

As a possible embodiment, in response to the interrupt signal, if the first thread is already scheduled out of the running state, for example, the first thread is in a ready state, the interrupt processing module 701 executes the second processing procedure described above, that is, the register context information stored in the thread control block of the first thread is stored in the shared memory space corresponding to the first thread. The interrupt processing module 701 modifies the PC address recorded in the thread control block to the entry PC address of the protocol saving module 7021, and modifies the SP address recorded in the thread control block to the stack top SP address of the protocol saving module 7021. The interrupt handling module 701 performs an interrupt return, returning the suspended thread. When the first thread is scheduled again, the context of the coroutine saving module 7021 is restored according to the thread control block of the first thread, and the coroutine saving module 7021 is skipped. The subsequent flow may refer to the detailed description of steps 908 to 914, and the steps of the interrupt processing module 701 before responding to the interrupt signal may refer to the detailed description of steps 901 to 904, and the description is not repeated here.

Through the design, the overtime coroutines the program, and the overtime coroutines the program forcibly, and switches to the second coroutines the program to operate, so that the phenomenon that the operating time of a certain coroutine program is too long and other coroutines the program can not obtain the execution opportunity is avoided, fair and stable operation between the coroutines is realized, and the system performance is improved. On the other hand, since the priority of the interrupt processing is high, when the first coroutine is the timeout coroutine, the first coroutine can be forcibly interrupted, and the other coroutines can be switched. Further, the context in which the first coroutine was interrupted is saved, so that the current context can be restored to continue running the coroutine when the first coroutine is scheduled again.

Based on the same inventive concept as the method embodiment, an embodiment of the present application further provides an apparatus for executing the method executed in the method embodiment, and related features may refer to the method embodiment described above, which are not described herein again, and as shown in fig. 10, the apparatus includes a determining unit 1001 and a processing unit 1002.

A determining unit 1001, configured to determine that the first coroutine is an overtime coroutine, where the overtime coroutine is a coroutine whose operation duration reaches a first threshold;

the processing unit 1002 is configured to interrupt the first coroutine and switch the second coroutine as a current execution coroutine.

It should be understood that the apparatus of this embodiment may be implemented by an application-specific integrated circuit (ASIC), or a Programmable Logic Device (PLD), which may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or any combination thereof. When the methods shown in fig. 8 to 9 can also be implemented by software, the device and its respective modules may also be software modules.

In a possible implementation, the determining unit 1001 is specifically configured to start timing when the first coroutine is started; and when the running time of the first protocol reaches a first threshold, determining that the first protocol is an overtime protocol.

In a possible implementation manner, the processing unit 1002 is specifically configured to select the second coroutine, where the second coroutine is a coroutine adjacent to the first coroutine in a task queue; and taking the second coroutine as a current execution coroutine.

In a possible implementation manner, the second coroutine is a randomly selected coroutine from coroutines to be executed included in the first thread; or the second coroutine is a coroutine with the highest priority in coroutines to be executed contained in the first thread; or, the second coroutine is a coroutine with the top sequence at the current time in coroutines to be executed contained in the first thread.

In a possible implementation manner, the processing unit 1002 is specifically configured to trigger an interrupt processing, where the interrupt processing includes: and saving the context when the first coroutine is interrupted according to the thread state of the first coroutine, wherein the context is used for indicating the running information when the first thread is interrupted.

In a possible implementation manner, the processing unit 1002 is specifically configured to, when a first thread where the first coroutine is located is in an interrupt state, store a register value of the first thread to a kernel shared space, where the kernel shared space is a kernel storage space corresponding to the first thread, and the register value is used to record the running information of the first thread.

In a possible implementation manner, the processing unit 1002 is further configured to modify a context returned by the interrupt into a context of the coroutine handler; executing interrupt return and running the coroutine processing program; and running the coroutine processing program to generate a recovery coroutine corresponding to the first coroutine in an application layer, and executing the recovery coroutine to recover the field when the first coroutine is interrupted.

In a possible implementation manner, the processing unit 1002 is specifically configured to: when a first thread in which the first coroutine is located is in a waiting state, storing a context of the first thread stored in the first thread control block to a kernel shared space, wherein the kernel shared space is a kernel storage space corresponding to the first thread, and the register value is used for recording the running information of the first thread.

In a possible implementation manner, the processing unit 1002 is further configured to: modifying the context stored in the first thread control block into the context of a coroutine processing program so as to restore the context of the coroutine processing program and run the coroutine processing program when the first thread is scheduled again; and running the coroutine processing program to generate a recovery coroutine corresponding to the first coroutine in an application layer, and executing the recovery coroutine to recover the field when the first coroutine is interrupted.

In a possible implementation manner, the processing unit 1002 is specifically configured to: acquiring a register value of the first thread from the kernel shared space, and storing the register value of the first coroutine to a data structure corresponding to the first coroutine according to a preset format; the preset format is used for indicating the storage sequence of the register values of the first coroutine; and generating the recovery coroutine corresponding to the first coroutine according to the stored data structure.

In a possible implementation manner, the processing unit 1002 is further configured to execute the recovery coroutine: and reading the register value of the first coroutine from the data structure corresponding to the first coroutine according to a preset format, and writing the register value into a corresponding register.

In a possible implementation manner, the processing unit 1002 is further configured to save the context of the coroutine restoring program into the data structure; and when the processing unit runs the recovery coroutine, the processing unit is further configured to read a context of the coroutine recovery program from the data structure and run the coroutine recovery program, where the coroutine recovery program is run to read a register value of the first coroutine from the data structure corresponding to the first coroutine according to a preset format and write the register value into a corresponding register.

The device according to the embodiment of the present application may correspond to perform the method described in the embodiment of the present application, and the above and other operations and/or functions of each unit in the apparatus are respectively for implementing corresponding flows of each method in fig. 8 to fig. 9, and are not described herein again for brevity.

Similar to the above concept, as shown in fig. 11, the present application provides a device 1100, where the device 1100 can be applied to one of the network devices in the scenario shown in fig. 4, and performs the steps performed by the main body in the method shown in fig. 8 or fig. 9.

The device 1100 may include a processor 1101 and a memory 1102. Further, the apparatus may further include a communication interface 1104, which may be a transceiver, or a network card. Further, the device 1100 may also include a bus system 1103.

The processor 1101, the memory 1102 and the communication interface 1104 may be connected via the bus system 1103, the memory 1102 may store instructions, and the processor 1101 may be configured to execute the instructions stored in the memory 1102 to control the communication interface 1104 to receive or send a signal, so as to complete the steps of executing the main body in the method shown in fig. 8 or fig. 9.

The memory 1102 may be integrated in the processor 1101 or may be a different physical entity from the processor 1101.

It should be appreciated that the processor 1101 may be a CPU, and that the processor 1101 may also be other general purpose processors, digital signal processors (dspdpsps), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general purpose processor may be a microprocessor or any conventional processor or the like.

The memory 1102 may include both read-only memory and random access memory, and provides instructions and data to the processor 1101. Memory 1102 can also include non-volatile random access memory. For example, memory 1102 may also store device type information.

The memory 1102 may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The non-volatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. Volatile memory can be Random Access Memory (RAM), which acts as external cache memory. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (static RAM, SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and direct bus RAM (DR RAM).

The bus 1103 may include a power bus, a control bus, a status signal bus, and the like, in addition to a data bus. But for purposes of clarity will be identified in the drawings as bus 1103.

As an implementation manner, the function of the communication interface 1104 may be realized by a transceiver circuit or a dedicated chip for transceiving. The processor 1101 may be considered to be implemented by a dedicated processing chip, processing circuit, processor, or general purpose chip.

As another implementation manner, a manner of using a computer may be considered to implement the first computing node or the function of the first computing node provided in the embodiment of the present application. That is, program code that implements the functions of the processor 1101 and the communication interface 1104 is stored in the memory 1102, and a general-purpose processor can implement the functions of the processor 1101 and the communication interface 1104 by executing the code in the memory.

For the concepts, explanations, and detailed descriptions related to the technical solutions provided in the present application and other steps related to the apparatus 1100, reference may be made to the descriptions of the foregoing methods or other embodiments, which are not described herein again.

In an example of the present application, the apparatus 1100 may be configured to execute the steps of the main body in the flow shown in fig. 8 or fig. 9. For example, the communication interface 1104 can receive a detection first data packet; the processor 1101 may respond to the first data packet detected by the communication interface 1104, and when there is no space in the first data structure to record information of a first data stream to which the first data packet belongs, determine whether there is a second data stream, in which information is not updated, in a data stream having a hash value same as that of the first data stream recorded in the first data structure for more than a preset time; if so, the information of the second data stream is replaced with the information of the first data stream.

For the description of the processor 1101 and the communication interface 1104, reference may be made to the description of the flow shown in fig. 8 or fig. 9, and details are not repeated here.

It should be understood that the apparatus 1100 according to the embodiment of the present application may correspond to the apparatus in fig. 10 in the embodiment of the present application, and may correspond to a corresponding main body in executing the method 100 according to the embodiment of the present application, and the above and other operations and/or functions of the respective modules in the apparatus 1100 are respectively for implementing the corresponding flows of the respective methods in fig. 8 to fig. 9, and are not repeated herein for brevity.

The above embodiments may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded or executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains one or more collections of available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. The semiconductor medium may be a Solid State Drive (SSD).

The foregoing is only illustrative of the present application. Those skilled in the art can conceive of changes or substitutions based on the specific embodiments provided in the present application, and all such changes or substitutions are intended to be included within the scope of the present application.

Claims

1. A coroutine handover method is characterized by comprising the following steps:

determining that the first protocol is an overtime protocol, wherein the overtime protocol is a protocol with the operation duration reaching a first threshold;

interrupting the first coroutine;

and switching the second coroutine as the current execution coroutine.

2. The method of claim 1, wherein the determining that the first protocol is a timeout protocol comprises:

starting timing when the first protocol is started;

and when the running time of the first protocol reaches a first threshold, determining that the first protocol is an overtime protocol.

3. The method according to claim 1 or 2, wherein the switching the second coroutine as the current execution coroutine comprises:

selecting the second coroutine, wherein the second coroutine is a coroutine adjacent to the first coroutine in a task queue;

and taking the second coroutine as a current execution coroutine.

4. The method of claim 3, wherein the selecting the second coroutine comprises any one of:

the second coroutine is a coroutine randomly selected from coroutines to be executed and contained in the first thread;

the second coroutine is a coroutine with the highest priority in coroutines to be executed contained in the first thread; or,

the second coroutine is a coroutine obtained by sequencing the coroutines at the current moment in the coroutines to be executed contained in the first thread.

5. The method of any of claims 1-4, wherein said interrupting said first routine comprises:

triggering interrupt processing, the interrupt processing comprising:

and saving the context when the first coroutine is interrupted according to the thread state of the first coroutine, wherein the context is used for indicating the running information when the first thread is interrupted.

6. The method of claim 5, wherein saving the context of the first thread when interrupted based on the state of the first coroutine comprises:

when a first thread where the first coroutine is located is in an interrupt state, storing a register value of the first thread to a kernel shared space, wherein the kernel shared space is a kernel storage space corresponding to the first thread, and the register value is used for recording the running information of the first thread.

7. The method of claim 6, further comprising:

modifying the context returned by the interruption into the context of the coroutine processing program;

executing interrupt return and running the coroutine processing program; and running the coroutine processing program to generate a recovery coroutine corresponding to the first coroutine in an application layer, and executing the recovery coroutine to recover the field when the first coroutine is interrupted.

8. The method of claim 7, further comprising:

and running the recovery coroutine:

and reading the register value of the first coroutine from the data structure corresponding to the first coroutine according to a preset format, and writing the register value into a corresponding register.

9. The method of claim 8, wherein after storing the register value of the first coroutine in a preset format to the data structure corresponding to the first coroutine, and before generating the recovery coroutine corresponding to the first coroutine, further comprising:

saving the context of the coroutine recovery program to the data structure;

running the recovery coroutine, further comprising:

and reading the context of the coroutine recovery program from the data structure, and operating the coroutine recovery program, wherein the coroutine recovery program is used for reading the register value of the first coroutine from the data structure corresponding to the first coroutine according to a preset format, and writing the register value into a corresponding register.

10. An apparatus, characterized in that the apparatus comprises a determining unit, a processing unit:

the determining unit is configured to determine that the first coroutine is an overtime coroutine, where the overtime coroutine is a coroutine whose operation duration reaches a first threshold;

and the processing unit is used for interrupting the first coroutine and switching a second coroutine as a current execution coroutine.

11. The device according to claim 10, wherein the determining unit is specifically configured to start timing when the first routine is started; and when the running time of the first protocol reaches a first threshold, determining that the first protocol is an overtime protocol.

12. The device according to claim 10 or 11, wherein the processing unit is specifically configured to select the second coroutine, where the second coroutine is a coroutine in a task queue that is adjacent to the first coroutine; and taking the second coroutine as a current execution coroutine.

13. The apparatus of claim 12, wherein the second coroutine is a randomly selected one of coroutines to be executed included in the first thread;

the second coroutine is a coroutine with the most front current time sequence in coroutines to be executed contained in the first thread.

14. The device according to any of claims 10 to 13, wherein the processing unit is specifically configured to trigger an interrupt handling, the interrupt handling comprising: and saving the context when the first coroutine is interrupted according to the thread state of the first coroutine, wherein the context is used for indicating the running information when the first thread is interrupted.

15. The device according to claim 14, wherein the processing unit is specifically configured to, when a first thread in which the first coroutine is located is in an interrupt state, store a register value of the first thread into a kernel shared space, where the kernel shared space is a kernel storage space corresponding to the first thread, and the register value is used to record the running information of the first thread.

16. The apparatus of claim 15, wherein the processing unit is further to modify a context returned by the interrupt to be a context of a coroutine handler; executing interrupt return and running the coroutine processing program; and running the coroutine processing program to generate a recovery coroutine corresponding to the first coroutine in an application layer, and executing the recovery coroutine to recover the field when the first coroutine is interrupted.

17. The apparatus of claim 16, wherein the processing unit is further to run the recovery routine to: and reading the register value of the first coroutine from the data structure corresponding to the first coroutine according to a preset format, and writing the register value into a corresponding register.

18. The apparatus of claim 17, wherein the processing unit is further operative to save a context of a coroutine recovery program into the data structure;

and when the processing unit runs the recovery coroutine, the processing unit is further configured to read a context of the coroutine recovery program from the data structure and run the coroutine recovery program, where the coroutine recovery program is run to read a register value of the first coroutine from the data structure corresponding to the first coroutine according to a preset format and write the register value into a corresponding register.

19. An apparatus comprising one or more processors and one or more memories;

the one or more memories coupled to the one or more processors for storing computer program code comprising computer instructions which, when executed by the one or more processors, cause the terminal device to perform the method of any of claims 1-9.