CN114068157A - Semiconductor inductance structure - Google Patents
Semiconductor inductance structure Download PDFInfo
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- CN114068157A CN114068157A CN202010751749.5A CN202010751749A CN114068157A CN 114068157 A CN114068157 A CN 114068157A CN 202010751749 A CN202010751749 A CN 202010751749A CN 114068157 A CN114068157 A CN 114068157A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/34—Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
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Abstract
The invention relates to a semiconductor inductance structure, comprising: the mutual inductance coil comprises a top coil and a bottom coil, wherein the top coil and the bottom coil are positioned on different planes, and mutual inductance is formed between the top coil and the bottom coil; the middle structure is positioned between the top coil and the bottom coil and comprises an interlayer conducting layer and a communicating structure, wherein the communicating structure is used for electrically connecting the interlayer conducting layer with the top coil and the interlayer conducting layer with the bottom coil. Middle structure connects top coil and bottom coil, middle structure includes conducting layer and connectivity structure between the layer, conducting layer and connectivity structure between the layer are conducting structure, magnetic conductivity between them is greater than the air, consequently, the magnetic resistance of magnetic circuit reduces greatly, make the magnetic flux increase between top coil and the bottom coil, then the inductance grow of bottom coil and top coil, after the mutual inductance grow of inductance that bottom coil and bottom coil are constituteed, parasitic inductance diminishes mutual inductance's influence, consequently, the interference that the signal of gathering received also diminishes.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a semiconductor inductor structure.
Background
With the development of the technology, the size of the chip is smaller and smaller, the magnetic flux of the coil of the chip is smaller, the collected signals are greatly influenced by the environment, meanwhile, the chip can generate parasitic inductances, and if the parasitic inductances are equivalent to the inductance of the mutual inductance coil of the collected signals, the collected signals are greatly interfered. However, in the prior art, the magnetic flux of the coil is usually increased by increasing the number of turns of the coil, which inevitably results in an increase in chip area, contrary to the trend of miniaturization of the chip, and in an increase in cost.
Disclosure of Invention
In view of the above, it is necessary to provide a semiconductor inductor structure having an effect of reducing signal acquisition interference.
A semiconductor inductor structure comprising:
the mutual inductance coil comprises a top coil and a bottom coil, wherein the top coil and the bottom coil are positioned on different planes, and mutual inductance is formed between the top coil and the bottom coil;
the middle structure is positioned between the top coil and the bottom coil and comprises an interlayer conducting layer and a communicating structure, wherein the communicating structure is used for electrically connecting the interlayer conducting layer with the top coil and the interlayer conducting layer with the bottom coil.
Through the technical scheme, top layer coil and bottom coil are connected to intermediate structure, intermediate structure includes conducting layer and connectivity structure between the layer, conducting layer and connectivity structure are conducting structure between the layer, both magnetic conductivity is greater than the air, consequently, the magnetic resistance of magnetic circuit reduces greatly, make the magnetic flux increase between top layer coil and the bottom coil, then the inductive reactance grow of bottom coil and top layer coil, after the mutual inductance grow that bottom coil and bottom coil formed, the parasitic inductance that chip self produced diminishes mutual inductance, consequently, the interference that the signal received has also diminished.
In one embodiment, the intermediate structure includes two or more interlayer conductive layers, and the communication structure is configured to electrically connect the interlayer conductive layer and the top layer coil, the interlayer conductive layer and the adjacent interlayer conductive layer, and the interlayer conductive layer and the bottom layer coil.
In one embodiment, the top layer coil and/or the bottom layer coil are back-end metal layers on a device wafer.
In one embodiment, the bottom layer coil and/or the top layer coil is a packaged metal coil.
In one embodiment, the bottom layer coil and the top layer coil are arranged in a column.
In one embodiment, the interlayer conductive layer is a metal layer.
In one embodiment, the communication structure is a metal via.
The present invention also provides a semiconductor inductor structure, comprising:
the inductance coil comprises a plurality of coil layers, the coil layers are arranged in a row, each coil layer is positioned on different planes, and continuous coils are arranged between the adjacent coil layers;
an intermediate structure comprising a plurality of communicating structures for electrically connecting adjacent coil layers.
Through above-mentioned technical scheme, adjacent coil layer is connected to the connectivity structure electricity, the connectivity structure is electrically conductive structure, its magnetic permeability is greater than the air, consequently, the magnetic resistance of magnetic circuit reduces greatly for magnetic flux increase between the adjacent coil layer, then inductance coil's inductance grow, after inductance coil's inductance grow that a plurality of coil layers are constituteed, the influence of the parasitic inductance that chip self produced is to inductance coil diminishes, consequently, the interference that the signal of gathering received has also diminished.
In one embodiment, the coil layer comprises a metal coil layer inside a semiconductor structure.
In one embodiment, the communication structure is a metal via.
Drawings
Fig. 1 is a schematic structural diagram of a semiconductor inductor structure according to an embodiment of the present invention;
fig. 2 is a schematic cross-sectional view of a semiconductor inductor structure according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a semiconductor inductor structure according to another embodiment of the present invention;
fig. 4 is a schematic cross-sectional view of a semiconductor inductor structure according to another embodiment of the present invention.
Reference numerals: 10. a mutual inductance coil; 101. a top layer coil; 102. a bottom layer coil; 11. an intermediate structure; 111. an interlayer conductive layer; 112. a communicating structure; 20. an inductor coil; 201. a coil layer; 21. an intermediate structure; 211. and a communicating structure.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on methods or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
With the development of the technology, the size of the chip is smaller and smaller, the magnetic flux of the coil of the chip is smaller, the collected signals are greatly influenced by the environment, meanwhile, the chip can generate parasitic inductances, and if the parasitic inductances are equivalent to the inductance of the mutual inductance coil of the collected signals, the collected signals are greatly interfered. However, in the prior art, the magnetic flux of the coil is usually increased by increasing the number of turns of the coil, which inevitably results in an increase in chip area, contrary to the trend of miniaturization of the chip, and in an increase in cost.
In order to solve the above problems, as shown in fig. 1 and 2, the present invention provides a semiconductor inductor structure, including: the mutual inductor 10 comprises a top coil 101 and a bottom coil 102, wherein the top coil 101 and the bottom coil 102 are positioned on different planes and form mutual inductance therebetween; the middle structure 11, the middle structure 11 is located between the top coil 101 and the bottom coil 102, and includes an interlayer conductive layer 111 and a communication structure 112, and the communication structure 112 is used to electrically connect the interlayer conductive layer 111 and the top coil 101, and the interlayer conductive layer 111 and the bottom coil 102.
Through the technical scheme, middle structure 11 connects top coil 101 and bottom coil 102, middle structure 11 includes conducting layer 111 and communicating structure 112 between the layer, conducting layer 111 and communicating structure 112 between the layer are electrically conductive structure, both magnetic conductivities are greater than the air, therefore the magnetic resistance of magnetic circuit reduces greatly, make the magnetic flux increase between top coil 101 and bottom coil 102, then bottom coil 102 and top coil 101's inductive reactance grow, after the inductance grow of mutual inductance 10 that bottom coil 102 and bottom coil 102 constitute, the influence of the parasitic inductance that the chip itself produced to mutual inductance 10 diminishes, consequently, the interference that the signal collection received has also diminished.
In an alternative embodiment, the middle structure 11 includes more than two interlayer conductive layers 111, and the communication structure 112 is used to electrically connect the interlayer conductive layers 111 and the top layer coil 101, the interlayer conductive layers 111 and the adjacent interlayer conductive layers 111, and the interlayer conductive layers 111 and the bottom layer coil 102. The intermediate structure 11 may include two interlayer conductive layers 111 and three communication structures 112, and the number of the interlayer conductive layers 111 and the number of the communication structures 112 included in the intermediate structure 11 are determined according to the specific structure of the semiconductor structure in the actual production process.
In an alternative embodiment, the semiconductor inductor structure is located in a semiconductor structure formed by fab process packaging, the top coil 101 is a back-end metal layer on a device wafer, and in this embodiment, the bottom coil 102 may be a packaging metal coil. In an alternative embodiment, the bottom coil 102 is a back-end metal layer on a device wafer, and the top coil 101 is a package metal coil. The back-end metal layer can be made of one or more of metal copper, metal aluminum, metal nickel, metal titanium or metal tungsten; the encapsulated metal coil may be an encapsulated copper coil.
In an alternative embodiment, the bottom layer coils 102 are arranged in a column with the top layer coils 101, the plane of the bottom layer coils 102 is parallel to the plane of the top layer coils 101, and the vertical projection of the top layer coils 101 completely falls on the bottom layer coils 102.
In an alternative embodiment, the interlayer conductive layer 111 is a metal layer, and the metal layer may be made of one or more of metal copper, metal aluminum, metal nickel, metal titanium, or metal tungsten; the communication structure 112 is a metal through hole, and the specific shape of the metal through hole is determined according to actual production conditions. The via structure 112 may be made of one or more of copper metal, aluminum metal, nickel metal, titanium metal, or tungsten metal.
As shown in fig. 3 and 4, the present invention further provides a semiconductor inductor structure, including: the inductance coil 20 comprises a plurality of coil layers 201, the coil layers 201 are arranged in a row, each coil layer 201 is located on different planes, and continuous coils are arranged between adjacent coil layers 201. The intermediate structure 21, the intermediate structure 21 comprises several communication structures 211, the communication structures 211 are used for electrically connecting adjacent coil layers 201.
In an alternative embodiment, the semiconductor inductor structure is formed in a semiconductor structure formed by fan-out type board level packaging (FOPLP) technology, the inductor coil 20 is formed by copper wires, and the through holes in the semiconductor structure form the communication structures 211.
In an alternative embodiment, the coil layer 201 faces the adjacent coil layer 201, a space exists between the adjacent coil layers 201, the communication structure 211 connects the center positions of the adjacent coil layers 201, and the coil layer 201 includes the metal coil layer 201 inside the semiconductor structure, and may be made of one or more of copper, aluminum, nickel, titanium, or tungsten. In an alternative embodiment, the communication structure 211 is a metal through hole, and may be a copper through hole, an aluminum through hole, a nickel through hole, a titanium through hole, or a tungsten through hole.
Through above-mentioned technical scheme, adjacent coil layer 201 is connected to the connectivity structure 211 electricity, the connectivity structure 211 is electrically conductive structure, its magnetic permeability is greater than the air, therefore the magnetic resistance of magnetic circuit reduces greatly, make the magnetic flux increase between the adjacent coil layer 201, then inductance 20's inductance grow, after inductance 20's inductance grow that inductance 201 is constituteed to a plurality of coil layers, the influence of the parasitic inductance that chip self produced is to inductance 20 diminishes, consequently, the interference that the signal of gathering received has also diminished.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A semiconductor inductor structure, comprising:
the mutual inductance coil comprises a top coil and a bottom coil, wherein the top coil and the bottom coil are positioned on different planes, and mutual inductance is formed between the top coil and the bottom coil;
the middle structure is positioned between the top coil and the bottom coil and comprises an interlayer conducting layer and a communicating structure, wherein the communicating structure is used for electrically connecting the interlayer conducting layer with the top coil and the interlayer conducting layer with the bottom coil.
2. The semiconductor inductor structure of claim 1, wherein the intermediate structure comprises more than two interlayer conductive layers, and the via structure is configured to electrically connect the interlayer conductive layer to the top coil, the interlayer conductive layer to the adjacent interlayer conductive layer, and the interlayer conductive layer to the bottom coil.
3. The semiconductor inductor structure of claim 1, wherein the top layer coil and/or the bottom layer coil is a back-end metal layer on a device wafer.
4. The semiconductor inductor structure of claim 1, wherein the bottom layer coil and/or the top layer coil is a packaged metal coil.
5. The semiconductor inductor structure of claim 1, wherein the bottom layer of windings is aligned in a column with the top layer of windings.
6. The semiconductor inductor structure of any one of claims 1-5, wherein the interlayer conductive layer is a metal layer.
7. The semiconductor inductor structure of any one of claims 1-5, wherein the via structure is a metal via.
8. A semiconductor inductor structure, comprising:
the inductance coil comprises a plurality of coil layers, the coil layers are arranged in a row, each coil layer is positioned on different planes, and continuous coils are arranged between the adjacent coil layers;
an intermediate structure comprising a plurality of communicating structures for electrically connecting adjacent coil layers.
9. The semiconductor inductor structure of claim 8, wherein the coil layer comprises a metal coil layer inside the semiconductor structure.
10. The semiconductor inductor structure of any one of claims 8-9, wherein the via structure is a metal via.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010751749.5A CN114068157A (en) | 2020-07-30 | 2020-07-30 | Semiconductor inductance structure |
| PCT/CN2021/087341 WO2022021945A1 (en) | 2020-07-30 | 2021-04-15 | Semiconductor inductance structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010751749.5A CN114068157A (en) | 2020-07-30 | 2020-07-30 | Semiconductor inductance structure |
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| Publication Number | Publication Date |
|---|---|
| CN114068157A true CN114068157A (en) | 2022-02-18 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202010751749.5A Pending CN114068157A (en) | 2020-07-30 | 2020-07-30 | Semiconductor inductance structure |
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| CN (1) | CN114068157A (en) |
| WO (1) | WO2022021945A1 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5610433A (en) * | 1995-03-13 | 1997-03-11 | National Semiconductor Corporation | Multi-turn, multi-level IC inductor with crossovers |
| US7262680B2 (en) * | 2004-02-27 | 2007-08-28 | Illinois Institute Of Technology | Compact inductor with stacked via magnetic cores for integrated circuits |
| CN102087907A (en) * | 2009-12-08 | 2011-06-08 | 上海华虹Nec电子有限公司 | Laminated inductor for enhancing mutual inductance by using metal alignment |
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2020
- 2020-07-30 CN CN202010751749.5A patent/CN114068157A/en active Pending
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2021
- 2021-04-15 WO PCT/CN2021/087341 patent/WO2022021945A1/en active Application Filing
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| WO2022021945A1 (en) | 2022-02-03 |
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