CN114038413A - Pixel driving method and display panel - Google Patents
Pixel driving method and display panel Download PDFInfo
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- CN114038413A CN114038413A CN202111449558.4A CN202111449558A CN114038413A CN 114038413 A CN114038413 A CN 114038413A CN 202111449558 A CN202111449558 A CN 202111449558A CN 114038413 A CN114038413 A CN 114038413A
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- 239000010409 thin film Substances 0.000 claims abstract description 269
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- 241000750042 Vini Species 0.000 description 24
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- 208000033361 autosomal recessive with axonal neuropathy 2 spinocerebellar ataxia Diseases 0.000 description 12
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- 238000010168 coupling process Methods 0.000 description 1
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/04—Maintaining the quality of display appearance
- G09G2320/043—Preventing or counteracting the effects of ageing
- G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
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Abstract
The embodiment of the application discloses a pixel driving circuit and a display panel, the pixel driving circuit comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a first capacitor, a second capacitor and a light-emitting device, and the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor and the sixth thin film transistor are respectively connected to a first scanning line, a second scanning line, a third scanning line, a data signal line, a reset signal line and a control signal line. The pixel driving circuit can effectively compensate and effectively compensate the threshold voltage of the driving thin film transistor, solve the problem of unstable current flowing through the light-emitting device caused by threshold voltage drift, enable the light-emitting brightness of the light-emitting device to be uniform and improve the display effect of pictures.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a pixel driving method and a display panel.
Background
A Micro semiconductor light emitting diode (Micro-LED) is a current-driven type light emitting device, and the light emission luminance of the Micro-LED is determined by a current flowing through the LED itself. The conventional Micro-LED employs Active Matrix (AM), and a pixel driving circuit of the conventional Micro-LED is generally 2T1C, i.e. a structure of two thin film transistors plus a capacitor, which converts a voltage into a current.
As shown in fig. 1 and 2, the conventional pixel driving circuit is a 2T1C structure, which includes a first thin film transistor T1 and a second thin film transistor T2, wherein during a specific operation, when WR is at a high voltage level in a frame (F1), T1 is turned on, and V is set to VdataWriting of signals CstOne terminal of, the data signal VdataDelay t relative to WR0Period, WR Low, T1 off, CstWill VdataUntil T11 turns on again writing a new VdataThe signal is up to. But VdataAt the moment of signal writing, the light emitting device D0Current flows through the device, and the current (I ═ 1/2K (V)GS-Vth)2) The light emitting device is on, can be according to VdataThe difference in value indicates different gray levels. As can be seen from the above equation, the current value of the light emitting device (i.e. the brightness of the LED) and the gate-source voltage V of T2GSAnd a threshold voltage VthAnd (4) correlating.
However, due to the limitation of the tft fabrication process, the V of the driving tft T2 for different pixelsth(i.e., threshold voltage) cannot be guaranteed to be completely uniform, and the driving thin film transistor T2 continues to be biased in the forward direction, resulting in V of the driving thin film transistor T2thIf the shift occurs, under the same condition of other signal inputs, the current flowing through the LEDs in different pixels will also differ, which may cause uneven light emission and brightness among the pixels, and affect the display effect.
Disclosure of Invention
The embodiment of the application provides a pixel driving method and a display panel, which can effectively compensate the threshold voltage of a driving thin film transistor, solve the problem of unstable current flowing through a light-emitting device caused by threshold voltage drift, enable the light-emitting device to have uniform light-emitting brightness, and improve the display effect of pictures.
In one aspect, an embodiment of the present application provides a pixel driving method, including: the light-emitting device comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a first capacitor, a second capacitor and a light-emitting device; the grid electrode of the first thin film transistor is electrically connected to a first node, the source electrode of the first thin film transistor is electrically connected to a second node, and the drain electrode of the first thin film transistor is electrically connected to a third node; the grid electrode of the second thin film transistor is electrically connected to the first scanning line, the source electrode of the second thin film transistor is electrically connected to the second node, and the drain electrode of the second thin film transistor is electrically connected to the first node; a gate of the third thin film transistor is electrically connected to the second scanning line, a source of the third thin film transistor is electrically connected to the reset signal line, and a drain of the third thin film transistor is electrically connected to the third node; a gate of the fourth thin film transistor is electrically connected to the first scanning line, a source of the fourth thin film transistor is electrically connected to a fourth node, and a drain of the fourth thin film transistor is electrically connected to the reset signal line; a gate of the fifth thin film transistor is electrically connected to a third scan line, a source of the fifth thin film transistor is electrically connected to the fourth node, and a drain of the fifth thin film transistor is electrically connected to a data signal line; a gate of the sixth thin film transistor is electrically connected to the control signal line, a drain of the sixth thin film transistor is electrically connected to the second node, and a source of the sixth thin film transistor is electrically connected to the first power supply; a first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the fourth node; a first end of the second capacitor is electrically connected to the first node, and a second end of the second capacitor is electrically connected to the third node; and the anode of the light-emitting device is electrically connected to the third node, and the cathode of the light-emitting device is electrically connected to a second power supply.
Optionally, in some embodiments of the present application, the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, and the fifth thin film transistor are N-type thin film transistors, and the sixth thin film transistor is a P-type thin film transistor.
Optionally, in some embodiments of the present application, the combination of the first scan line, the second scan line, the third scan line, and the control signal line sequentially corresponds to a reset phase, a compensation phase, a data writing phase, and a light emitting phase.
Optionally, in some embodiments of the present application, in the reset phase, the signal supplied by the first scan line is at a high level, the signal supplied by the second scan line is at a high level, the signal supplied by the third scan line is at a low level, and the signal supplied by the control signal line is at a low level.
Optionally, in some embodiments of the present application, in the reset phase, the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, and the sixth thin film transistor are all in an on state, and the fifth thin film transistor is in an off state.
Optionally, in some embodiments of the present application, in the compensation phase, the signal supplied by the first scan line is at a high level, the signal supplied by the second scan line is at a high level, the signal supplied by the third scan line is at a low level, and the signal supplied by the control signal line is at a high level.
Optionally, in some embodiments of the present application, in the compensation phase, the first thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film transistor are all in an on state, and the fifth thin film transistor and the sixth thin film transistor are all in an off state.
Optionally, in some embodiments of the present application, in the data writing phase, the signal supplied by the first scan line is at a low level, the signal supplied by the second scan line is at a high level, the signal supplied by the third scan line is at a high level, and the signal supplied by the control signal line is at a high level.
Optionally, in some embodiments of the present application, in the data writing phase, the first thin film transistor, the third thin film transistor, and the fifth thin film transistor are all in an on state, and the second thin film transistor, the fourth thin film transistor, and the sixth thin film transistor are all in an off state.
Optionally, in some embodiments of the present application, in the light emitting phase, the signal supplied by the first scan line is at a low level, the signal supplied by the second scan line is at a low level, the signal supplied by the third scan line is at a low level, and the signal supplied by the control signal line is at a low level.
Optionally, in some embodiments of the present application, in the light emitting phase, the first thin film transistor and the sixth thin film transistor are in an on state, and the second thin film transistor, the third thin film transistor and the fourth thin film transistor and the fifth thin film transistor are in an off state.
On the other hand, an embodiment of the present application further provides a display device, including: the pixel units are arranged in an array mode and comprise the pixel driving circuit.
The embodiment of the application provides a pixel driving circuit and a display panel, wherein the pixel driving circuit comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a first capacitor, a second capacitor and a light-emitting device, and the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor and the sixth thin film transistor are respectively connected to a first scanning line, a second scanning line, a third scanning line, a data signal line, a reset signal line and a control signal line. The pixel driving circuit can effectively compensate and effectively compensate the threshold voltage of the driving thin film transistor, solve the problem of unstable current flowing through the LED of the light-emitting device caused by threshold voltage drift, ensure the uniformity of the brightness of the light-emitting device and improve the display effect of pictures.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a circuit diagram of a conventional display panel driving circuit having a 2T1C structure;
fig. 2 is a timing diagram of a conventional display panel driving circuit having a 2T1C structure;
fig. 3 is a circuit diagram of a pixel driving circuit provided in an embodiment of the present application;
fig. 4 is a timing diagram of a pixel driving circuit according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a pixel driving circuit in a reset phase according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a pixel driving circuit in a compensation stage according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a pixel driving circuit in a data writing stage according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a pixel driving circuit in a light emitting stage according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
According to the driving method of the display device and the display device, the problem of abnormal display caused by vertical crosstalk of the parasitic capacitance to the pixel unit can be solved by adjusting the gray-scale value of the pixel unit. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments. In addition, in the description of the present application, the term "including" means "including but not limited to". The terms "first," "second," "third," and the like are used merely as labels to distinguish between different objects and not to describe a particular order.
Referring to fig. 3, fig. 3 is a circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure, and as shown in fig. 3, the embodiment of the present disclosure provides a pixel driving circuit including a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, a first capacitor C1, a second capacitor C2, and a light emitting device LED.
In the embodiment of the present invention, the gate of the first thin film transistor T1 is electrically connected to the first node VG, the source of the first thin film transistor T1 is electrically connected to the second node VN, and the drain of the first thin film transistor T1 is electrically connected to the third node VS.
In the embodiment of the present application, the gate of the second thin film transistor T2 is electrically connected to the first Scan line Scan1, the source of the second thin film transistor T2 is electrically connected to the second node VN, and the drain of the second thin film transistor T2 is electrically connected to the first node VG.
In the embodiment of the present application, the gate of the third thin film transistor T3 is electrically connected to the second Scan line Scan2, the source of the third thin film transistor T3 is electrically connected to the reset signal line Vini, and the drain of the third thin film transistor T3 is electrically connected to the third node VS.
In the embodiment of the present invention, the gate of the fourth thin film transistor T4 is electrically connected to the first Scan line Scan1, the source of the fourth thin film transistor T4 is electrically connected to the fourth node VA, and the drain of the fourth thin film transistor T4 is electrically connected to the reset signal line Vini.
In the embodiment of the present application, the gate of the fifth thin film transistor T5 is electrically connected to the third Scan line Scan3, the source of the fifth thin film transistor T5 is electrically connected to the fourth node VA, and the drain of the fifth thin film transistor T5 is electrically connected to the Data line Data.
In the embodiment of the present invention, the gate of the sixth tft T6 is electrically connected to the control signal line EM, the drain of the sixth tft T6 is electrically connected to the second node VN, and the source of the sixth tft T5 is electrically connected to the first power source, preferably, the first power source is the positive power source VDD.
In the embodiment of the present disclosure, a first end of the first capacitor C1 is electrically connected to the first node VG, and a second end of the first capacitor C1 is electrically connected to the fourth node VA.
In the embodiment of the present application, a first end of the second capacitor C2 is electrically connected to the first node VG, and a second end of the second capacitor C2 is electrically connected to the third node VS.
In the embodiment of the present application, the anode of the light emitting device LED is electrically connected to the third node VS, and the cathode of the light emitting device LED is electrically connected to the second power source, preferably, the second power source is the negative electrode VSs of the power source.
In the embodiment of the present application, the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, and the fifth thin film transistor T5 are N-type thin film transistors, and the sixth thin film transistor T6 is a P-type thin film transistor. In the panel display process, since the N-type sixth tft T6 needs to be in a normally open state, a normally high signal needs to be provided to the N-type backplane, i.e., the control signal line EM, which has a high requirement for the IC. In order to reduce the requirement on the IC, an EOA circuit is usually used to convert a normally low signal output by the IC into a normally high signal required by a sixth thin film transistor T6(EM TFT), and the introduction of the EOA circuit increases the risk of driving failure.
In the present application, the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5 and the sixth thin film transistor T6 are used as driving thin film transistors in a pixel driving circuit, and the first Scan line Scan1, the second Scan line Scan2, the third Scan line Scan3, the Data signal line Data, the reset signal line Vini and the control signal line EM are connected, so that the threshold voltage of the driving thin film transistors can be effectively compensated, the problem of unstable current flowing through the light emitting device LED due to drift of the threshold voltage is solved, the uniformity of the light emitting luminance of the light emitting device LED is ensured, and the display effect of the picture is improved.
In the embodiment of the present application, the pixel driving circuit adopts a 6T2C structure, and the first Thin Film Transistor T1 may adopt a Thin Film Transistor (TFT) or a metal oxide semiconductor field effect Transistor (mosfet)
The second thin film Transistor T2, the third thin film Transistor T3, the fourth thin film Transistor T4, the fifth thin film Transistor T5, and the sixth thin film Transistor T6 may all be TFT transistors, or other types of thin film transistors may be set according to specific situations. In the present embodiment, the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, and the sixth thin film transistor T6 each employ a TFT transistor.
The first thin film transistor T1 is used as a driving TFT tube for driving the light emitting device LED to emit light in the pixel driving circuit, and the pixel driving circuit can compensate the threshold voltage of the driving TFT, i.e., the first thin film transistor T1. The first Scan line Scan1, the second Scan line Scan2, the third Scan line Scan3, the reset signal line Vini, and the control signal line EM are all generated by an external timing controller.
As an embodiment of the present application, please refer to fig. 4 to 8, in which fig. 4 is a timing diagram of a pixel driving circuit provided in an embodiment of the present application; fig. 5 is a schematic structural diagram of a pixel driving circuit in a reset phase according to an embodiment of the present disclosure; fig. 6 is a schematic structural diagram of a pixel driving circuit in a compensation stage according to an embodiment of the present disclosure; fig. 7 is a schematic structural diagram of a pixel driving circuit in a data writing stage according to an embodiment of the present disclosure; fig. 8 is a schematic structural diagram of a pixel driving circuit in a light-emitting stage according to an embodiment of the present disclosure; as shown in fig. 4, the combination of the first Scan line Scan1, the second Scan line Scan2, the third Scan line Scan3 and the control signal line EM corresponds to a reset phase, a compensation phase, a data write phase and a light emitting phase in sequence. The potential changes of the first node VG, the third node VS, and the fourth node VA in the reset phase, the compensation phase, the data writing phase, and the light emitting phase are specifically shown in table 1.
TABLE 1 Point voltages of nodes corresponding to stages of the driving circuit
The following is a detailed analysis of potential changes in the reset phase, compensation phase, data write phase, and light emission phase.
In the embodiment of the present application, as shown in fig. 5, in the reset stage, the signal supplied by the first Scan line Scan1 is at a high level, the signal supplied by the second Scan line Scan2 is at a high level, the signal supplied by the control signal line EM is at a low level, the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, and the sixth thin film transistor T6 are all in an on state, the signal supplied by the third Scan line Scan3 is at a low level, the fifth thin film transistor T5 is in an off state, the first node VG is written with the power supply positive voltage VDD, and the third node VS and the fourth node VA are written with the reset voltage Vini, and since the fifth thin film transistor T5 is in an off state, the light emitting device LED does not emit light.
In the embodiment of the present application, as shown in fig. 6, in the compensation phase, the signal supplied by the first Scan line Scan1 is at a high level, the signal supplied by the second Scan line Scan2 is at a high level, the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3 and the fourth thin film transistor T4 are all in an on state, the signal supplied by the third Scan line Scan3 is at a low level, the signal supplied by the control signal line EM is at a high level, the fifth thin film transistor T5 and the sixth thin film transistor T6 are all in an off state, the third node VS and the fourth node VA maintain a reset voltage Vini, and the voltage of the first node VG is changed to a first voltage V1, and V1 is Vini + Vth, where Vini is the reset voltage Vini and is a threshold voltage of the first thin film transistor T1.
Specifically, in the compensation phase, at the moment when the sixth thin film transistor T6 is turned off, the power supply positive voltage VDD written by the first node VG in the reset phase starts to discharge until the gate-source voltage difference of the first thin film transistor T1 is equal to the threshold voltage Vth of the first thin film transistor T1, while the first thin film transistor T1 is turned off, at this moment, the voltage of the first node VG is equal to the sum of the drain voltage (i.e., the reset voltage Vini) of the first thin film transistor T1 and the threshold voltage Vth of the first thin film transistor T1, the voltage of the first node VG does not change, at this moment, the potential voltage of the first node VG includes the threshold voltage Vth information of the first thin film transistor T1, and since the fifth thin film transistor T5 and the sixth thin film transistor T6 are both in the off state, the light emitting device LED does not emit light.
In the embodiment of the present application, as shown in fig. 7, in the data writing phase, the signal supplied by the first Scan line Scan1 is at a low level, the signal supplied by the control signal line EM is at a high level, the second thin film transistor T2, the fourth thin film transistor T4 and the sixth thin film transistor T6 are all in an off state, the signal supplied by the second Scan line Scan2 is at a high level, the signal supplied by the third Scan line Scan3 is at a high level, the first thin film transistor T1, the third thin film transistor T3 and the fifth thin film transistor T5 are all in an on state, the third node VS maintains the reset voltage Vini, the fourth node VA writes the data signal, and the first node VG potential is in a floating state, the first capacitor C1 couples the data signal to the first node VG, and the voltage of the first node VG is changed to the second voltage V2 according to the capacitive coupling principle,
v2 is Vini + Vth + (Data Vini) × [ C1/(C1+ C2) ], where Vini is a reset voltage Vini, Vth is a threshold voltage Vth of the first thin film transistor T1, Data is a Data signal, C1 is a capacitance value of the first capacitor C1, and C2 is a capacitance value of the second capacitor C2.
In the embodiment of the present application, as shown in fig. 8, in the light emitting phase, the signal supplied by the first Scan line Scan1 is at a low level, the signal supplied by the second Scan line Scan2 is at a low level, the signal supplied by the third Scan line Scan3 is at a low level, the signal supplied by the control signal line EM is at a low level, the first thin film transistor T1 and the sixth thin film transistor T6 are both in an on state, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, and the fifth thin film transistor T5 are all in an off state, the second node VN and the third node VS write the power supply positive voltage VDD, the second voltage V2 of the first node VG is consumed, the second voltage V2 includes the threshold voltage Vth information of the first thin film transistor T1, and the light emitting device LED emits light, thereby achieving the effect of compensating the threshold voltage VG of the first thin film transistor T1.
On the other hand, the present application also provides a pixel driving method, as shown in fig. 5 to 8, based on the pixel driving circuit, the driving method includes steps S10 to S50:
s10, providing a pixel driving circuit;
the driving circuit includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, a first capacitor C1, a second capacitor C2, and a light emitting device LED.
S20, as shown in fig. 5, the reset stage is entered, the first Scan line Scan1 provides a high level signal, the second Scan line Scan2 provides a high level signal, the control signal line EM provides a low level signal, the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, and the sixth thin film transistor T6 are all in an on state, the third Scan line Scan3 provides a low level signal, the fifth thin film transistor T5 is in an off state, the first node VG is written with the positive voltage of the power supply VDD, and the third node VS and the fourth node VA are written with the reset voltage Vini.
S30, as shown in fig. 6, entering a compensation phase, the first Scan line Scan1 provides a high level signal, the second Scan line Scan2 provides a high level signal, the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3 and the fourth thin film transistor T4 are all in an on state, the third Scan line Scan3 provides a low level signal, the control signal line EM provides a high level signal, the fifth thin film transistor T5 and the sixth thin film transistor T6 are all in an off state, the third node VS and the fourth node VA maintain a reset voltage Vini, and the voltage of the first node VG changes to a first voltage V1, V1 is Vini + Vth, where Vini is the reset voltage Vini and Vth is the threshold voltage of the first thin film transistor T1.
S40, as shown in fig. 7, entering the Data writing phase, the first Scan line Scan1 provides a low level signal, the control signal line EM provides a high level signal, the second thin film transistor T2, the fourth thin film transistor T4 and the sixth thin film transistor T6 are all in the off state, the second Scan line Scan2 provides a high level signal, the third Scan line Scan3 provides a high level signal, the first thin film transistor T1, the third thin film transistor T3 and the fifth switching tube T5 are all in the on state, the third node VS maintains the reset voltage Vini, the fourth node VA writes the Data signal, while the first capacitor C1 couples the Data signal to the first node VG, the voltage of the first node VG changes to the second voltage V2, V2 is Vini + Data (Vini Data) [ C1/(C1+ C2), where Vini is the reset voltage, Vth is the first threshold voltage of the first thin film transistor T3842, and the Data line Scan line EM 1 is the high level signal, c1 is the capacitance of the first capacitor C1, and C2 is the capacitance of the second capacitor C2.
S50, as shown in fig. 8, in the light emitting stage, the first Scan line Scan1 provides a low level signal, the second Scan line Scan2 provides a low level signal, the third Scan line Scan3 provides a low level signal, the control signal line EM provides a low level signal, the first thin film transistor T1 and the sixth thin film transistor T6 are both in the on state, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, and the fifth thin film transistor T5 are all in the off state, the second node VN and the third node VS write the power supply positive voltage VDD, the second voltage V2 of the first node VG is consumed, the second voltage V2 includes the threshold voltage Vth of the first thin film transistor T1, and the light emitting device LED emits light.
On the other hand, the present application further provides a display panel, which includes a plurality of pixel units arranged in an array, where the pixel units include the pixel driving circuit as described above. The application provides a display panel, through improving current pixel drive circuit, can effectively compensate the threshold voltage who drives thin film transistor of effective compensation, solve the unstable problem of the electric current that flows through luminescent device LED that leads to by threshold voltage drift, guarantee that luminescent device's luminance is even, improve the display effect of picture.
The foregoing detailed description is directed to a display device provided in an embodiment of the present application, and specific examples are used herein to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (12)
1. A pixel driving circuit, comprising: the light-emitting device comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a first capacitor, a second capacitor and a light-emitting device;
the grid electrode of the first thin film transistor is electrically connected to a first node, the source electrode of the first thin film transistor is electrically connected to a second node, and the drain electrode of the first thin film transistor is electrically connected to a third node;
the grid electrode of the second thin film transistor is electrically connected to the first scanning line, the source electrode of the second thin film transistor is electrically connected to the second node, and the drain electrode of the second thin film transistor is electrically connected to the first node;
a gate of the third thin film transistor is electrically connected to the second scanning line, a source of the third thin film transistor is electrically connected to the reset signal line, and a drain of the third thin film transistor is electrically connected to the third node;
a gate of the fourth thin film transistor is electrically connected to the first scanning line, a source of the fourth thin film transistor is electrically connected to a fourth node, and a drain of the fourth thin film transistor is electrically connected to the reset signal line;
a gate of the fifth thin film transistor is electrically connected to a third scan line, a source of the fifth thin film transistor is electrically connected to the fourth node, and a drain of the fifth thin film transistor is electrically connected to a data signal line;
a gate of the sixth thin film transistor is electrically connected to the control signal line, a drain of the sixth thin film transistor is electrically connected to the second node, and a source of the sixth thin film transistor is electrically connected to the first power supply;
a first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the fourth node;
a first end of the second capacitor is electrically connected to the first node, and a second end of the second capacitor is electrically connected to the third node;
and the anode of the light-emitting device is electrically connected to the third node, and the cathode of the light-emitting device is electrically connected to a second power supply.
2. The pixel driving circuit according to claim 1, wherein the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, and the fifth thin film transistor are N-type thin film transistors, and the sixth thin film transistor is a P-type thin film transistor.
3. The pixel driving circuit according to claim 2, wherein the first scan line, the second scan line, the third scan line, and the control signal line in combination correspond to a reset phase, a compensation phase, a data writing phase, and a light emitting phase in sequence.
4. The pixel driving circuit according to claim 3, wherein in the reset phase, the signal supplied from the first scan line is at a high level, the signal supplied from the second scan line is at a high level, the signal supplied from the third scan line is at a low level, and the signal supplied from the control signal line is at a low level.
5. The pixel driving circuit according to claim 4, wherein in the reset phase, the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, and the sixth thin film transistor are all in an on state, and the fifth thin film transistor is in an off state.
6. The pixel driving circuit according to claim 3, wherein in the compensation phase, the signal supplied from the first scan line is at a high level, the signal supplied from the second scan line is at a high level, the signal supplied from the third scan line is at a low level, and the signal supplied from the control signal line is at a high level.
7. The pixel driving circuit according to claim 6, wherein in the compensation phase, the first thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film transistor are all in an on state, and the fifth thin film transistor and the sixth thin film transistor are all in an off state.
8. The pixel driving circuit according to claim 3, wherein in the data writing phase, the signal supplied from the first scan line is at a low level, the signal supplied from the second scan line is at a high level, the signal supplied from the third scan line is at a high level, and the signal supplied from the control signal line is at a high level.
9. The pixel driving circuit according to claim 8, wherein in the data writing phase, the first thin film transistor, the third thin film transistor, and the fifth thin film transistor are all in an on state, and the second thin film transistor, the fourth thin film transistor, and the sixth thin film transistor are all in an off state.
10. The pixel driving circuit according to claim 3, wherein in the light emitting period, the signal supplied from the first scanning line is at a low level, the signal supplied from the second scanning line is at a low level, the signal supplied from the third scanning line is at a low level, and the signal supplied from the control signal line is at a low level.
11. The pixel driving circuit according to claim 10, wherein in the light emitting period, the first thin film transistor and the sixth thin film transistor are in an on state, and the second thin film transistor, the third thin film transistor and the fourth thin film transistor and the fifth thin film transistor are in an off state.
12. A display panel, comprising: a plurality of pixel cells arranged in an array, the pixel cells comprising a pixel drive circuit as claimed in any one of claims 1 to 11.
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| CN202111449558.4A CN114038413A (en) | 2021-11-30 | 2021-11-30 | Pixel driving method and display panel |
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| CN202111449558.4A CN114038413A (en) | 2021-11-30 | 2021-11-30 | Pixel driving method and display panel |
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| CN114708825A (en) * | 2022-04-22 | 2022-07-05 | Tcl华星光电技术有限公司 | Pixel circuit and display panel |
| CN115101012A (en) * | 2022-07-06 | 2022-09-23 | 北京欧铼德微电子技术有限公司 | Pixel compensation circuit, system and method |
| WO2023201678A1 (en) * | 2022-04-22 | 2023-10-26 | 京东方科技集团股份有限公司 | Pixel circuit and driving method therefor, and display panel and display apparatus |
| WO2023226083A1 (en) * | 2022-05-27 | 2023-11-30 | 惠州华星光电显示有限公司 | Pixel driving circuit, pixel driving method, and display panel |
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| CN113593473A (en) * | 2021-08-05 | 2021-11-02 | 深圳市华星光电半导体显示技术有限公司 | Display panel driving circuit and driving method |
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| CN114708825A (en) * | 2022-04-22 | 2022-07-05 | Tcl华星光电技术有限公司 | Pixel circuit and display panel |
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Application publication date: 20220211 |