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CN114023707A - Fan-out type packaging structure and forming method thereof - Google Patents

Fan-out type packaging structure and forming method thereof Download PDF

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Publication number
CN114023707A
CN114023707A CN202111098968.9A CN202111098968A CN114023707A CN 114023707 A CN114023707 A CN 114023707A CN 202111098968 A CN202111098968 A CN 202111098968A CN 114023707 A CN114023707 A CN 114023707A
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CN
China
Prior art keywords
electronic component
electronic
fan
layer
package structure
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Pending
Application number
CN202111098968.9A
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Chinese (zh)
Inventor
方绪南
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Priority to CN202111098968.9A priority Critical patent/CN114023707A/en
Publication of CN114023707A publication Critical patent/CN114023707A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

An embodiment of the present invention provides a fan-out package structure, including: a first electronic component and a second electronic component arranged side by side; and a dummy chip continuously covering the first electronic component and the second electronic component, wherein the crystal lattices between the silicon of the first electronic component and the silicon of the second electronic component and the silicon of the dummy chip are continuous at the interface where the dummy chip is bonded to the first electronic component and the second electronic component. The invention aims to provide a fan-out type packaging structure and a forming method thereof, so as to improve the yield of the fan-out type packaging structure.

Description

Fan-out type packaging structure and forming method thereof
Technical Field
Embodiments of the present application relate to fan-out package structures and methods of forming the same.
Background
In the fan-out package structure, the Coefficient of Thermal Expansion (CTE) of each material structure in the package is not matched, so that the package may warp under the influence of thermal stress during thermal cycling, and the thermal stress cannot be directly released, so that the structure with low rigidity is easy to crack all the time, and further the adjacent structure is extended and damaged.
Disclosure of Invention
In view of the problems in the related art, an object of the present invention is to provide a fan-out package structure and a method for forming the same, so as to improve the yield of the fan-out package structure.
To achieve the above object, an embodiment of the present invention provides a fan-out package structure, including: a first electronic component and a second electronic component arranged side by side; and a dummy chip continuously covering the first electronic component and the second electronic component, wherein the crystal lattices between the silicon of the first electronic component and the silicon of the second electronic component and the silicon of the dummy chip are continuous at the interface where the dummy chip is bonded to the first electronic component and the second electronic component.
In some embodiments, the dummy chip and the first and second electronic elements have an air gap therebetween.
In some embodiments, further comprising: and the filling layer is positioned between the first electronic element and the second electronic element.
In some embodiments, the dummy chip also engages the fill layer.
In some embodiments, there is a gap between the dummy chip and the fill layer.
In some embodiments, the second electronic component includes an encapsulation layer disposed at the periphery, and a portion of the encapsulation layer in contact with the filling layer is spaced apart from the dummy chip.
In some embodiments, a top surface of a portion of the encapsulation layer in contact with the fill layer is flush with a top surface of the fill layer.
In some embodiments, further comprising: and the circuit layer is positioned below the first electronic element and the second electronic element, and the first connecting piece of the first electronic element and the second connecting piece of the second electronic element are jointed with the circuit layer.
In some embodiments, the filling layer is further located between the first electronic element, the second electronic element and the circuit layer, and covers the first connecting piece and the second connecting piece.
In some embodiments, further comprising: and the molding compound is positioned on the circuit layer and covers the outer side walls of the first electronic element and the second electronic element.
Embodiments of the present application also provide a method of forming a fan-out package structure, comprising: disposing a first electronic component and a second electronic component on the wiring layer; forming a filling layer for coating the first electronic element and the second electronic element; forming a molding compound that encapsulates the first electronic component, the second electronic component, and the fill layer; grinding the upper surface of the first electronic element and the upper surface of the second electronic element to ensure that the surface flatness of the upper surfaces of the first electronic element and the second electronic element is less than 50 nm; forming a dummy chip on an upper surface of the first electronic component and an upper surface of the second electronic component; and annealing the interfaces of the first electronic element, the second electronic element and the pseudo chip.
In some embodiments, the roughness of the lower surface of the dummy chip is less than 50 nm.
In some embodiments, the temperature of the anneal is 150 ° to 300 °.
In some embodiments, the top of the fill layer is removed after grinding the upper surface of the first electronic component and the upper surface of the second electronic component and before forming the dummy chip.
In some embodiments, the dummy chip also contacts the fill layer.
In some embodiments, the sidewalls of the dummy chip are flush with the outer sidewalls of the first and second electronic elements.
In some embodiments, after forming the mold compound, the mold compound is formed on top surfaces of the first electronic component and the second electronic component, and after grinding the upper surface of the first electronic component and the upper surface of the second electronic component, the upper surface of the mold compound is flush with the upper surface of the first electronic component and the upper surface of the second electronic component.
In some embodiments, after annealing, the crystal lattice between the silicon of the first electronic element and the silicon of the second electronic element and the silicon of the dummy chip is continuous.
In some embodiments, the filling layer is formed between the first electronic element, the second electronic element and the circuit layer, and the filling layer covers part of the outer side walls of the first electronic element and the second electronic element.
In some embodiments, the line layer is flush with the sidewalls of the molding compound.
Drawings
Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.
Fig. 1-9 illustrate a process of forming a fan-out package structure according to an embodiment of the present application.
Fig. 10-12 illustrate fan-out package structures according to various embodiments of the present application.
Detailed Description
In order to better understand the spirit of the embodiments of the present application, the following further description is given in conjunction with some preferred embodiments of the present application.
Embodiments of the present application will be described in detail below. Throughout the specification, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the figures are illustrative in nature, are diagrammatic in nature, and are used to provide a basic understanding of the present application. The embodiments of the present application should not be construed as limiting the present application.
As used herein, the terms "substantially", "substantially" and "about" are used to describe and illustrate minor variations. When used in conjunction with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the term can refer to a range of variation that is less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, two numerical values are considered to be "substantially" identical if the difference between the two numerical values is less than or equal to ± 10% (e.g., less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%) of the mean of the values.
In this specification, unless specified or limited otherwise, relative terms such as: terms of "central," "longitudinal," "lateral," "front," "rear," "right," "left," "inner," "outer," "lower," "upper," "horizontal," "vertical," "above," "below," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the orientation as then described in the discussion or as shown in the drawing figures. These relative terms are for convenience of description only and do not require that the present application be constructed or operated in a particular orientation.
Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.
Moreover, for convenience in description, "first," "second," "third," etc. may be used herein to distinguish between different elements of a figure or series of figures. "first," "second," "third," etc. are not intended to describe corresponding components.
The fan-out Chip-on-Substrate (FOCOS) packaging structure is formed by replacing a traditional 2.5D (dimension) silicon insert with a fan-out circuit layer/redistribution layer (RDL) to achieve the aim of low cost, but because the RDL is thin, the overall rigidity of the material of the RDL is insufficient, and the CTE of the RDL is far larger than that of a through silicon insert, the warpage in a subsequent thermal process is larger than that of a Chip-on-Wafer-on-Substrate (CoWs) packaging structure on a Substrate, and therefore cracks are easily generated in a filling layer with lower rigidity, and even the cracks are expanded to extend into the RDL to damage the RDL. If the thickness or number of layers of the RDL is increased, the overall strength of the RDL may be increased, but the overall RDL may be warped, which may affect the subsequent processes. The existing filling material can not effectively improve the problem of insufficient structural strength of the product.
The fan-out package structure and the forming method thereof will be described in detail below with reference to the accompanying drawings.
Referring to fig. 1, a wiring layer 10 is disposed on a carrier substrate 12. In some embodiments, the wiring layer 10 is an RDL or a wafer. In some embodiments, the CTE of the wiring layer 10 is 20. In some embodiments, the carrier substrate 12 may be a glass carrier substrate, a ceramic carrier substrate, a wafer, or the like. In some embodiments, there is a release layer (not shown) between the carrier substrate 12 and the wiring layer 10, which may be formed of a polymer-based material that may be removed from the carrier substrate 12 in a subsequent step. In some embodiments, the release layer is an epoxy-based thermal release material that loses its adhesion upon heating, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer may be an Ultraviolet (UV) glue that loses its adhesion when exposed to UV light. The release layer may be dispensed in liquid form and cured, may be a laminated film laminated on the carrier substrate 12, or may be similar.
Referring to fig. 2, a first electronic component 20 and a second electronic component 22 are formed on the wiring layer 10.
In some embodiments, first electronic component 20 and second electronic component 22 are chips. In some embodiments, the first electronic component 20 is an Application Specific Integrated Circuit (ASIC) chip and the second electronic component 22 is a High Bandwidth Memory (HBM) chip. In some embodiments, the CTE of the first electronic component 20 and the second electronic component 22 is 2.8-3. In some embodiments, a plurality of second electronic components 22 are positioned around the first electronic component 20.
Referring to fig. 3, the first electronic component 20 and the second electronic component 22 are encapsulated with a filler layer 30. In some embodiments, the first electronic component 20 and the second electronic component 22 are separated by a filler layer 30. In some embodiments, the filler layer 30 includes or underfills (underfills). in some embodiments, the filler layer 30 is also located between the first electronic component 20, the second electronic component 22, and the wiring layer 10 and covers the first connectors 32 of the first electronic component 20 and the second connectors 34 of the second electronic component 22. In some embodiments, the filler layer 30 also encapsulates portions of the outer sidewalls of the first and second electronic elements 20 and 22. In some embodiments, the CTE of the fill layer 30 is 20.
In some embodiments, the filler layer 30 is only located between the first electronic component 20 and the second electronic component 22, an adhesive layer (not shown) is located between the first electronic component 20, the second electronic component 22, and the wiring layer 10, and the first connection 32 of the first electronic component 20 and the second connection 34 of the second electronic component 22 pass through the adhesive layer. In some embodiments, the Coefficient of Thermal Expansion (CTE) of the filler layer 30 and the adhesive layer are different. In some embodiments, the material of the adhesive layer includes Polyimide (PI). In some embodiments, the CTE of the adhesion layer is 20.
Referring to fig. 4, a molding Compound (CPD)40 is formed to encapsulate the first electronic component 20, the second electronic component 22, and the filling layer 30, the molding compound 40 being located on the wiring layer 10. In some embodiments, the CTE of the molding compound 40 is 12.
Referring to fig. 5, the grinding removes portions of the mold compound 40 that are located on the first and second electronic components 20 and 22, and grinds the upper surfaces of the first and second electronic components 20 and 22 to a surface flatness of less than 50nm, parallelism of less than 0.2 μm, and roughness of less than 100 μm. In some embodiments, Z1 (rough grinding), Z2 (fine grinding), and Z3 (polishing) are performed at the time of grinding so that the roughness of the upper surface of the first electronic component 20 and the upper surface of the second electronic component 22 is less than 3nm and the flatness is between 2nm and 3 nm.
Referring to fig. 6, the dummy chip 60 is disposed on the first and second electronic components 20 and 22, and the surface flatness of the lower surface of the dummy chip 60 is less than 50 nm. In some embodiments, the surface flatness of the lower surface of the dummy chip 60 is between 2nm and 3 nm. In some embodiments, the sidewalls of the dummy chip 60 are flush with the outer sidewalls of the first and second electronic components 20 and 22.
Referring to fig. 7, an annealing process is performed such that the lattices between the silicon of the first electronic component 20 and the second electronic component 22 and the silicon of the dummy chip 60 are continuous and the connection strength is large.
Referring to fig. 8, the carrier substrate 12 is removed.
Referring to fig. 9, bumps 90 are formed on the backside of the wiring layer 10. In some embodiments, the bumps 90 are Controlled Collapse Chip Connection (C4) bumps. Thus, the fan-out package structure 900 of the embodiment of the present application is formed. Fig. 1 to 9 illustrate a single fan-out package structure as an example, in actual production, a plurality of fan-out package structures are formed at the same time, and a singulation process (e.g., dicing) is performed after the step of fig. 9 to form a plurality of singulated fan-out package structures.
Fig. 10 shows an embodiment different from fig. 9, in fig. 10, an air gap 100 is provided between the dummy chip 60 and the first and second electronic components 20 and 22.
Fig. 11 shows an embodiment different from fig. 10, in fig. 11, a gap 110 is provided between the dummy chip 60 and the filling layer 30. In the embodiment shown in fig. 11, the top of the fill layer 30 is removed (e.g., by laser drilling) after the upper surface of the first electronic component 20 and the upper surface of the second electronic component 22 are ground as shown in fig. 5 and before the dummy chip 60 is formed as shown in fig. 6. The gap 110 allows room for the subsequent fill layer 30 to expand when heated.
Fig. 12, which shows a different embodiment from fig. 11, in some embodiments the second electronic component 22 comprises an encapsulation layer 23 arranged at the periphery, the portion of the encapsulation layer 23 in contact with the filling layer 30 being spaced apart from the dummy chip 60. In some embodiments, the top surface of the portion of the encapsulation layer 23 in contact with the fill layer 30 is flush with the top surface of the fill layer 30.
In the embodiment of the present application, the regions of the filling layer 30 prone to cracking (e.g., between the first electronic component 20 and the second electronic component 22, and between the first electronic component 20 and the second electronic component 22 and the wiring layer 10) are all located under the coverage surface of the silicon, and the dummy chip 60 covers the excessive half area of the first electronic component 20 and the second electronic component 22, and the silicon strength is sufficient to overcome the warpage deformation, so as to avoid the generation of cracks in the filling layer 30.
The embodiment of the present application performs grinding after forming the first electronic component 20 and the second electronic component 22 and performs a Z3 (polishing) process after the grinding, and controls the roughness of the surface after polishing to be less than 3nm and the flatness to be between 2nm and 3 nm. Providing a dummy chip 60 on the polished surface, bonding the first electronic component 20, the second electronic component 22 and the dummy chip 60 by using a capillary force (interatomic attraction force-van der waals force) between the silicon atom of the first electronic component 20 and the silicon atom of the second electronic component 22 and the silicon atom of the dummy chip 60, and performing an annealing process (temperature between 150 ℃ and 300 ℃) such that lattices between the silicon of the first electronic component 20 and the silicon of the second electronic component 22 and the silicon of the dummy chip 60 are continuous, and the silicon of the first electronic component 20 and the silicon of the second electronic component 22 and the silicon of the dummy chip 60 are diffused each other, the interfaces are connected to each other without any medium, and the connection strength is stronger than when using other media (e.g., adhesive paste, etc.).
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A fan-out package structure, comprising:
a first electronic component and a second electronic component arranged side by side;
and a dummy chip continuously covering the first electronic component and the second electronic component, wherein a crystal lattice between silicon of the first electronic component and silicon of the second electronic component and silicon of the dummy chip is continuous at an interface where the dummy chip and the first and second electronic components are bonded.
2. The fan-out package structure of claim 1, wherein an air gap is provided between the dummy die and the first and second electronic components.
3. The fan-out package structure of claim 1, further comprising:
a fill layer between the first electronic component and the second electronic component.
4. The fan-out package structure of claim 3, wherein the dummy die further engages the fill layer.
5. The fan-out package structure of claim 3, wherein a gap is between the dummy die and the fill layer.
6. The fan-out package structure of claim 5, wherein the second electronic component comprises an encapsulation layer disposed at a periphery, a portion of the encapsulation layer in contact with the filler layer being spaced apart from the dummy chip.
7. The fan-out package structure of claim 3, further comprising:
and the circuit layer is positioned below the first electronic element and the second electronic element, and the first connecting piece of the first electronic element and the second connecting piece of the second electronic element are jointed with the circuit layer.
8. The fan-out package structure of claim 7, wherein the filler layer is further located between the first electronic component, the second electronic component, and the wiring layer, the filler layer encasing the first connector and the second connector.
9. The fan-out package structure of claim 7, further comprising:
and the molding compound is positioned on the circuit layer and coats the outer side walls of the first electronic element and the second electronic element.
10. A method of forming a fan-out package structure, comprising:
disposing a first electronic component and a second electronic component on the wiring layer;
forming a filling layer which coats the first electronic element and the second electronic element;
forming a molding compound encasing the first electronic component, the second electronic component, and the fill layer;
grinding the upper surface of the first electronic element and the upper surface of the second electronic element to enable the surface flatness of the upper surface of the first electronic element and the upper surface of the second electronic element to be less than 50 nm;
forming a dummy chip on an upper surface of the first electronic component and an upper surface of the second electronic component;
and annealing the interfaces of the first electronic element, the second electronic element and the pseudo chip, wherein the annealing temperature is 150-300 ℃.
CN202111098968.9A 2021-09-18 2021-09-18 Fan-out type packaging structure and forming method thereof Pending CN114023707A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111098968.9A CN114023707A (en) 2021-09-18 2021-09-18 Fan-out type packaging structure and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111098968.9A CN114023707A (en) 2021-09-18 2021-09-18 Fan-out type packaging structure and forming method thereof

Publications (1)

Publication Number Publication Date
CN114023707A true CN114023707A (en) 2022-02-08

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CN202111098968.9A Pending CN114023707A (en) 2021-09-18 2021-09-18 Fan-out type packaging structure and forming method thereof

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CN (1) CN114023707A (en)

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