CN114006644A - Method for realizing satellite measurement and control simulator based on PXI bus - Google Patents
Method for realizing satellite measurement and control simulator based on PXI bus Download PDFInfo
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Abstract
The invention relates to the technical field of satellite simulators, in particular to a method for realizing a satellite measurement and control simulator based on a PXI bus, which adopts the PXI bus, can realize the measurement and control channel function by using 1 standard 3U board card through minimum design, can be flexibly combined with other subsystem simulators, and can realize the simulation task requirements of satellites with various models; the method comprises the following steps: s1, designing a hardware platform: the measurement and control simulator board card takes a digital signal processing chip as a core and mainly comprises a high-speed A/D conversion circuit, an AGC gain control circuit, a large-scale FPGA device, a D/A conversion circuit, a clock management circuit, a power supply management circuit, an interface circuit and the like; the system comprises an uplink channel and a downlink channel, and realizes the minimum design of core functions; the board card realizes system communication by using a PXI bus chip, and finishes information interaction work with a PC (personal computer) through a PXI interface; and S2, designing a digital signal processing module.
Description
Technical Field
The invention relates to the technical field of satellite simulators, in particular to a method for realizing a satellite measurement and control simulator based on a PXI bus.
Background
The satellite simulator is used for simulating each subsystem of the satellite, and comprises a measurement and control subsystem, a satellite affair subsystem, a power supply and distribution subsystem and the like, and the simulator reflects the real state of the satellite as much as possible. The measurement and control simulator is an important component of the satellite simulator, and is mainly used for checking and verifying the working states of telemetering receiving and remote control instruction sending of the ground measurement and control system, improving the emergency processing capability of the ground measurement and control system on satellite faults, verifying the correctness of ground measurement and control system equipment, serving as a tested object for user training and helping a user to be familiar with the normal measurement and control process of the satellite and the emergency processing method under the fault condition.
The PXI bus is a high-performance open, modular instrumentation bus that has evolved from the PCI bus technology defined in the Compact PCI specification, with prominent features in terms of system integration, compatibility, generalization, modularity, and system cost.
The prior satellite simulator has the following defects: the customization mode is mainly adopted, the development efficiency is low, the generalization degree is low, the system framework is relatively closed, and the maintenance and the function expansion are not facilitated; and the developed component modules are difficult to reuse and low in utilization rate.
Disclosure of Invention
In order to solve the technical problems, the invention provides a method for realizing a satellite measurement and control simulator based on a PXI bus, which adopts the PXI bus, can realize the measurement and control channel function by using 1 standard 3U board card through a minimum design, can be flexibly combined with other subsystem simulators, and meets the simulation task requirements of satellites with various models.
The invention discloses a method for realizing a PXI bus-based satellite measurement and control simulator, which comprises the following steps of:
s1, designing a hardware platform: the measurement and control simulator board card takes a digital signal processing chip as a core and mainly comprises a high-speed A/D conversion circuit, an AGC gain control circuit, a large-scale FPGA device, a D/A conversion circuit, a clock management circuit, a power supply management circuit, an interface circuit and the like; the system comprises an uplink channel and a downlink channel, and realizes the minimum design of core functions; the board card realizes system communication by using a PXI bus chip, and finishes information interaction work with a PC (personal computer) through a PXI interface;
and S2, designing a digital signal processing module.
The invention relates to a realization method of a PXI bus-based satellite measurement and control simulator, wherein a large-scale FPGA device in step S1 is a main device for baseband signal processing, and not only carries digital up-down frequency conversion and data preprocessing tasks, but also needs to complete the receiving, caching and control command receiving and sending of high-speed data; for a receiving channel, the FPGA receives data after high-speed A/D conversion through a high-speed parallel interface, firstly carries out down-conversion on the data to a baseband, including NCO, filtering, extraction, frequency point selection and the like, and then carries out pretreatment on the baseband data according to needs, such as signal synchronization, correlation and the like; for a transmitting channel, the FPGA firstly preprocesses data acquired from central control software, then up-converts the data to intermediate frequency, and then sends the intermediate frequency to a front end D/A (digital/analog) to transmit the intermediate frequency to a radio frequency; the FPGA is also responsible for the control function of the PXI interface;
high-speed A/D conversion: the input signal of the intermediate frequency acquisition circuit is 70MHz, according to Nyquist sampling theorem, if the intermediate frequency is directly subjected to low-pass sampling, the sampling clock at least needs 140MHz to ensure that frequency spectrums are not overlapped, but the sampling rate is too high to cause great pressure on subsequent signal processing, and because the bandwidth of the intermediate frequency signal is 10MHz, the intermediate frequency band-pass sampling design is adopted; LTC2252 adopted by the analog-to-digital conversion part is a 12-bit 125Msps low-power-consumption A/D converter and is specially designed for carrying out digital processing on high-frequency and wide-dynamic-range signals; LTC2252 is well suited for demanding imaging and communications applications with AC performance SNR of 70.1dB, spurious free dynamic range (SFDR for signals at nyquist frequency) of 85 dB; the DC specification includes + -0.3 LSBINL (typical values), + -0.15 LSBDNL (typical values) and missing-free codes over the entire temperature range;
an AGC gain control circuit: the signal strength of the input end of the intermediate frequency receiving unit is small, and the dynamic range is wide, so that a gain control system needs to be added at the front end to ensure that the signal reaching the ADC is not saturated and has enough conversion bits, so that the demodulated input signal is stable;
PXI bus chip: the PXI interface control is realized by adopting a mode of controlling a PXI interface chip by using the FPGA; the FPGA is responsible for communicating with a local port between the interface chips, realizes a local bus control function, and is used for responding extension signals such as a trigger signal, a reference clock and the like in the PXI bus and performing other time sequence operation and control;
clock management: an external input clock synchronization interface circuit is designed by integrated board card, external 10MHz synchronization signal is introduced, the circuit detects the external clock input condition through FPGA, if there is external clock input, the system uses external clock mode, if there is no external clock input, the system generates 10MHz clock signal.
The invention discloses a method for realizing a PXI bus-based satellite measurement and control simulator, which comprises the following steps of S2:
(a) modulation transmission module design
The modulation module is mainly used for completing modulation and transmission of a telemetering signal, outputting a 70MHz intermediate frequency PM modulation signal, and has the functions of carrier frequency Doppler presetting, telemetering and ranging subcarrier adding and demodulating control, subcarrier modulation degree adjustment and the like; receiving a control instruction through a parameter control module, and transmitting corresponding configuration parameters to each unit of a software module to realize the configuration of parameters such as telemetry code rate, telemetry subcarrier frequency, telemetry modulation degree, intermediate frequency output frequency, telemetry signal code type, telemetry frame length, frame synchronization head, synchronization head length and the like;
the system data flow is as follows: the satellite simulator central control software generates analog simulation telemetering data, the system realizes code pattern conversion on the telemetering analog data according to code pattern setting, and the telemetering analog data is modulated on a subcarrier in a BPSK modulation mode according to a certain code rate after code pattern conversion to form a telemetering data subcarrier modulation signal, and whether modulation is carried out or not is selected through a modulation switch; phase modulation is carried out on a subcarrier signal to a carrier, a 70MHz carrier signal is generated by a DDS numerical control oscillator, and the phase of the carrier is changed to be changed along with the amplitude of an input modulation signal according to the linear proportion of a preset modulation index, so that PM modulation is realized; the digital quadrature modulation module modulates the low-rate baseband digital signals to high-rate intermediate frequency signals after interpolation, and outputs the signals after D/A conversion;
(b) receive demodulation module design
The intermediate frequency receiving module is mainly used for receiving an intermediate frequency 70MHz uplink remote control signal output by a radio frequency front end, performing AD sampling, performing digital down-conversion in an orthogonal manner with a local carrier NCO, and sending a demodulated remote control subcarrier signal to the subcarrier demodulation module to complete remote control instruction receiving through carrier capturing, tracking and demodulation; the received and demodulated distance measuring signal is directly forwarded to the modulation module after passing through the controllable delay module, and meanwhile, a locking indication signal is output; the parameter control module receives the control instruction and transmits the corresponding configuration parameters to each unit of the demodulation module, thereby realizing the configuration of parameters such as remote control code rate, remote control subcarrier frequency, intermediate frequency receiving frequency, remote control signal code pattern, remote control instruction length, frame synchronization head and the like.
The invention relates to a realization method of a PXI bus-based satellite measurement and control simulator, wherein a chip selected by an AGC gain control circuit is AD8367, the chip is a variable gain single-ended IF amplifier provided by AD company, the chip uses an advanced X-AMP structure of the AD company, and the AGC gain control circuit has excellent gain control characteristics; the single AGC chip can realize automatic gain control in a 45dB dynamic range, and in order to ensure the input gain range, the gain range of the single chip can not meet the technical index requirement, so the system is realized by adopting a mode of cascading two chips and can meet the requirement of the system; the two AD8367 pieces work in a low-mode, wherein the second piece adopts an internal accurate square root filter, and output current is integrated by an external capacitor to generate gain control voltage; the gain control voltage end of the first chip is directly connected with the gain control end of the second chip, the second chip provides gain control voltage and works in a VGA state; through the cascade gain control circuit, the gain control can be effectively carried out on the input signal with the fluctuation range of 80dBm, and the output signal of the amplifier is ensured to be stabilized in a small range.
Compared with the prior art, the invention has the beneficial effects that:
1. the software radio concept is adopted, most of communication functions are realized by using software, the volume of the equipment is effectively reduced, and the reliability of the equipment is improved;
2. the board card adopts a miniaturized design, only one 3U board card is needed, and the measurement and control simulation function can be realized by occupying one slot position;
3. the external interface is simplified, only three interfaces of receiving, transmitting and 10MHz synchronous clock are reserved, and the use difficulty and the volume of the equipment are reduced;
4. the device has strong universality, has the receiving function of two intermediate frequency signals of 70MHz and 140MHz, and meets the simulation of measurement and control channels of various systems;
5. the auxiliary information of the lead code is utilized to realize rapid carrier frequency, phase capturing and tracking and bit synchronization, and the single-frame instruction code is received in a form of 'guide head + instruction content';
6. the dynamic range of the signal is wide, and the signal receiving and demodulation in the range of-80 db to 0db can be realized;
7. the design mode of the traditional complete machine is changed, a PXI bus interface is adopted to realize the interaction between an upper computer and a hardware bottom layer, the modularized design concept is realized, the test and control simulator function can be flexibly combined with frequency converters with different wave bands, and the satellite multi-system simulation function can also be flexibly combined with other satellite simulators;
8. the problem that the data analog source of the conventional measurement and control baseband equipment is relatively fixed is solved, and the function of downloading the telemetering analog data in real time is realized;
9. the control mode can meet the requirements of local control and network control.
Drawings
FIG. 1 is a block diagram of the system components of the present invention;
FIG. 2 is a general block diagram of the hardware of the present invention;
FIG. 3 is a functional block diagram of a modulation module;
FIG. 4 is a functional block diagram of a demodulation module;
FIG. 5 is a timing synchronization functional block diagram;
FIG. 6 is a schematic representation of a Gardner Ring error detection;
FIG. 7 is a Costas loop carrier synchronization;
fig. 8 is a remote control signal reception flowchart.
Detailed Description
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
As shown in fig. 1 to fig. 8, the method for implementing a PXI bus-based satellite measurement and control simulator of the present invention includes the following steps:
s1, designing a hardware platform: the measurement and control simulator board card takes a digital signal processing chip as a core and mainly comprises a high-speed A/D conversion circuit, an AGC gain control circuit, a large-scale FPGA device, a D/A conversion circuit, a clock management circuit, a power supply management circuit, an interface circuit and the like; the system comprises an uplink channel and a downlink channel, and realizes the minimum design of core functions; the board card realizes system communication by using a PXI bus chip, and finishes information interaction work with a PC (personal computer) through a PXI interface;
and S2, designing a digital signal processing module.
The invention relates to a realization method of a PXI bus-based satellite measurement and control simulator, wherein a large-scale FPGA device in step S1 is a main device for baseband signal processing, and not only carries digital up-down frequency conversion and data preprocessing tasks, but also needs to complete the receiving, caching and control command receiving and sending of high-speed data; for a receiving channel, the FPGA receives data after high-speed A/D conversion through a high-speed parallel interface, firstly carries out down-conversion on the data to a baseband, including NCO, filtering, extraction, frequency point selection and the like, and then carries out pretreatment on the baseband data according to needs, such as signal synchronization, correlation and the like; for a transmitting channel, the FPGA firstly preprocesses data acquired from central control software, then up-converts the data to intermediate frequency, and then sends the intermediate frequency to a front end D/A (digital/analog) to transmit the intermediate frequency to a radio frequency; the FPGA is also responsible for the control function of the PXI interface;
high-speed A/D conversion: the input signal of the intermediate frequency acquisition circuit is 70MHz, according to Nyquist sampling theorem, if the intermediate frequency is directly subjected to low-pass sampling, the sampling clock at least needs 140MHz to ensure that frequency spectrums are not overlapped, but the sampling rate is too high to cause great pressure on subsequent signal processing, and because the bandwidth of the intermediate frequency signal is 10MHz, the intermediate frequency band-pass sampling design is adopted; LTC2252 adopted by the analog-to-digital conversion part is a 12-bit 125Msps low-power-consumption A/D converter and is specially designed for carrying out digital processing on high-frequency and wide-dynamic-range signals; LTC2252 is well suited for demanding imaging and communications applications with AC performance SNR of 70.1dB, spurious free dynamic range (SFDR for signals at nyquist frequency) of 85 dB; the DC specification includes + -0.3 LSBINL (typical values), + -0.15 LSBDNL (typical values) and missing-free codes over the entire temperature range;
an AGC gain control circuit: the signal strength of the input end of the intermediate frequency receiving unit is small, and the dynamic range is wide, so that a gain control system needs to be added at the front end to ensure that the signal reaching the ADC is not saturated and has enough conversion bits, so that the demodulated input signal is stable;
PXI bus chip: the PXI interface control is realized by adopting a mode of controlling a PXI interface chip by using the FPGA; the FPGA is responsible for communicating with a local port between the interface chips, realizes a local bus control function, and is used for responding extension signals such as a trigger signal, a reference clock and the like in the PXI bus and performing other time sequence operation and control;
clock management: an external input clock synchronization interface circuit is designed by integrated board card, external 10MHz synchronization signal is introduced, the circuit detects the external clock input condition through FPGA, if there is external clock input, the system uses external clock mode, if there is no external clock input, the system generates 10MHz clock signal.
The invention discloses a method for realizing a PXI bus-based satellite measurement and control simulator, which comprises the following steps of S2:
(a) modulation transmission module design
The modulation module is mainly used for completing modulation and transmission of a telemetering signal, outputting a 70MHz intermediate frequency PM modulation signal, and has the functions of carrier frequency Doppler presetting, telemetering and ranging subcarrier adding and demodulating control, subcarrier modulation degree adjustment and the like; receiving a control instruction through a parameter control module, and transmitting corresponding configuration parameters to each unit of a software module to realize the configuration of parameters such as telemetry code rate, telemetry subcarrier frequency, telemetry modulation degree, intermediate frequency output frequency, telemetry signal code type, telemetry frame length, frame synchronization head, synchronization head length and the like;
the system data flow is as follows: the satellite simulator central control software generates analog simulation telemetering data, the system realizes code pattern conversion on the telemetering analog data according to code pattern setting, and the telemetering analog data is modulated on a subcarrier in a BPSK modulation mode according to a certain code rate after code pattern conversion to form a telemetering data subcarrier modulation signal, and whether modulation is carried out or not is selected through a modulation switch; phase modulation is carried out on a subcarrier signal to a carrier, a 70MHz carrier signal is generated by a DDS numerical control oscillator, and the phase of the carrier is changed to be changed along with the amplitude of an input modulation signal according to the linear proportion of a preset modulation index, so that PM modulation is realized; the digital quadrature modulation module modulates the low-rate baseband digital signals to high-rate intermediate frequency signals after interpolation, and outputs the signals after D/A conversion; the modulation module is shown in the schematic block diagram of fig. 3:
(1) telemetry double-buffering design
The system designs ping-pong storage, receives telemetering simulation data sent by the system in real time, alternately places the data in the memory-ping and the memory-pong, and can simultaneously read and process the data in the other memory in the process of storing the data in one memory, thereby improving the data transmission efficiency;
(2) baseband coding design
In practical baseband transmission systems, not all baseband waveforms are suitable for transmission in a channel; for example, a unipolar baseband waveform containing dc and low frequency components is not suitable for transmission in a channel with poor low frequency transmission, since it may cause severe signal distortion; for another example, when the information symbol sequence includes a long string of consecutive "1" or "0" symbols, the nrzi waveform exhibits a continuous fixed level, and thus timing information cannot be acquired; the same problem exists when a unipolar return-to-zero code is transmitted as a "0"; three code pattern transformations of NRZ-L, NRZ-M and NRZ-S are supported in the system;
NRZ-L non-return-to-zero level codes, which represent 0 and 1 by two levels, respectively, "-1" represents "0" and "1" represents "1";
NR Z-M mark differential code, the level change represents "1", the level change represents "0";
NRZ-S space number differential code, a level change indicates "0", and a level non-change indicates "1";
(3) PSK mapping
The constellation diagram reflects the distribution of the phase and amplitude of the in-phase branch component I (t) and the quadrature branch component Q (t) of the quadrature-modulated baseband signal on a two-dimensional plane.
After the baseband signal is encoded, BPSK modulation is first applied to the subcarriers. BPSK (binary absolute phase shift keying) uses the unmodulated phase as the reference phase, i.e., the absolute value of the carrier phase is used to convey digital information. The numerical expression is as follows:
S(t)＝D(t)cos(ω0t) wherein
And adjusting the phase of the carrier sinusoidal signal according to the input logic value. If the data is 0, the phase is 0, and if the data is 1, the phase is 180 degrees;
(4) shaped filtering
The commonly used channel is a band-limited channel, and when a rectangular pulse signal passes through the band-limited channel, an obvious trailing image can be generated, so that intersymbol interference is formed, the receiving of adjacent code elements is directly influenced, and the error rate of a receiving end is increased to a certain extent. In the system, the baseband signal is subjected to pulse forming, so that the frequency spectrum of the baseband signal is more concentrated, the channel bandwidth required by the formed and filtered baseband signal is narrower, and the problem of intersymbol interference is effectively avoided. A raised cosine filter is used, which corresponds to an impulse response as follows:
where α determines the steepness of the filter frequency response and B is the filter bandwidth. The filter has small tailing and fast attenuation, and can effectively reduce intersymbol interference;
(5) CIC interpolation filtering
CIC interpolation is a process of increasing sampling rate, the shape of the frequency spectrum of a signal after interpolation is not changed, the signal is subjected to image expansion, and redundant image frequency is filtered by a low-pass filter; the coefficients of the CIC filter are all 1, the structure is simple, the CIC filter is suitable for working under high sampling frequency and is commonly used for programmable filtering, and the CIC filter is used for 4 times of the later stage of the fixed interpolation filter in the text and realizes the interpolation function of 1 time to 64 times;
(6) quadrature up-conversion
The time domain expression is:
s(t)＝I(t)·cosωct+Q(t)·sinωct
wherein ω c is the carrier angular frequency, and the information of the modulated signal is contained in I (t), Q (t);
(7) modulation of main carrier
PM modulation is in principle a corresponding change of the carrier phase according to the amplitude variation of the modulation signal. The phase modulation signal formula is as follows:
SPM(t)＝Acos[2πFt+2πkpm(t)+θ0]
where m (t) is BPSK modulation signal, kpIs a modulation index, θ0For the initial phase, F is the carrier frequency. The phase modulation index represents the ratio between the carrier power and the information power, and when the information power is constant, the phase modulation index kpThe larger the information power is, the stronger the information power is, and the weaker the carrier power is; phase modulationIndex kpThe smaller the information power, the weaker the carrier power.
(b) Receive demodulation module design
The intermediate frequency receiving module is mainly used for receiving an intermediate frequency 70MHz uplink remote control signal output by a radio frequency front end, performing AD sampling, performing digital down-conversion in an orthogonal manner with a local carrier NCO, and sending a demodulated remote control subcarrier signal to the subcarrier demodulation module to complete remote control instruction receiving through carrier capturing, tracking and demodulation; the received and demodulated distance measuring signal is directly forwarded to the modulation module after passing through the controllable delay module, and meanwhile, a locking indication signal is output; receiving a control instruction through a parameter control module, and transmitting corresponding configuration parameters to each unit of a demodulation module to realize the configuration of parameters such as remote control code rate, remote control subcarrier frequency, intermediate frequency receiving frequency, remote control signal code pattern, remote control instruction length, frame synchronization head and the like; the schematic block diagram of the demodulation module is shown in fig. 4:
1) main carrier quadrature down-conversion design
After the measurement and control signal is received, performing band-pass sampling on a 70MHz input signal through A/D, wherein the sampling rate is selected to meet the Nyquist band-pass sampling theorem; forming a digital sequence x (n) after digitalization and then connecting the digital sequence x (n) with two orthogonal local oscillator sequences cos (omega)0n) and sin (ω)0n) multiplying and obtaining a baseband IQ signal by a low-pass filtering method;
2) demodulation of main carrier
After the signal is subjected to digital quadrature down-conversion, frequency multiplication components are removed through a low-pass filter on the premise of ensuring that subcarriers pass through; but the frequency and phase deviation exists between the received carrier and the local carrier, I, Q two paths of signals are multiplied to be offset, a phase-locked loop error equation is obtained through a loop filter, a digital frequency synthesizer (DDS) is driven according to the error equation, the phase-locked loop works, and finally the output frequency of the DDS is consistent with the input frequency of the signals; then, the phase angle of the obtained complex signal is calculated to complete the demodulation of PM;
3) CIC decimation design
After orthogonal down-conversion, because the sampling rate of the signal is too high, firstly, carrying out down-sampling with the symbol rate of N times, so that the number of sampling points in one symbol period is N, providing data for timing recovery, and the value of N is determined by a timing synchronization algorithm; extracting by using a CIC (common information center) extraction filter;
as can be seen from the CIC filter principle, the system function of an N-stage CIC filter can be expressed by the following equation:
if the change multiple of the decimation rate is not an integer, the method can be realized by cascading an interpolator and a decimator;
4) matched filter design
In digital signal receiving, the matched filter can effectively inhibit out-of-band noise of a signal, so that the noise component output by the filter is as small as possible, and the influence of the noise on signal judgment is reduced; the criterion is to maximize the output signal-to-noise ratio of the filter at a specific time; in the system, a receiving filter adopts a square root raised cosine roll-off filter which is conjugate matched with a transmitting filter; experiments prove that the system adopting the matched filter has lower error rate of output signals than the system adopting the non-matched filter, and the transmission quality of the signals is high;
5) timing synchronization
The system uses a Gardner timing synchronization ring to realize the bit synchronization function, has relatively simple structure, does not need to know the carrier phase in advance, and is a relatively common loop structure for timing synchronization; the structural block diagram is shown in FIG. 5;
timing error detection in the Gardner timing synchronization loop structure is achieved by calculating the values of adjacent symbol best sampling decision points and transition points, as shown in fig. 6;
for BPSK modulated signals, the error calculation equation is as follows:
it can be seen from the expression and the figure that when the timing synchronization loop finishes the decision of the optimal sampling moment, the phase is the sameIf the adjacent symbols are the same, y (r) -y (r-1) is zero; if the adjacent symbols are different:
is zero; that is, as long as the timing loop is locked, the timing error of the loop is always 0 value; when the loop does not complete synchronization, if adjacent code elements are different, and the sampling time is assumed to be behind the optimal sampling time, error is greater than 0, otherwise, error is less than 0; when the adjacent code elements are the same, the loop timing error is always 0; the Gardner timing synchronization loop can start loop synchronization only when adjacent symbol symbols generate hopping;
6) carrier synchronization
The system selects the Costas ring as the carrier recovery ring to process the received signal, so that the hardware occupies less resources and is easy to realize. The input signal is divided into two branches, the upper branch and the DDS output orthogonal phase discrimination, and the lower branch and the DDS output in-phase discrimination with 90-degree phase shift. The output of the upper phase discriminator and the output of the lower phase discriminator are multiplied after low-pass filtering to obtain an error signal, the error signal controls the phase and the frequency of the DDS after passing through a loop filter, and the DDS outputs sine and cosine signals with the same frequency and phase as the input carrier signal under the action of the error signal. The Costas loop carrier synchronization schematic diagram is shown in fig. 7;
7) constellation diagram mapping
When BPSK modulation is performed, the mapping relationship is: "0" - - - "-1", "1" - - - "1"; therefore, when the mapping is received, the decision is directly made, the symbol larger than 0 is '1', and the symbol smaller than 0 is '0';
8) baseband decoding
NRZ-L non-return-to-zero level code; the more than zero level is judged to be '1', and the less than zero level is judged to be '0';
NRZ-M mark differential code; if the high and low levels change, the judgment is '1', and if no jump occurs, the judgment is '0';
NRZ-S space number differential code; if the high and low levels change, the judgment is '0', and if no jump occurs, the judgment is '1';
9) remote control instruction single-frame receiving design
As shown in fig. 8, the remote control command is typically command information with a length of 16 bytes, and frame synchronization cannot be normally achieved without a fixed frame header and frame tail; in the simulation test process, a form of 'a guide head + instruction content' is designed to realize the receiving of remote control instructions, and the guide head is a field with a fixed length, such as '0 xEB 90'; the upper computer software sends the received remote control instruction (the actual instruction content after the guide head is removed) to the satellite simulator central control software, and responds to the remote control instruction, stores the disk and the like;
because the receiving characteristics of remote control and remote control are different, the remote control receiving is a continuous frame receiving process and has sufficient time for tracking and capturing, and the ground test equipment generally does not have the function of receiving remote control. In order to meet project requirements, on one hand, the device fully utilizes auxiliary information of the lead code to realize rapid carrier frequency, phase capturing and tracking and bit synchronization; on the other hand, a flexibly-configurable frame synchronization strategy is adopted, and the single-frame detection, namely the synchronization function, can be completed.
The invention relates to a realization method of a PXI bus-based satellite measurement and control simulator, wherein a chip selected by an AGC gain control circuit is AD8367, the chip is a variable gain single-ended IF amplifier provided by AD company, the chip uses an advanced X-AMP structure of the AD company, and the AGC gain control circuit has excellent gain control characteristics; the single AGC chip can realize automatic gain control in a 45dB dynamic range, and in order to ensure the input gain range, the gain range of the single chip can not meet the technical index requirement, so the system is realized by adopting a mode of cascading two chips and can meet the requirement of the system; the two AD8367 pieces work in a low-mode, wherein the second piece adopts an internal accurate square root filter, and output current is integrated by an external capacitor to generate gain control voltage; the gain control voltage end of the first chip is directly connected with the gain control end of the second chip, the second chip provides gain control voltage and works in a VGA state; through the cascade gain control circuit, the gain control can be effectively carried out on the input signal with the fluctuation range of 80dBm, and the output signal of the amplifier is ensured to be stabilized in a small range.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (4)
1. A realization method of a PXI bus-based satellite measurement and control simulator is characterized by comprising the following steps:
s1, designing a hardware platform: the measurement and control simulator board card takes a digital signal processing chip as a core and mainly comprises a high-speed A/D conversion circuit, an AGC gain control circuit, a large-scale FPGA device, a D/A conversion circuit, a clock management circuit, a power supply management circuit, an interface circuit and the like; the system comprises an uplink channel and a downlink channel, and realizes the minimum design of core functions; the board card realizes system communication by using a PXI bus chip, and finishes information interaction work with a PC (personal computer) through a PXI interface;
and S2, designing a digital signal processing module.
2. The method as claimed in claim 1, wherein the large-scale FPGA device in step S1 is a main device for baseband signal processing, and not only carries digital up-down conversion and data preprocessing tasks, but also needs to complete high-speed data reception, caching and control command transceiving; for a receiving channel, the FPGA receives data after high-speed A/D conversion through a high-speed parallel interface, firstly carries out down-conversion on the data to a baseband, including NCO, filtering, extraction, frequency point selection and the like, and then carries out pretreatment on the baseband data according to needs, such as signal synchronization, correlation and the like; for a transmitting channel, the FPGA firstly preprocesses data acquired from central control software, then up-converts the data to intermediate frequency, and then sends the intermediate frequency to a front end D/A (digital/analog) to transmit the intermediate frequency to a radio frequency; the FPGA is also responsible for the control function of the PXI interface;
high-speed A/D conversion: the input signal of the intermediate frequency acquisition circuit is 70MHz, according to Nyquist sampling theorem, if the intermediate frequency is directly subjected to low-pass sampling, the sampling clock at least needs 140MHz to ensure that frequency spectrums are not overlapped, but the sampling rate is too high to cause great pressure on subsequent signal processing, and because the bandwidth of the intermediate frequency signal is 10MHz, the intermediate frequency band-pass sampling design is adopted; LTC2252 adopted by the analog-to-digital conversion part is a 12-bit 125Msps low-power-consumption A/D converter and is specially designed for carrying out digital processing on high-frequency and wide-dynamic-range signals; LTC2252 is well suited for demanding imaging and communications applications with AC performance SNR of 70.1dB, spurious free dynamic range (SFDR for signals at nyquist frequency) of 85 dB; the DC specification includes + -0.3 LSBINL (typical values), + -0.15 LSBDNL (typical values) and missing-free codes over the entire temperature range;
an AGC gain control circuit: the signal strength of the input end of the intermediate frequency receiving unit is small, and the dynamic range is wide, so that a gain control system needs to be added at the front end to ensure that the signal reaching the ADC is not saturated and has enough conversion bits, so that the demodulated input signal is stable;
PXI bus chip: the PXI interface control is realized by adopting a mode of controlling a PXI interface chip by using the FPGA; the FPGA is responsible for communicating with a local port between the interface chips, realizes a local bus control function, and is used for responding extension signals such as a trigger signal, a reference clock and the like in the PXI bus and performing other time sequence operation and control;
clock management: an external input clock synchronization interface circuit is designed by integrated board card, external 10MHz synchronization signal is introduced, the circuit detects the external clock input condition through FPGA, if there is external clock input, the system uses external clock mode, if there is no external clock input, the system generates 10MHz clock signal.
3. The method as claimed in claim 2, wherein the step S2 includes the following steps:
(a) modulation transmission module design
The modulation module is mainly used for completing modulation and transmission of a telemetering signal, outputting a 70MHz intermediate frequency PM modulation signal, and has the functions of carrier frequency Doppler presetting, telemetering and ranging subcarrier adding and demodulating control, subcarrier modulation degree adjustment and the like; receiving a control instruction through a parameter control module, and transmitting corresponding configuration parameters to each unit of a software module to realize the configuration of parameters such as telemetry code rate, telemetry subcarrier frequency, telemetry modulation degree, intermediate frequency output frequency, telemetry signal code type, telemetry frame length, frame synchronization head, synchronization head length and the like;
the system data flow is as follows: the satellite simulator central control software generates analog simulation telemetering data, the system realizes code pattern conversion on the telemetering analog data according to code pattern setting, and the telemetering analog data is modulated on a subcarrier in a BPSK modulation mode according to a certain code rate after code pattern conversion to form a telemetering data subcarrier modulation signal, and whether modulation is carried out or not is selected through a modulation switch; phase modulation is carried out on a subcarrier signal to a carrier, a 70MHz carrier signal is generated by a DDS numerical control oscillator, and the phase of the carrier is changed to be changed along with the amplitude of an input modulation signal according to the linear proportion of a preset modulation index, so that PM modulation is realized; the digital quadrature modulation module modulates the low-rate baseband digital signals to high-rate intermediate frequency signals after interpolation, and outputs the signals after D/A conversion;
(b) receive demodulation module design
The intermediate frequency receiving module is mainly used for receiving an intermediate frequency 70MHz uplink remote control signal output by a radio frequency front end, performing AD sampling, performing digital down-conversion in an orthogonal manner with a local carrier NCO, and sending a demodulated remote control subcarrier signal to the subcarrier demodulation module to complete remote control instruction receiving through carrier capturing, tracking and demodulation; the received and demodulated distance measuring signal is directly forwarded to the modulation module after passing through the controllable delay module, and meanwhile, a locking indication signal is output; the parameter control module receives the control instruction and transmits the corresponding configuration parameters to each unit of the demodulation module, thereby realizing the configuration of parameters such as remote control code rate, remote control subcarrier frequency, intermediate frequency receiving frequency, remote control signal code pattern, remote control instruction length, frame synchronization head and the like.
4. The method as claimed in claim 2, wherein the chip selected by the AGC gain control circuit is AD8367, the chip is a variable gain single-ended IF amplifier from AD company, and the chip uses an advanced X-AMP structure from AD company and has an excellent gain control characteristic; the single AGC chip can realize automatic gain control in a 45dB dynamic range, and in order to ensure the input gain range, the gain range of the single chip can not meet the technical index requirement, so the system is realized by adopting a mode of cascading two chips and can meet the requirement of the system; the two AD8367 pieces work in a low-mode, wherein the second piece adopts an internal accurate square root filter, and output current is integrated by an external capacitor to generate gain control voltage; the gain control voltage end of the first chip is directly connected with the gain control end of the second chip, the second chip provides gain control voltage and works in a VGA state; through the cascade gain control circuit, the gain control can be effectively carried out on the input signal with the fluctuation range of 80dBm, and the output signal of the amplifier is ensured to be stabilized in a small range.
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