CN103996661B - Method for generating SRAM layout - Google Patents

Abstract

The invention proposes a method for generating an SRAM layout, first forming the first unit, then duplicating the first unit to form the second unit, connecting the first unit and the second unit to form an SRAM, and classifying the same parameters in the SRAM, which can realize The automatic generation of SRAM layout can efficiently complete the realization of SRAM layout of different sizes, simplify the design of SRAM layout, thereby reducing the error rate generated in the process of manual layout design, and shorten the time for SRAM layout realization.

Description

SRAM layout generation method

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a method for generating an SRAM layout.

Background technique

SRAM (Static Random Access Memory, Static Random Access Memory) is a semiconductor memory that retains data as long as it is powered. SRAM has the advantages of low power consumption, fast data access speed and compatibility with CMOS logic technology, and is widely used in various electronic devices. Therefore, SRAM is an indispensable part of any semiconductor logic process.

A basic SRAM cell consists of two cross-coupled inverters and two access transistors (usually NMOS transistors), which is a typical six-transistor SRAM (6T SRAM). Specifically, the SRAM can be divided into a first inverter (Inverter), a second inverter and two NMOS transistors (abbreviated as NPASS), wherein the first inverter is composed of a first PMOS transistor and a first NMOS transistor, The second inverter is composed of a second PMOS transistor and a second NMOS transistor, plus two NMOS transistors are composed of six transistors (Transistor) in total.

The traditional SRAM layout generation method is to generate each transistor separately through software, and then combine them into SRAM. Although the generation method of the traditional SRAM layout can meet the design requirements of the current SRAM layout, since there are 6 transistors in the SRAM, and each transistor has multiple dimensions that need to be defined, such as gate size, active area size, and injection layer The size of the well layer and the well layer need to be defined. Therefore, the traditional SRAM layout generation method is not efficient, especially when the size of the SRAM needs to be modified, there are many sizes that need to be changed, so human operations often affect the generation of the SRAM layout. Unnecessary errors are made and a lot of time and effort is wasted.

Contents of the invention

The purpose of the present invention is to provide a method for generating SRAM layout, which can classify the same parameters, realize automatic generation of SRAM layout, and improve efficiency.

In order to achieve the above object, the present invention proposes a method for generating an SRAM layout, comprising steps:

defining the shape and size of the gate of the first inverter;

The shape and size of the active region of the first PMOS transistor and the first NMOS transistor in the first inverter are defined by the shape and size of the gate of the first inverter;

defining the shape and size of the NMOS gate at the first input terminal;

The shape and size of the first input NMOS active region are defined by the shape and size of the first input NMOS gate;

The shape and size of the first injection layer and the first well layer are defined by the shape and size of the first input NMOS active region;

Connecting the drains of the first PMOS transistor and the first NMOS transistor together, connecting the first input terminal NMOS and the active region of the first NMOS transistor together, and connecting the first input terminal NMOS and the first NMOS transistor together The drains of the first NMOS transistors are also connected together, thereby constituting the first unit;

Duplicate the first unit and rotate it by 180 degrees to form the second unit;

The drain of the first PMOS transistor in the first unit is connected to the gate of the second inverter in the second unit, and the drain of the second PMOS transistor in the second unit is connected to the gate of the second inverter in the first unit. An inverter gate is connected to generate the SRAM layout.

Further, the drains of the first PMOS transistor and the first NMOS transistor are connected together through a via connection and a metal connection.

Further, the first input terminal NMOS and the drain of the first NMOS transistor are connected together through a via hole.

Further, the drain of the first PMOS transistor in the first unit is connected to the gate of the second inverter in the second unit through a via.

Further, the drain of the second PMOS transistor in the second unit is connected to the gate of the first inverter in the first unit through a via hole.

Further, the through-hole connections are all led out through metal connections.

Compared with the prior art, the beneficial effects of the present invention are mainly reflected in: first forming the first unit, then duplicating the first unit to form the second unit, connecting the first unit and the second unit to form an SRAM, and returning the same parameters in the SRAM to class, which can realize the automatic generation of SRAM layout, so that the realization of SRAM layout of different sizes can be efficiently completed, the design of SRAM layout can be simplified, thereby reducing the error rate generated in the process of manual layout design, and shortening the implementation time of SRAM layout.

Description of drawings

Fig. 1 is the flowchart of the generation method of SRAM layout in an embodiment of the present invention;

Fig. 2 is a schematic structural diagram of the first unit in an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of an SRAM layout in an embodiment of the present invention.

detailed description

The method for generating the SRAM layout of the present invention will be described in more detail below in conjunction with the schematic diagram, wherein a preferred embodiment of the present invention is shown, and it should be understood that those skilled in the art can modify the present invention described here, while still realizing the advantages of the present invention Effect. Therefore, the following description should be understood as the broad knowledge of those skilled in the art, but not as a limitation of the present invention.

In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions and constructions are not described in detail since they would obscure the invention with unnecessary detail. It should be appreciated that in the development of any actual embodiment, numerous implementation details must be worked out to achieve the developer's specific goals, such as changing from one embodiment to another in accordance with system-related or business-related constraints. Additionally, it should be recognized that such a development effort might be complex and time consuming, but would nevertheless be merely a routine undertaking for those skilled in the art.

In the following paragraphs the invention is described more specifically by way of example with reference to the accompanying drawings. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

The core idea of the present invention is that since the 6T SRAM has a first inverter, a first input terminal NMOS, a second inverter and a second input terminal NMOS, and in the first inverter, the first NMOS transistor, the first The parameters of the PMOS transistor and the second NMOS transistor and the second PMOS transistor in the second inverter are exactly the same, and the parameters of the first input terminal NMOS and the second input terminal NMOS are also completely the same, so it is possible to have a large number of identical The parameters are classified to form the first unit, then the first unit is copied and rotated to obtain the second unit, and the first unit and the second unit are connected to obtain the 6T SRAM layout.

Specifically, please refer to FIG. 1, FIG. 2 and FIG. 3. FIG. 1 is a flowchart of a method for generating an SRAM layout in an embodiment of the present invention. FIG. 2 is a schematic structural diagram of the first unit in an embodiment of the present invention. FIG. 3 It is a schematic structural diagram of the SRAM layout in an embodiment of the present invention; in this embodiment, the method for generating the proposed SRAM layout includes steps:

S100: Define the shape and size of the first inverter gate 61;

In step S100 , the shape and size of the first inverter gate 61 can be determined according to specific process requirements, and different sizes of the gate 61 can obtain SRAM layouts of different sizes.

S200: Define the shape and size of the active regions of the first PMOS transistor 12 and the first NMOS transistor 11 in the first inverter 10 according to the shape and size of the first inverter gate 61;

S300: Define the shape and size of the NMOS gate 62 at the first input terminal;

Similarly, in step S300 , the shape and size of the NMOS gate 62 at the first input terminal can be determined according to specific process requirements, and different sizes of the NMOS gate 62 at the first input terminal can obtain SRAM layouts of different sizes.

S400: Define the shape and size of the active region of the first input NMOS 30 according to the shape and size of the first input NMOS gate 62;

S500: Define the shape and size of the first injection layer 13 and the first well layer 14 according to the shape and size of the active region of the first input NMOS 30;

S600: Connect the drains of the first PMOS transistor 12 and the first NMOS transistor 11 together, connect the first input terminal NMOS30 and the active region of the first NMOS transistor 11 together, and connect the first NMOS transistor 11 An input terminal NMOS30 and the drain of the first NMOS transistor 11 are also connected together to form a first unit, as shown in FIG. 2 ;

S700: Duplicating the first unit and rotating it by 180 degrees to form a second unit;

Wherein, the second unit includes a second inverter 20, a second input terminal NMOS40, a second injection layer and a second well layer, and the second inverter 20 includes a second inverter gate 63 , the first PMOS transistor 22 and the first NMOS transistor 21, the second input terminal NMOS40 includes a second input terminal NMOS gate 64, as shown in FIG. The first injection layer 13 , the first well layer 14 , the second injection layer, the second well layer and some metal wirings.

S800: Connect the drain of the first PMOS transistor 12 in the first unit to the gate 63 of the second inverter in the second unit, and connect the drain of the second PMOS transistor 22 in the second unit to the second inverter gate 63 in the second unit. The gates 61 of the first inverters in a cell are connected to create an SRAM layout.

In this embodiment, the drains of the first PMOS transistor 12 and the first NMOS transistor 11 are connected together through a via connection 50 and a metal connection 70; the first input terminal NMOS30 and the first NMOS transistor 11 The drains of the drains are connected together through the through-hole connection 50; the drain of the first PMOS transistor 12 in the first unit is connected with the second inverter gate 63 in the second unit through the through-hole connection 50; The second PMOS transistor drain 22 in the second unit is connected to the first inverter gate 61 in the first unit through a through-hole connection 50; in actual production, the through-hole connection 50 is connected through a metal connection. Line 70 leads out to facilitate external circuit connection.

Using the SRAM layout generation method proposed in this embodiment and using SMARTCELL software for implementation, there is no need to modify and define the size of each transistor, and only need to modify fewer independent variables, such as the shape and size of the first inverter gate 1. The shape and size of the NMOS gate at the first input terminal can realize the modification of all the shapes and sizes of the six transistors. Therefore, SRAMs of different sizes can be obtained more quickly, reducing the probability of errors that may occur when manually modifying many parameters.

To sum up, in the SRAM layout generation method provided by the embodiment of the present invention, the first unit is first formed, then the first unit is copied to form the second unit, the first unit and the second unit are connected to form the SRAM, and the same parameters in the SRAM are Classification can realize the automatic generation of SRAM layout, so that the realization of SRAM layout of different sizes can be completed efficiently, the design of SRAM layout can be simplified, thereby reducing the error rate generated in the process of manual layout design, and shortening the realization time of SRAM layout.

The foregoing are only preferred embodiments of the present invention, and do not limit the present invention in any way. Any person skilled in the technical field, within the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the technical solution of the present invention. The content still belongs to the protection scope of the present invention.

Claims (6)

1. a kind of generation method of SRAM domain, including step：

Define the shape and size of the first inverter gate；

Define the first PMOS transistor and first in the first phase inverter by the shape and size of described first inverter gate The shape and size of nmos pass transistor active area；

Define the shape and size of first input end NMOS gate；

Define the shape of described first input end NMOS active area with the shape and size of described first input end NMOS gate And size；

With the shape and size of described first input end NMOS active area define the first implanted layer and the first well layer shape and Size；

So that the drain electrode of described first PMOS transistor and the drain electrode of the first nmos pass transistor is linked together, make described first input The active area of the active area of end NMOS and the first nmos pass transistor links together, and makes the leakage of described first input end NMOS The drain electrode of pole and the first nmos pass transistor also links together, thus constituting first module；

Replicate described first module, rotate 180 degree, form second unit；

So that the first PMOS transistor drain electrode in described first module is connected with the second inverter gate in second unit, make institute The the second PMOS transistor drain electrode stated in second unit is connected with the first inverter gate in first module, thus generating SRAM Domain.

2. the generation method of SRAM domain as claimed in claim 1 is it is characterised in that the drain electrode of described first PMOS transistor Drain electrode with the first nmos pass transistor is linked together by through hole line and metal connecting line.

3. the generation method of SRAM domain as claimed in claim 2 is it is characterised in that the drain electrode of described first input end NMOS Drain electrode with the first nmos pass transistor is linked together by through hole line.

4. the generation method of SRAM domain as claimed in claim 3 is it is characterised in that a PMOS in described first module Transistor drain is connected by through hole line with the second inverter gate in second unit.

5. the generation method of SRAM domain as claimed in claim 4 is it is characterised in that the 2nd PMOS in described second unit Transistor drain is connected by through hole line with the first inverter gate in first module.

6. the generation method of SRAM domain as claimed in claim 5 is it is characterised in that described through hole line is all connected by metal Line is drawn.