CN103996602B - A kind of method using bilateral wall technique to form ultralow size figure - Google Patents
A kind of method using bilateral wall technique to form ultralow size figure Download PDFInfo
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- CN103996602B CN103996602B CN201410253213.5A CN201410253213A CN103996602B CN 103996602 B CN103996602 B CN 103996602B CN 201410253213 A CN201410253213 A CN 201410253213A CN 103996602 B CN103996602 B CN 103996602B
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- 238000000034 method Methods 0.000 title claims abstract description 67
- 230000002146 bilateral effect Effects 0.000 title claims abstract description 16
- 239000010409 thin film Substances 0.000 claims abstract description 47
- 239000000463 material Substances 0.000 claims abstract description 42
- 238000001259 photo etching Methods 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 73
- 239000000377 silicon dioxide Substances 0.000 claims description 36
- 235000012239 silicon dioxide Nutrition 0.000 claims description 35
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 6
- 238000004380 ashing Methods 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 2
- 230000003287 optical effect Effects 0.000 claims description 2
- 239000010408 film Substances 0.000 claims 1
- 230000008021 deposition Effects 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- SRPAPUGGPQTIBE-UHFFFAOYSA-N [O-2].[O-2].[Ti+4].[Si+2]=O Chemical compound [O-2].[O-2].[Ti+4].[Si+2]=O SRPAPUGGPQTIBE-UHFFFAOYSA-N 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000000101 transmission high energy electron diffraction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
Abstract
A kind of method using bilateral wall technique to form ultralow size figure, including: form the figure with fisrt feature size；Then depositing thin film material layer on this figure, form the conforma layer of uniform fold mask graph, on side wall, the thickness of thin film is the first thickness；Carry out second time photoetching and develop, defining the first device area；Carrying out second time on this figure to deposit, deposit thin film material layer, deposit thickness is the second thickness, and now the first device area covers the thickness of material is the sum that the first thickness adds the second thickness, and the thickness of the second device area is the second thickness；Anisotropically etch thin-film material, the thin-film material of mask layer top and bottom is removed, leaves behind the thin-film material on sidewall；Cineration technics optionally removes hard mask, leaves behind the side wall that thin-film material is formed；Utilize thin-film material to perform etching as the new mask of etching, form the hyperfine figure of two kinds of sizes with the first thickness by deposition thin film and the decision of the second thickness.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of self aligned formation hyperfine feature chi
The method of very little figure.Bilateral wall technique is used to form ultralow dimensional drawing it is more particularly related to a kind of
The method of shape.
Background technology
The characteristic size of super large-scale integration according to the development of Moore's Law, have evolved to 20 nanometers and
Following characteristic size, in order to increase the capacity of semiconductor device on less area and reduce cost, is formed
There is better performance, the semiconductor device of lower power consumption.The contraction of the characteristic size of each device needs
More complicated technology.Photoetching process is the conventional method transferring on substrate by device and circuit pattern, line
Width and spacing are two parameters the most key in photoetching process.Spacing is defined as the phase of two adjacent lines
With the distance between putting.Due to various factors, such as the physical restriction such as wavelength of optics and light, existing photoetching
Technology has minimum spacing can not meet the demand of integrated circuit below 20 nanometers, less than this specific photoetching
The figure of the characteristic size of technological limit can not be formed by existing photoetching technique.Therefore, one is found
The method that can meet again characteristic size demand while of utilizing existing photoetching technique is the most extremely important.
Self aligned secondary graphical method is to be widely studied in recent years and the figure of very likely large-scale production
Transfer techniques, with it, disclosure satisfy that the figure transfer demand of below 20 nanometers, not by photoetching work
The physics of skill and the restriction of the equipment limit.
But the width of the spacer that self aligned secondary graphical method obtains (thickness of conforma layer) is unique
, the size of the figure so obtained also is unique, but in actual Application of integrated circuit, especially
It is in logic circuit, SRAM circuit, it is desirable to have the active area of different characteristic size, different characteristic size
Grid etc..
Summary of the invention
The technical problem to be solved is for there is drawbacks described above in prior art, it is provided that Yi Zhongneng
Enough use the method that bilateral wall technique forms ultralow size figure.
In order to realize above-mentioned technical purpose, according to the present invention, it is provided that a kind of employing bilateral wall technique is formed super
First the method for low dimensional figure, comprising: carry out photoetching for the first time etch mask layer by a layer mask version
Form the figure with fisrt feature size；Then on this figure, deposit thin film material layer, formed uniformly
The conforma layer of coverage mask figure, on side wall, the thickness of thin film is the first thickness；Carry out second time photoetching and show
Shadow, is defined as the first device area with a part of thin-film material covered by photoresist, will be as the second device
The thin-film material of the expose portion in region is removed；Removing photoresist, the most only first device area is by thin film
Material covers；Then carrying out second time on this figure to deposit, deposit thin film material layer, deposit thickness is
Second thickness, now the first device area covers the thickness of material is the sum that the first thickness adds the second thickness, the
Two device areas thickness be the second thickness；Anisotropically etch thin-film material, by mask layer top and
The thin-film material of bottom is removed, and leaves behind the thin-film material on sidewall；Cineration technics is optionally removed and is firmly covered
Mould, leaves behind the side wall that thin-film material is formed；Thin-film material is utilized to perform etching as the new mask of etching,
Forming the hyperfine figure with two kinds of sizes, two kinds of sizes are by the first thickness and the second thickness depositing thin film
Determine.
In one embodiment, first photoetching for the first time etch mask layer (amorphous are carried out by a layer mask version
Carbon sacrifice layer) form the figure with fisrt feature size (this is closely sized to the physics limit of photoetching)；Connect
Deposition thin film material layer on this figure, form the side wall of uniform fold mask graph, thin film on side wall
Thickness be the first thickness；Carrying out second time photoetching developing, photoresist covers a part of material and is defined as the
One device area, removes the thin-film material of the part (the second device area) exposed；Remove photoresist,
The first device area is now only had to have material one covering；Then on this figure, carry out second time deposit, deposition
Thin film material layer 1, deposit thickness is the second thickness, and now the first device area covers the thickness of material is the
One thickness adds the sum of the second thickness, the second device area thickness be the second thickness；Anisotropic etching
Thin-film material 1, removes the thin-film material of mask layer top and bottom, leaves behind the thin film on sidewall；Ashing
The removal hard mask (sacrifice layer) of process selectivity, leaves behind the side wall that material 1 is formed；Material is as etching
New mask perform etching, formed and there is the hyperfine figure of two kinds of sizes.And the size of size close to
First thickness of side wall and the second thickness, the second thickness is the second size of the second requirement on devices, the first thickness
With the second thickness and the first size that is the first requirement on devices.
In one embodiment, the method for the shallow trench forming patterning in a silicon substrate includes: at silicon substrate
Upper formation silicon nitride, and form mask layer (sacrifice layer) on silicon nitride, and use photoetching process formation to have
The mask graph of fisrt feature size；The method further includes at covering layer of silicon dioxide on above-mentioned figure
Conforma layer, forms the side wall of uniform fold mask graph, and on side wall, the thickness of thin film is the first thickness；Immediately
Row second time photoetching is also developed, and photoresist covers a part of silicon dioxide conforma layer, by being total to of the part of exposure
Shape layer is removed clean, and definition overlay area is the first device area, and expose portion is the second device area；Go
Except photoresist and carry out second time and deposit silicon dioxide conforma layer, form the side wall of uniform fold mask graph,
Deposit thickness is the second thickness, and now to be that the first thickness adds the second thick for the thickness of the first device area silicon dioxide
Degree sum, the second device area thickness be the second thickness；Anisotropic etching silicon dioxide, by sacrificial
The silicon dioxide of domestic animal layer top and bottom is removed, and leaves behind the silicon dioxide on sidewall；Use oxygen ash chemical industry
Skill removes the mask layer (sacrifice layer) being exposed to surface；Dry etching is used to etch the conforma layer carried over,
And as hard mask etch silicon nitride and silicon substrate, form shallow trench, having of the shallow trench finally obtained isolation
The size of source region has two kinds, and the second thickness is the second size of the second requirement on devices, the first thickness and the second thickness
First size that is that spend and that be the first requirement on devices.
The method of the polysilicon gate forming patterning in another embodiment on substrate includes: form titanium dioxide
Silicon oxide gate dielectric layer, forms polysilicon gate, and forms mask layer (sacrifice layer) on polysilicon gate, and use light
Carving technology forms the mask graph with fisrt feature size；The method further includes at above-mentioned figure overlying
Lid layer of silicon dioxide conforma layer, forms the side wall of uniform fold mask graph, and on side wall, the thickness of thin film is
First thickness；Immediately row second time photoetching developing, photoresist covers a part of silicon dioxide conforma layer, will
The conforma layer of the part exposed is removed clean, and definition overlay area is the first device area, and expose portion is the
Two device areas；Remove photoresist and carry out depositing for the second time silicon dioxide, forming uniform fold mask graph
Side wall, deposit thickness is the second thickness, now first device area cover silicon dioxide thickness is first
Thickness adds the sum of the second thickness, the second device area thickness be the second thickness；Anisotropic etching two
Silicon oxide, removes the silicon dioxide of sacrifice layer top and bottom, leaves behind the thin film on sidewall；Use oxygen
Gas cineration technics removes the mask layer (sacrifice layer) being exposed to surface；Dry etching etching is used to carry over
Conforma layer, and as hard mask etches polycrystalline Si-gate and gate dielectric layer, form grid structure, finally obtain
The size of grid structure has two kinds, and the second thickness is the second size of the second requirement on devices, the first thickness and
Two thickness and the first size that is the first requirement on devices.
By the invention it is possible to be once lithographically formed the spacer with two kinds of thickness by increasing；And,
By this method, the figure of two kinds of characteristic sizes can disposably be etched, it might even be possible to unrestrictedly increase
Photoetching number of times forms the spacer spacer of various thickness, obtains the figure of more different characteristic size, full
The actual demand of foot integrated circuit, significant to the large-scale application of SADP.
Accompanying drawing explanation
In conjunction with accompanying drawing, and by with reference to detailed description below, it will more easily the present invention is had more complete
Understand and its adjoint advantage and feature is more easily understood, wherein:
Fig. 1 to Figure 11 schematically show employing bilateral wall technique according to the preferred embodiment of the invention
Form sectional view or the top view of each step of the method for ultralow size figure.
It should be noted that accompanying drawing is used for illustrating the present invention, and the unrestricted present invention.Note, represent structure
Accompanying drawing may be not necessarily drawn to scale.Further, in accompanying drawing, same or like element indicate identical or
The label that person is similar to.
Detailed description of the invention
In order to make present disclosure more clear and understandable, below in conjunction with specific embodiments and the drawings to this
Bright content is described in detail.
Fig. 1 to Figure 11 schematically show employing bilateral wall technique according to the preferred embodiment of the invention
Form sectional view or the top view of each step of the method for ultralow size figure.
As shown in Figure 1 to 11, bilateral wall technique is used to form ultralow chi according to the preferred embodiment of the invention
The method of very little figure includes:
Silicon substrate 1 is formed silicon nitride (not shown), and forms amorphous carbon layer (mask layer) on silicon nitride
2 (as shown in Figure 1), and use photoetching process formation to have the mask graph of fisrt feature size (such as Fig. 2
Sectional view shown in)；Wherein fisrt feature size is formed at or close high-resolution photomask etching system
The limit of optical resolution, the size at the resolution limit of present stage state-of-the-art immersed photoetching machine is
20-28 nanometer.
Aforementioned mask figure covers layer of silicon dioxide conforma layer 3 (such as the top view of Fig. 3 and cutting of Fig. 4
Shown in the figure of face), after this conforma layer 3, extended meeting forms the side wall (sectional view such as Fig. 5 of uniform fold mask graph
Shown in), on side wall, the thickness of thin film is the first thickness；
Immediately carrying out second time photoetching and develop, photoresist 4 covers a part of silicon dioxide conforma layer, covers
Part is defined as the first device area (as illustrated in the top plan view of fig. 6), is removed by the conforma layer of the part exposed
Totally (as shown in Figure 7), expose portion is defined as the second device area；
Remove photoresist (as shown in Figure 8) and carry out depositing for the second time silicon dioxide conforma layer 5, being formed uniformly
The side wall of coverage mask figure, deposit thickness is the second thickness, and now the first device area covers silicon dioxide
Thickness be the sum that the first thickness adds the second thickness, the second device area thickness be that the second thickness is (such as Fig. 9
Sectional view and Figure 10 top view shown in)；
Anisotropic etching silicon dioxide, removes the silicon dioxide of mask layer top and bottom, leaves behind
Silica membrane (as shown in figure 11) on sidewall；
Oxygen ashing process is used to remove the amorphous carbon layer (mask layer) being exposed to surface；
Dry etching is used to etch the silicon dioxide conforma layer carried over, and as hard mask etch silicon nitride
And silicon substrate, forming shallow trench, the size of the active area of the shallow trench finally obtained isolation has two kinds, and second
Thickness be the second size of the second requirement on devices, the first thickness and the second thickness and be the first requirement on devices
First size.
In the present invention, the size of the figure obtained as silicon dioxide or the silicon nitride of final etching mask
Having two kinds, two kinds of sizes are not limited by the physics limit of photoetching, are only determined by the thickness of side wall.
Using bilateral wall technique to form the method for ultralow size figure according to the preferred embodiment of the invention can be favourable
Apply in 20 nanometers and following IC manufacturing lithographic etch process.Such as, said method can conduct
The method forming the polysilicon gate of patterning on substrate.
<concrete technology example>
Describe concrete technology example according to embodiments of the present invention below, can perform following step successively:
Use thermal oxidation method to form the silicon dioxide layer of 3 to 5 nanometers on a silicon substrate, adopt at silicon dioxide layer
The silicon nitride layer of 50-80 nano thickness is formed with LPCVD；
With the amorphous carbon layer of the method deposition 50-200 nano thickness of PECVD on silicon nitride layer, by decomposing
C2H2, forms amorphous carbon, and technique initialization is: the flow of C2H2 is 1500sccm, and temperature is 400C, buffering
Gas He flow is 300-1500sccm, radio frequency be 13.56Mhz power be 800-1200W, pressure is 10
Torr；
Photoetching also etches amorphous carbon layer and is formed and have the figure of fisrt feature size, and the size of this example is 80 nanometers；
The method using ald (ALD) on above-mentioned figure forms silicon dioxide conforma layer, and technique sets
Be set to: 2Nte flow is 1mgm, power be the flow of 2000-3000W, O2 be 3000-4000sccm,
The flow of Ar is 1000-2000sccm；The thickness of conforma layer is 10-20 nanometer, and step coverage is 100%；
Carry out second time photoetching: spin coating gel method forms one layer of positive photoresist, carries out the second device area
Development, retains the first device area photoresist, and this example is that the drop-down metal-oxide-semiconductor region in 6T-SRAM region is carried out
Development, retains the photoresist in transmission metal-oxide-semiconductor region；
The conforma layer using the dry etching Pull-down metal-oxide-semiconductor region to coming out is removed；
Use cineration technics to get rid of all photoresists, carry out the method shape of second time ald (ALD)
Becoming silicon dioxide conforma layer, technique initialization is: 2Nte flow is 1mgm, and power is 2000-3000W, O2's
Flow be the flow of 3000-4000sccm, Ar be 1000-2000sccm；The thickness of conforma layer is that 15-20 receives
Rice, step coverage is 100%；
The anisotropic silicon dioxide getting rid of amorphous carbon top and bottom of using plasma etching is conformal
Layer, only leaves the silicon dioxide on side wall；
Using oxygen ashing process to remove amorphous carbon sacrifice layer, technique initialization is: the flow of O2 is
500-1500sccm, temperature is 200 degree, and power is 300W；
For hard mask, substrate is carried out dry etching with the silicon dioxide conforma layer of residual, form shallow trench isolation
Active area, the size of this active area is the thickness of conforma layer, the first device area (transmission metal-oxide-semiconductor)
A size of 25-40 nanometer；The size of the second device area (drop-down metal-oxide-semiconductor) is 10-20 nanometer.
The present invention uses advanced photoetching process to form the figure with fisrt feature size, and fisrt feature size connects
It is bordering on the physics limit of photoetching, the physics of photoetching can be limited by the method using double isolation double patterning molding
System is broken, and forms the figure much smaller than fisrt feature size, obtains two kinds of ultralow sizes by Twi-lithography
Figure, meets the figure transfer demand of 20 nanometers and following integrated circuit technology.
Furthermore, it is necessary to explanation, unless stated otherwise or point out, the otherwise term in description " the
One " each assembly during, the description such as " second ", " the 3rd " is used only for differentiation description, element, step
Deng rather than for representing the logical relation between each assembly, element, step or ordering relation etc..
Although it is understood that the present invention discloses as above with preferred embodiment, but above-described embodiment is also
It is not used to limit the present invention.For any those of ordinary skill in the art, without departing from skill of the present invention
In the case of art aspects, technical solution of the present invention is made many by the technology contents that all may utilize the disclosure above
Possible variation and modification, or it is revised as the Equivalent embodiments of equivalent variations.Therefore, every without departing from this
The content of bright technical scheme, according to the present invention technical spirit to any simple modification made for any of the above embodiments,
Equivalent variations and modification, all still fall within the range of technical solution of the present invention protection.
Claims (6)
1. one kind uses the method that bilateral wall technique forms ultralow size figure, it is characterised in that including: first
The mask layer carried out in photoetching for the first time etched substrate by a layer mask version has fisrt feature size to be formed
Figure；Then on this figure, deposit thin film material layer, form the conforma layer of uniform fold mask graph,
On side wall, the thickness of thin film is the first thickness；Carry out second time photoetching developing, with photoresist is covered one
Part thin-film material is defined as the first device area, using the thin film material of the expose portion as the second device area
Material is removed；Removing photoresist, the most only first device area is covered by thin-film material；Then at this figure
On carry out second time deposit, deposit thin film material layer, deposit thickness is the second thickness, now the first device
The thickness of region overlay material is the sum that the first thickness adds the second thickness, the second device area thickness be
Two thickness；Anisotropically etch thin-film material, the thin-film material of mask layer top and bottom is removed, only
Leave the thin-film material on sidewall；Cineration technics optionally removes mask layer, leaves behind thin-film material and is formed
Side wall；Utilize thin-film material to perform etching as the new mask of etching, form the superfinishing with two kinds of sizes
Thin figure, two kinds of sizes are determined by the first thickness and the second thickness depositing thin film.
The method that employing bilateral wall technique the most according to claim 1 forms ultralow size figure, it is special
Levying and be, mask layer is amorphous carbon film.
The method that employing bilateral wall technique the most according to claim 1 and 2 forms ultralow size figure,
It is characterized in that, fisrt feature size is equal to the pole of the optical resolution of high-resolution photomask etching system
Limit.
The method that employing bilateral wall technique the most according to claim 1 and 2 forms ultralow size figure,
It is characterized in that, thin-film material is silicon dioxide or silicon nitride.
The method that employing bilateral wall technique the most according to claim 1 and 2 forms ultralow size figure,
It is characterized in that, the size of the second device area is less than the size of the first device area.
6. one kind uses the method that bilateral wall technique forms ultralow size figure, it is characterised in that including: formed
Silicon dioxide gate dielectric layer, forms polysilicon gate, and forms mask layer on polysilicon gate, and use photoetching
Technique forms the mask graph with fisrt feature size；Mask graph covers layer of silicon dioxide conformal
Layer, forms the side wall of uniform fold mask graph, and on side wall, the thickness of thin film is the first thickness；Perform subsequently
Photoetching for the second time is also developed, and photoresist covers a part of silicon dioxide conforma layer, part conformal that will expose
Layer is removed clean, and definition overlay area is the first device area, and expose portion is the second device area；Remove
Photoresist also carries out depositing for the second time silicon dioxide, forms the side wall of uniform fold mask graph, deposit thickness
Being the second thickness, now the first device area covers the thickness of silicon dioxide is that the first thickness adds the second thickness
With, the second device area thickness be the second thickness；Anisotropic etching silicon dioxide, by mask layer
The silicon dioxide of top and bottom is removed, and leaves behind the thin film on sidewall；Oxygen ashing process is used to remove sudden and violent
It is exposed at the mask layer on surface；Use dry etching to etch the conforma layer carried over, and etch as hard mask
Polysilicon gate and gate dielectric layer, form grid structure, and the size of the grid structure finally obtained has two kinds, the
Two thickness be the second size of the second requirement on devices, the first thickness and the second thickness and be the first requirement on devices
First size.
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| CN201410253213.5A CN103996602B (en) | 2014-06-09 | 2014-06-09 | A kind of method using bilateral wall technique to form ultralow size figure |
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Citations (5)
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| TW201036033A (en) * | 2008-12-04 | 2010-10-01 | Micron Technology Inc | Methods of fabricating substrates |
| CN102540701A (en) * | 2010-12-28 | 2012-07-04 | 中国科学院微电子研究所 | Self-aligning secondary imaging method |
| CN103187300A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Fin type field effect transistor and formation method of fin type field effect transistor |
| CN103227152A (en) * | 2012-01-26 | 2013-07-31 | 格罗方德半导体公司 | Methods of forming SRAM devices using sidewall image transfer techniques |
| CN103578923A (en) * | 2012-08-06 | 2014-02-12 | 台湾积体电路制造股份有限公司 | Self-assembled monolayer for pattern formation |
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| TW201036033A (en) * | 2008-12-04 | 2010-10-01 | Micron Technology Inc | Methods of fabricating substrates |
| CN102540701A (en) * | 2010-12-28 | 2012-07-04 | 中国科学院微电子研究所 | Self-aligning secondary imaging method |
| CN103187300A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Fin type field effect transistor and formation method of fin type field effect transistor |
| CN103227152A (en) * | 2012-01-26 | 2013-07-31 | 格罗方德半导体公司 | Methods of forming SRAM devices using sidewall image transfer techniques |
| CN103578923A (en) * | 2012-08-06 | 2014-02-12 | 台湾积体电路制造股份有限公司 | Self-assembled monolayer for pattern formation |
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