CN103985353A - Light emitting control circuit, driving circuit thereof and organic light emitting diode display panel thereof - Google Patents

Abstract

The invention discloses a light-emitting control circuit, its driving circuit and its active matrix organic light-emitting diode display panel. The lighting control circuit includes a plurality of lighting control units. These light-emitting control units respectively receive a first clock signal, a second clock signal, a gate low voltage and a gate high voltage, and are used to provide multiple light-emitting signals to multiple components of the active matrix organic light-emitting diode display panel. pixels. Each light-emitting control unit determines to output a low gate voltage or a high gate voltage as the voltage level of the corresponding light-emitting signal based on the first clock signal and the second clock signal.

Description

Light-emitting control circuit, its driving circuit and its organic light-emitting diode display panel

technical field

The present invention relates to a control circuit, and in particular to a lighting control circuit, its driving circuit and its active matrix organic light emitting diode display panel.

Background technique

Since 1987, Kodak Corporation of the United States published the organic light emitting diode (Organic Light Emitting Diode, OLED) device with practical potential, which has attracted many manufacturers to invest in the research and mass production of OLED displays. Transistor liquid crystal display, TFT LCD), one of the most promising flat-panel display technologies in the future. Among them, OLED has the advantages of self-luminescence, high response speed, power saving, light and thin, wide viewing angle, wide color gamut, low operating voltage, high contrast, etc., and the manufacturing process is simple and low cost, and can be applied to flexible panels.

OLED displays can be broadly classified into passive matrix OLED displays and active matrix OLED displays. The main driving method of the active matrix OLED display is to use thin film transistor (TFT) elements, and use capacitors to store different data voltages, so as to control the gray scale of each pixel on the panel. In other words, the driving circuit of the active matrix OLED display provides multiple scanning signals to control the capacitance of each pixel to store the corresponding data voltage, and provides multiple light emitting signals to control each pixel to emit light according to the corresponding data voltage. When the driving circuit of the active matrix OLED display provides more control voltages, its circuit area will be larger, so that the frame width of the display panel will be affected. Therefore, the design of the driving circuit of the active matrix OLED display greatly affects the size of the display panel.

Contents of the invention

The invention provides a lighting control circuit, its driving circuit and its active matrix organic light emitting diode display panel, and the grid driving circuit and the lighting control circuit of the driving circuit can be separated to reduce the circuit area of the driving circuit.

The lighting control circuit of the present invention is suitable for an Active Matrix Organic Light Emitting Diodes (AMOLED) display panel. The light emission control circuit includes a plurality of light emission control units. These light-emitting control units respectively receive a first clock signal, a second clock signal, a gate low voltage and a gate high voltage, and are used to provide multiple light-emitting signals to multiple active matrix OLED display panels. pixels. Each light emitting control unit determines to output the gate low voltage or the gate high voltage as the voltage level of the corresponding light emitting signal according to the first clock signal and the second clock signal.

The driving circuit of the present invention is suitable for an active matrix OLED display panel. The driving circuit includes the above-mentioned light emitting control circuit and a gate driving circuit. The gate driving circuit includes a plurality of shift registers. The shift registers respectively receive a third clock signal, a fourth clock signal, gate low voltage and gate high voltage, and are used to provide a plurality of gate driving signals to the pixels.

The active matrix organic light emitting diode display panel of the present invention includes a plurality of pixels and the above-mentioned light emitting control circuit.

In an embodiment of the present invention, the first lighting control unit receives a lighting start signal, and the i-th lighting control unit receives the lighting signal provided by the i-1th lighting control unit, where i is a positive value greater than or equal to 2. integer.

In an embodiment of the present invention, each light emitting control unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor and a logic control unit. The first transistor has a first terminal, a second terminal and a first control terminal, wherein the first terminal receives the light-emitting start signal or the light-emitting signal provided by the i-1th light-emitting control unit, and the first control terminal receives the light-emitting signal provided by the i-1th light-emitting control unit. A clock signal. The second transistor has a third terminal, a fourth terminal and a second control terminal, wherein the third terminal receives the gate low voltage, the fourth terminal provides a corresponding light emitting signal, and the second control terminal is coupled to the second terminal. The third transistor has a fifth terminal, a sixth terminal and a third control terminal, wherein the fifth terminal is coupled to the second terminal, the sixth terminal receives the gate high voltage, and the third control terminal receives a logic control signal. The fourth transistor has a seventh terminal, an eighth terminal and a fourth control terminal, wherein the seventh terminal is coupled to the fourth terminal, the eighth terminal receives the gate high voltage, and the fourth control terminal receives the logic control signal. The first capacitor is coupled between the second clock signal and the second control terminal. The logic control unit receives at least one reference signal, and is coupled to the third control terminal and the fourth control terminal to provide a logic control signal.

In an embodiment of the present invention, the reference signal includes a light-emitting start signal or a light-emitting signal provided by the i-1th light-emitting control unit, and a first clock signal.

In an embodiment of the present invention, the logic control unit includes a fifth transistor, a sixth transistor, a seventh transistor and a second capacitor. The fifth transistor has a ninth terminal, a tenth terminal and a fifth control terminal, wherein the tenth terminal receives the gate high voltage, and the fifth control terminal receives the light-emitting start signal or the i-1th light-emitting control unit provided luminous signal. The sixth transistor has an eleventh terminal, a twelfth terminal and a sixth control terminal, wherein the eleventh terminal receives the gate low voltage, the twelfth terminal provides a logic control signal, and the sixth control terminal is coupled to the ninth end. The seventh transistor has a thirteenth terminal, a fourteenth terminal and a seventh control terminal, wherein the thirteenth terminal is coupled to the twelfth terminal, the fourteenth terminal receives the gate high voltage, and the seventh control terminal receives the light-emitting A start signal or a light-emitting signal provided by the i-1th light-emitting control unit. The second capacitor is coupled between the first clock signal and the ninth terminal.

In an embodiment of the present invention, the fifth control terminal and the seventh control terminal are coupled to the second terminal.

In an embodiment of the present invention, the fifth control terminal and the seventh control terminal are coupled to the first terminal.

In an embodiment of the present invention, the fifth control terminal is coupled to the first terminal, and the seventh control terminal is coupled to the second terminal.

In an embodiment of the present invention, the logic control unit further includes an eighth transistor and a third capacitor. The eighth transistor has a fifteenth terminal, a sixteenth terminal and an eighth control terminal, wherein the fifteenth terminal is coupled to the first terminal, the sixteenth terminal is coupled to the fifth control terminal and the seventh control terminal, and the eighth transistor is coupled to the fifth control terminal and the seventh control terminal. The eight control terminals receive the second clock signal. The third capacitor is coupled between the fifth control terminal and the gate high voltage.

In an embodiment of the invention, the duty cycles of the first clock signal and the second clock signal are the same.

In an embodiment of the present invention, the pulse widths of the light-emitting signals are inversely proportional to the duty ratio of the first clock signal.

In an embodiment of the present invention, the pulse width of the light-emitting signals is proportional to the pulse width of the light-emitting start signal.

In an embodiment of the present invention, each pixel includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, an organic light emitting diode and a storage capacitor. The ninth transistor has a seventeenth terminal, an eighteenth terminal and a ninth control terminal, wherein the eighteenth terminal receives an initial voltage, and the ninth control terminal receives a first scan signal. The tenth transistor has a nineteenth terminal, a twentieth terminal and a tenth control terminal, wherein the nineteenth terminal receives a system high voltage, and the tenth control terminal receives a corresponding light emitting signal. The eleventh transistor has a twenty-first terminal, a twenty-second terminal and an eleventh control terminal, wherein the twenty-first terminal is coupled to the twentieth terminal, and the eleventh control terminal is coupled to the seventeenth terminal . The twelfth transistor has a twenty-third terminal, a twenty-fourth terminal and a twelfth control terminal, wherein the twenty-third terminal is coupled to the eleventh control terminal, and the twenty-fourth terminal is coupled to the twenty-second terminal, and the twelfth control terminal receives a second scanning signal. The thirteenth transistor has a twenty-fifth terminal, a twenty-sixth terminal and a thirteenth control terminal, wherein the twenty-fifth terminal is coupled to the twentieth terminal, the twenty-sixth terminal receives a data voltage, and the thirteenth transistor receives a data voltage. The thirteenth control terminal receives the second scanning signal. The fourteenth transistor has a twenty-seventh terminal, a twenty-eighth terminal and a fourteenth control terminal, wherein the twenty-seventh terminal is coupled to the twenty-second terminal, and the fourteenth control terminal receives the corresponding light-emitting signal . The anode of the OLED is coupled to the twenty-eighth terminal, and the cathode of the OLED receives a system low voltage. The storage capacitor is coupled between the system high voltage and the seventeenth terminal.

Based on the above, the light emitting control circuit, its driving circuit and its active matrix organic light emitting diode display panel of the embodiment of the present invention separate the gate driving circuit and the light emitting control circuit of the driving circuit to reduce the circuit area of the driving circuit.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Description of drawings

1 is a system diagram of an active matrix organic light emitting diode display panel according to an embodiment of the present invention;

2A to 2C are respectively schematic diagrams of waveforms of a first clock signal, a second clock signal and a light emitting signal according to an embodiment of the present invention;

3A to 3C are respectively schematic diagrams of waveforms of a lighting start signal, a first clock signal, a second clock signal and a lighting signal according to an embodiment of the present invention;

FIG. 4 is a system schematic diagram of the lighting control unit in FIG. 1 according to an embodiment of the present invention;

5A to 5D are schematic circuit diagrams of the lighting control unit in FIG. 4 according to an embodiment of the present invention;

FIG. 6 is a schematic circuit diagram of the pixel in FIG. 1 according to an embodiment of the invention.

Among them, reference signs:

100: active matrix organic light emitting diode display panel

110: pixel array

111: scan line

113: multiple data lines

115: Luminous control line

120: drive circuit

121: Lighting control circuit

123: Gate drive circuit

125: Luminous control unit

127: shift register

410, 410a-410d: logic control unit

C1～C3: capacitance

CK1～CK4, CK1a～CK1c, CK2a～CK2c: clock signal

Cst: storage capacitor

EM, EM(n), EM(n-1), EMa(n), EMa(n+1), EMb(n), EMb(n+1), EMc(n), EMc(n+1), EMd(1), EMd(2), EMe(1), EMe(2), EMf(1), EMf(2): Luminescent signals

M1～M14, M5a～M5c, M7a, M7c: transistors

OD1: Organic Light Emitting Diode

OVDD: System high voltage

OVSS: System Low Voltage

P, PSa～PSc: pulse width

PX, PXa: pixels

SLC: logic control signal

SN1, SN2: gate drive signal

SRE: reference signal

STVG: gate start signal

STVL, STVLa～STVLc: Luminescence start signal

Vdata: data voltage

VGH: gate high voltage

VGL: Gate Low Voltage

Vint: initial voltage

Detailed ways

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

FIG. 1 is a system schematic diagram of an active matrix organic light emitting diode display panel according to an embodiment of the present invention. Referring to FIG. 1 , in this embodiment, an active matrix organic light emitting diode display panel 100 includes a pixel array 110 and a driving circuit 120 , wherein the driving circuit 120 includes a light emission control circuit 121 and a gate driving circuit 123 . The light emitting control circuit 121 is used for providing a plurality of light emitting signals EM, and the gate driving circuit 123 is used for providing a plurality of gate driving signals (such as SN1, SN2).

The pixel array 110 includes a plurality of pixels PX, a plurality of scan lines 111 , a plurality of data lines 113 and a plurality of light emission control lines 115 . Each scan line 111 is coupled between the corresponding pixel PX and the gate driving circuit 123 to transmit the corresponding gate driving signal (such as SN1 , SN2 ) to the corresponding pixel PX. Each data line 113 is coupled between the corresponding pixel PX and a source driving circuit (not shown), so as to transmit the corresponding data voltage Vdata to the corresponding pixel PX. Each light emission control line 115 is coupled between the corresponding pixel PX and the light emission control circuit 121 to transmit the corresponding light emission signal EM to the corresponding pixel PX.

The light emission control circuit 121 includes a plurality of light emission control units 125 . The light emission control units 125 respectively receive the clock signals CK1 , CK2 , the gate low voltage VGL and the gate high voltage VGH, and are controlled by the light emission start signal STVL to start. Next, the light emission control unit 125 provides light emission signals EM to the pixels PX on the display panel 100 according to the clock signals CK1 and CK2 . Wherein, each light emitting control unit 125 determines to output the gate low voltage VGL or the gate high voltage VGL as the voltage level of the corresponding light emitting signal EM according to the clock signals CK1 and CK2 . Moreover, the first light emission control unit 125 receives the light emission start signal STVL, the i light emission control unit 125 receives the light emission signal EM provided by the i-1 light emission control unit 125, and i is a positive integer greater than or equal to 2.

The gate driving circuit 123 includes a plurality of shift registers 127 . The shift registers 127 respectively receive the clock signals CK3 , CK4 , the low gate voltage VGL and the high gate voltage VGH, and are activated by the gate start signal STVG. Then, the shift registers 127 provide gate driving signals (such as SN1 and SN2 ) to the pixels PX on the display panel 100 according to the clock signals CK3 and CK4 . Wherein, each shift register 127 determines to output the clock signal CK3 or CK4 as the corresponding gate driving signal (such as SN1, SN2) according to the clock signal CK3 and CK4, and the clock signal CK3 and CK4 are mutually inverse signals . Moreover, the first shift register 127 receives the gate start signal STVG, and the i-th shift register 127 receives the gate drive signals (such as SN1, SN2) provided by the i-1 shift register 127 .

Based on the above, the operation of the light emission control circuit 121 of this embodiment is not related to the operation of the gate drive circuit 123, that is, the light emission control circuit 121 can operate independently, so the design of the light emission control circuit 121 of this embodiment can be simplified, and further The circuit area of the light emission control circuit 121 is reduced.

2A to 2C are respectively schematic diagrams of waveforms of a first clock signal, a second clock signal and a light emitting signal according to an embodiment of the present invention. Please refer to FIG. 1 and FIG. 2A to FIG. 2C , wherein the same or similar components use the same or similar reference numerals. In this embodiment, the pulse width of the clock signals CK1 and CK2 is P, that is, the duty cycles of the clock signals CK1 and CK2 are the same, and the pulse width P may be the same as one horizontal scanning period. Moreover, the pulse width of the light emitting signal EM is inversely proportional to the duty ratio of the clock signal CK1 or CK2.

Taking FIG. 2A as an example, the duty ratio of the clock signals CK1a and CK2a is 1/2 (ie 50%). At this time, the pulse width of the light emitting signals EMa(n) and EMa(n+1) is 2 P, for example, 2 horizontal scanning periods. In addition, the displacement (or delay time) between the light emitting signals EMa(n) and EMa(n+1) is 1 P, for example, 1 horizontal scanning period. Wherein, n is a positive integer.

Taking FIG. 2B as an example, the duty ratio of the clock signals CK1b and CK2b is 1/4 (ie 25%). At this time, the pulse width of the light emitting signals EMb(n) and EMb(n+1) is 4 P, for example, 4 horizontal scanning periods. In addition, the displacement (or delay time) between the light emitting signals EMb(n) and EMb(n+1) is 2 P, for example, 2 horizontal scanning periods.

Taking FIG. 2C as an example, the working ratio of the clock signals CK1c and CK2c is 1/6 (ie 16.7%). At this time, the pulse width of the light emitting signals EMc(n) and EMc(n+1) is 6 P, for example, 6 horizontal scanning periods. In addition, the displacement (or delay time) between the light emitting signals EMc(n) and EMc(n+1) is 3 P, for example, 3 horizontal scanning periods.

Wherein, the adjustment of the pulse width of the light emitting signal EM may depend on the design of the pixel array (such as 110 ). For example, if a single light emitting signal EM corresponds to a single row of pixels PX, the light emitting signals EMa(n) and EMa(n+1) can be used to drive the pixels PX; if a single light emitting signal EM corresponds to a double row of pixels PX, then the light emitting signal EMb can be used (n) and EMb(n+1) to drive the pixel PX; if a single luminescence signal EM corresponds to three rows of pixels PX, then the luminescence signal EMc(n) and EMc(n+1) can be used to drive the pixel PX, and the rest can be determined according to By analogy, details will not be repeated here, but this embodiment of the present invention is not limited thereto.

3A to 3C are waveform diagrams of a light-emitting start signal, a first clock signal, a second clock signal and a light-emitting signal, respectively, according to an embodiment of the present invention. Please refer to FIG. 1 , FIG. 2C and FIG. 3A to FIG. 3C , wherein the same or similar components use the same or similar labels. In this embodiment, the pulse width of the light emitting signal EM is proportional to the pulse width of the light emitting start signal STVL.

Taking FIG. 3A as an example, the duty ratio of the clock signals CK1c and CK2c is 1/6 (ie 16.7%), and the pulse width PSa of the light-emitting start signal STVLa is 6 P, for example, 6 horizontal scanning periods. At this time, the pulse width of the light emitting signals EMd( 1 ) and EMd( 2 ) is 6 P, for example, 6 horizontal scanning periods. In addition, the displacement (or delay time) between the light emitting signals EMd( 1 ) and EMd( 2 ) is 3 P, for example, 3 horizontal scanning periods.

Taking FIG. 3B as an example, the pulse width PSb of the lighting start signal STVLb is 12 P, for example, 12 horizontal scanning periods. At this time, the pulse width of the light emitting signals EMe(1) and EMe(2) is 12 P, for example, 12 horizontal scanning periods. In addition, the displacement (or delay time) between the light emitting signals EMe( 1 ) and EMe( 2 ) is 3 P, for example, 3 horizontal scanning periods.

Taking FIG. 3C as an example, the pulse width PSc of the lighting start signal STVLc is 18 P, for example, 18 horizontal scanning periods. At this time, the pulse width of the light emitting signals EMf(1) and EMf(2) is 18 P, for example, 18 horizontal scanning periods. In addition, the displacement (or delay time) between the light emitting signals EMf(1) and EMf(2) is 3 P, for example, 3 horizontal scanning periods.

FIG. 4 is a system diagram of the lighting control unit in FIG. 1 according to an embodiment of the present invention. Referring to FIG. 1 and FIG. 4, in this embodiment, the light emission control unit 125 may be a light emission control unit 400, wherein the same or similar elements use the same or similar symbols, and the light emission control unit 125 includes transistors M1-M4 (corresponding to the first transistors to fourth transistors), the capacitor C1 and the logic control unit 410. Wherein, the transistors M1 - M4 are P-type transistors as an example, but the embodiments of the present invention are not limited thereto.

The source of the transistor M1 (corresponding to the first terminal) receives the light-emitting start signal STVL or the light-emitting signal EM(n-1) provided by the n-1th light-emitting control unit 125, and the gate of the transistor M1 (corresponding to the first control terminal ) to receive the clock signal CK1 or CK2. The source of the transistor M2 (corresponding to the third terminal) receives the gate low voltage VGL, the drain of the transistor M2 (corresponding to the fourth terminal) provides the corresponding light emitting signal EM(n), and the gate of the transistor M2 (corresponding to the second control terminal ) is coupled to the drain of the transistor M1 (corresponding to the second terminal). The source of the transistor M3 (corresponding to the fifth terminal) is coupled to the drain of the transistor M1, the drain of the transistor M3 (corresponding to the sixth terminal) receives the gate high voltage VGH, and the gate of the transistor M3 (corresponding to the third control terminal) receives The logic control signal SLC provided by the logic control unit 410 .

The source of the transistor M4 (corresponding to the seventh terminal) is coupled to the drain of the transistor M2, the drain of the transistor M4 (corresponding to the eighth terminal) receives the gate high voltage VGH, and the gate of the transistor M4 (corresponding to the fourth control terminal) receives Logic control signal SLC. The capacitor C1 is coupled between the clock signal CK2 or CK1 and the gate of the transistor M2. The logic control unit 410 receives at least one reference signal SRE, and is coupled to the gates of the transistors M3 and M4 to provide a logic control signal SLC. Wherein, the reference signal SRE may include one or part of the lighting start signal STVL, the lighting signal EM(n-1) provided by the n-1th lighting control unit 125, and the clock signals CK2 and CK1, which may be based on It is usually set by those skilled in the art.

In this embodiment, when the gate of the transistor M1 receives the clock signal CK1, the capacitor C1 receives the clock signal CK2; otherwise, when the gate of the transistor M1 receives the clock signal CK2, the capacitor C1 receives the clock signal CK1.

5A to 5D are schematic circuit diagrams of the lighting control unit shown in FIG. 4 according to an embodiment of the present invention. Please refer to FIG. 1 , FIG. 4 and FIGS. 5A to 5D , wherein the same or similar components use the same or similar labels. In this embodiment, the reference signal SRE includes a light-emitting start signal STVL or a light-emitting signal EM(n−1), and a clock signal CK1 or CK2 .

Taking FIG. 5A as an example, the logic control unit 410a includes transistors M5 - M7 (corresponding to the fifth transistor to the seventh transistor) and a capacitor C2. Wherein, the transistors M5 - M7 are P-type transistors as an example, but the embodiments of the present invention are not limited thereto. The drain of the transistor M5 (corresponding to the tenth terminal) receives the gate high voltage VGH, and the gate of the transistor M5 (corresponding to the fifth control terminal) is coupled to the drain of the transistor M1 to receive the light-emitting start signal STVL through the turned-on transistor M1 Or luminescent signal EM(n-1). The source of the transistor M6 (corresponding to the eleventh terminal) receives the gate low voltage VGL, the drain of the transistor M6 (corresponding to the twelfth terminal) provides a logic control signal SLC, and the gate of the transistor M6 (corresponding to the sixth control terminal) is coupled to Connect to the source of transistor M5 (corresponding to the ninth terminal). The source of the transistor M7 (corresponding to the thirteenth terminal) is coupled to the drain of the transistor M6, the drain of the transistor M7 (corresponding to the fourteenth terminal) receives the gate high voltage VGH, and the gate of the transistor M7 (corresponding to the seventh control terminal ) is coupled to the drain of the transistor M1 to receive the light-emitting start signal STVL or the light-emitting signal EM(n−1) through the turned-on transistor M1. The capacitor C2 is coupled between the clock signal CK1 or CK2 and the source of the transistor M5.

In this embodiment, when the gate of the transistor M1 receives the clock signal CK1, the capacitor C1 receives the clock signal CK2, and the capacitor C2 receives the clock signal CK1; otherwise, when the gate of the transistor M1 receives the clock signal CK2, The capacitor C1 receives the clock signal CK1, and the capacitor C2 receives the clock signal CK2.

According to the embodiment shown in FIG. 5A and FIG. 5B, the difference between the logic control unit 410b and the logic control unit 410a lies in the transistors M5a and M7a, wherein the gates of the transistors M5a and M7a are coupled to the source of the transistor M1 to receive the light-emitting start signal STVL or luminescence signal EM(n-1).

According to the embodiment shown in FIG. 5A and FIG. 5C , the difference between the logic control unit 410c and the logic control unit 410a is the transistor M5b, wherein the gate of the transistor M5b is coupled to the source of the transistor M1 to receive the light-emitting start signal STVL or the light-emitting signal EM(n-1). At this time, the gate voltages of the transistors M6 and M7 change more consistent, that is, the switching speed of the voltage level of the logic control signal SLC is faster, thereby reducing the chance of the light-emitting control unit 125 operating incorrectly.

According to the embodiment shown in FIG. 5A and FIG. 5D , the difference between the logic control unit 410d and the logic control unit 410a is that it also includes a transistor M8 and a capacitor C3, wherein the transistor M8 is a P-type transistor as an example, but the embodiment of the present invention does not use This is the limit. The source of the transistor M8 (corresponding to the fifteenth terminal) is coupled to the source of the transistor M1, the drain of the transistor M8 (corresponding to the sixteenth terminal) is coupled to the gates of the transistors M5c and M7c, and the gate of the transistor M8 (corresponding to the first Eight control terminals) receive the clock signal CK2 or CK1. The capacitor C3 is coupled between the gate of the transistor M5c and the gate high voltage VGH. The gates of the transistors M5c and M7c receive the light-emitting start signal STVL or the light-emitting signal EM(n−1) through the turned-on transistor M8. In this embodiment, when the gate of the transistor M1 receives the clock signal CK1, the capacitor C1 receives the clock signal CK2, the capacitor C2 receives the clock signal CK1, and the gate of the transistor M8 receives the clock signal CK2; When the gate of M1 receives the clock signal CK2, the capacitor C1 receives the clock signal CK1, the capacitor C2 receives the clock signal CK2, and the gate of the transistor M8 receives the clock signal CK1.

FIG. 6 is a schematic circuit diagram of the pixel in FIG. 1 according to an embodiment of the invention. Referring to FIG. 1 and FIG. 6 , the pixel PX may be the pixel PXa. In this embodiment, the pixel PXa includes transistors M9-M14 (corresponding to the ninth to fourteenth transistors), a storage capacitor Cst and an organic light emitting diode OD1, wherein the transistors M9-M14 are P-type transistors as an example, but the implementation of the present invention Examples are not limited to this.

The drain of the transistor M9 (corresponding to the eighteenth terminal) receives the initial voltage Vint, and the gate of the transistor M9 (corresponding to the ninth control terminal) receives the corresponding scanning signal SN1. The source of the transistor M10 (corresponding to the nineteenth terminal) receives the system high voltage OVDD, and the gate of the transistor M10 (corresponding to the tenth control terminal) receives the corresponding light emitting signal EM. The source of the transistor M11 (corresponding to the twenty-first terminal) is coupled to the drain of the transistor M10 (corresponding to the twentieth terminal), and the gate of the transistor M11 (corresponding to the eleventh control terminal) is coupled to the source of the transistor M9 (corresponding to the end seventeen).

The source of the transistor M12 (corresponding to the twenty-third terminal) is coupled to the gate of the transistor M11 (corresponding to the eleventh control terminal), and the drain of the transistor M12 (corresponding to the twenty-fourth terminal) is coupled to the drain of the transistor M11, The gate of the transistor M12 (corresponding to the twelfth control terminal) receives the corresponding scan signal SN2. The source of the transistor M13 (corresponding to the twenty-fifth terminal) is coupled to the drain of the transistor M10 (corresponding to the twentieth terminal), and the drain of the transistor M13 (corresponding to the twenty-sixth terminal) receives the corresponding data voltage Vdata, and the transistor M13 The gate (corresponding to the thirteenth control terminal) receives the corresponding scan signal SN2. The source of the transistor M14 (corresponding to the twenty-seventh terminal) is coupled to the drain of the transistor M11, and the gate of the transistor M14 (corresponding to the fourteenth control terminal) receives the corresponding light emitting signal EM. The anode of the organic light emitting diode OD1 is coupled to the drain of the transistor M14 (corresponding to the twenty-eighth terminal), and the cathode of the organic light emitting diode OD1 receives the system low voltage OVSS. The storage capacitor Cst is coupled between the OVDD system high voltage and the source of the transistor M9.

To sum up, the light emitting control circuit, its driving circuit and its active matrix organic light emitting diode display panel of the embodiment of the present invention separate the gate driving circuit and the light emitting control circuit of the driving circuit to reduce the circuit area of the driving circuit. Moreover, the pulse width of the light-emitting signal can be changed by adjusting the working ratio of the clock signal, thereby further reducing the circuit area of the light-emitting control circuit. Furthermore, the pulse width of the light-emitting signal can be changed by adjusting the pulse width of the light-emitting start signal, so as to improve the picture quality of the display panel.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

Claims (37)

1. an emission control circuit, is applicable to an active-matrix organic LED display panel, it is characterized in that, comprising:

Multiple luminous controling units, receive respectively one first clock signal, one second clock signal, a grid low-voltage and a grid high voltage, and in order to the multiple pixels of multiple luminous signals to this active-matrix organic LED display panel to be provided, wherein each described luminous controling unit determines this grid low-voltage of output or this grid high voltage voltage level as corresponding luminous signal according to this first clock signal and this second clock signal.

2. emission control circuit according to claim 1, it is characterized in that, the 1st luminous controling unit receives a luminous start signal, and i luminous controling unit receives the luminous signal that i-1 luminous controling unit provides, and i is more than or equal to 2 positive integer.

3. emission control circuit according to claim 2, is characterized in that, each described luminous controling unit comprises:

One the first transistor, has a first end, one second end and one first control end, and this first end receives this luminous start signal or i-1 the luminous signal that luminous controling unit provides, and this first control end receives this first clock signal;

One transistor seconds, has one the 3rd end, one the 4th end and one second control end, and the 3rd termination is received this grid low-voltage, and the 4th end provides corresponding luminous signal, and this second control end couples this second end;

One the 3rd transistor, has a five terminal, one the 6th end and one the 3rd control end, and this five terminal couples this second end, and the 6th termination is received this grid high voltage, and the 3rd control end receives a logic control signal;

One the 4th transistor, has one the 7th end, one the 8th end and one the 4th control end, and the 7th end couples the 4th end, and the 8th termination is received this grid high voltage, and the 4th control end receives this logic control signal;

One first electric capacity, is coupled between this second clock signal and this second control end; And

One logic control element, receives at least one reference signal, and couples the 3rd control end and the 4th control end so that this logic control signal to be provided.

4. emission control circuit according to claim 3, is characterized in that, this at least one reference signal comprises this luminous start signal or i-1 the luminous signal that luminous controling unit provides, and this first clock signal.

5. emission control circuit according to claim 4, is characterized in that, this logic control element comprises:

One the 5th transistor, has one the 9th end, 1 the tenth end and one the 5th control end, and the tenth termination is received this grid high voltage, and the 5th control end receives this luminous start signal or i-1 the luminous signal that luminous controling unit provides;

One the 6th transistor, has 1 the tenth one end, 1 the 12 end and one the 6th control end, and the tenth one end receives this grid low-voltage, and the 12 end provides this logic control signal, and the 6th control end couples the 9th end;

One the 7th transistor, there is 1 the 13 end, 1 the 14 end and one the 7th control end, the 13 end couples the 12 end, and the 14 termination is received this grid high voltage, and the 7th control end receives this luminous start signal or i-1 the luminous signal that luminous controling unit provides; And

One second electric capacity, is coupled between this first clock signal and the 9th end.

6. emission control circuit according to claim 5, is characterized in that, the 5th control end and the 7th control end couple this second end.

7. emission control circuit according to claim 5, is characterized in that, the 5th control end and the 7th control end couple this first end.

8. emission control circuit according to claim 5, is characterized in that, the 5th control end couples this first end, and the 7th control end couples this second end.

9. emission control circuit according to claim 5, is characterized in that, this logic control element also comprises:

One the 8th transistor, has 1 the tenth five terminal, 1 the 16 end and one the 8th control end, and the tenth five terminal couples this first end, and the 16 end couples the 5th control end and the 7th control end, and the 8th control end receives this second clock signal; And

One the 3rd electric capacity, is coupled between the 5th control end and this grid high voltage.

10. emission control circuit according to claim 1, is characterized in that, this first clock signal is identical with the work period of this second clock signal.

11. emission control circuits according to claim 10, is characterized in that, the pulse bandwidth of described luminous signal is inversely proportional to the work ratio of this first clock signal.

12. emission control circuits according to claim 10, is characterized in that, the pulse bandwidth of described luminous signal is proportional to the pulse bandwidth of this luminous start signal.

13. 1 kinds of driving circuits, are applicable to an active-matrix organic LED display panel, it is characterized in that, comprising:

One emission control circuit, comprising:

Multiple luminous controling units, receive respectively one first clock signal, one second clock signal, a grid low-voltage and a grid high voltage, and in order to the multiple pixels of multiple luminous signals to this active-matrix organic LED display panel to be provided, wherein each described luminous controling unit determines this grid low-voltage of output or this grid high voltage voltage level as corresponding luminous signal according to this first clock signal and this second clock signal; And

One gate driver circuit, comprising:

Multiple displacement working storages, receive respectively one the 3rd clock signal, one the 4th clock signal, this grid low-voltage and this grid high voltage, and in order to provide multiple gate drive signals to described pixel.

14. driving circuits according to claim 13, is characterized in that, the 1st luminous controling unit receives a luminous start signal, and i luminous controling unit receives the luminous signal that i-1 luminous controling unit provides, and i is more than or equal to 2 positive integer.

15. driving circuits according to claim 14, is characterized in that, each described luminous controling unit comprises:

One the first transistor, has a first end, one second end and one first control end, and this first end receives this luminous start signal or i-1 the luminous signal that luminous controling unit provides, and this first control end receives this first clock signal;

One transistor seconds, has one the 3rd end, one the 4th end and one second control end, and the 3rd termination is received this grid low-voltage, and the 4th end provides corresponding luminous signal, and this second control end couples this second end;

One the 3rd transistor, has a five terminal, one the 6th end and one the 3rd control end, and this five terminal couples this second end, and the 6th termination is received this grid high voltage, and the 3rd control end receives a logic control signal;

One the 4th transistor, has one the 7th end, one the 8th end and one the 4th control end, and the 7th end couples the 4th end, and the 8th termination is received this grid high voltage, and the 4th control end receives this logic control signal;

One first electric capacity, is coupled between this second clock signal and this second control end; And

One logic control element, receives at least one reference signal, and couples the 3rd control end and the 4th control end so that this logic control signal to be provided.

16. driving circuits according to claim 15, is characterized in that, this at least one reference signal comprises this luminous start signal or i-1 the luminous signal that luminous controling unit provides, and this first clock signal.

17. driving circuits according to claim 16, is characterized in that, this logic control element comprises:

One the 5th transistor, has one the 9th end, 1 the tenth end and one the 5th control end, and the tenth termination is received this grid high voltage, and the 5th control end receives this luminous start signal or i-1 the luminous signal that luminous controling unit provides;

One the 6th transistor, has 1 the tenth one end, 1 the 12 end and one the 6th control end, and the tenth one end receives this grid low-voltage, and the 12 end provides this logic control signal, and the 6th control end couples the 9th end;

One the 7th transistor, there is 1 the 13 end, 1 the 14 end and one the 7th control end, the 13 end couples the 12 end, and the 14 termination is received this grid high voltage, and the 7th control end receives this luminous start signal or i-1 the luminous signal that luminous controling unit provides; And

One second electric capacity, is coupled between this first clock signal and the 9th end.

18. driving circuits according to claim 17, is characterized in that, the 5th control end and the 7th control end couple this second end.

19. driving circuits according to claim 17, is characterized in that, the 5th control end and the 7th control end couple this first end.

20. driving circuits according to claim 17, is characterized in that, the 5th control end couples this first end, and the 7th control end couples this second end.

21. driving circuits according to claim 17, is characterized in that, this logic control element also comprises:

One the 8th transistor, has 1 the tenth five terminal, 1 the 16 end and one the 8th control end, and the tenth five terminal couples this first end, and the 16 end couples the 5th control end and the 7th control end, and the 8th control end receives this second clock signal; And

One the 3rd electric capacity, is coupled between the 5th control end and this grid high voltage.

22. driving circuits according to claim 13, is characterized in that, this first clock signal is identical with the work period of this second clock signal.

23. driving circuits according to claim 22, is characterized in that, the pulse bandwidth of described luminous signal is inversely proportional to the work ratio of this first clock signal.

24. driving circuits according to claim 22, is characterized in that, the pulse bandwidth of described luminous signal is proportional to the pulse bandwidth of this luminous start signal.

25. 1 kinds of active-matrix organic LED display panels, is characterized in that, comprising:

Multiple pixels; And

Multiple luminous controling units, receive respectively one first clock signal, one second clock signal, a grid low-voltage and a grid high voltage, and in order to provide multiple luminous signals to described pixel, wherein each described luminous controling unit determines this grid low-voltage of output or this grid high voltage voltage level as corresponding luminous signal according to this first clock signal and this second clock signal.

26. active-matrix organic LED display panels according to claim 25, it is characterized in that, the 1st luminous controling unit receives a luminous start signal, i luminous controling unit receives the luminous signal that i-1 luminous controling unit provides, and i is more than or equal to 2 positive integer.

27. active-matrix organic LED display panels according to claim 26, is characterized in that, each described luminous controling unit comprises:

One the first transistor, has a first end, one second end and one first control end, and this first end receives this luminous start signal or i-1 the luminous signal that luminous controling unit provides, and this first control end receives this first clock signal;

One transistor seconds, has one the 3rd end, one the 4th end and one second control end, and the 3rd termination is received this grid low-voltage, and the 4th end provides corresponding luminous signal, and this second control end couples this second end;

One the 3rd transistor, has a five terminal, one the 6th end and one the 3rd control end, and this five terminal couples this second end, and the 6th termination is received this grid high voltage, and the 3rd control end receives a logic control signal;

One the 4th transistor, has one the 7th end, one the 8th end and one the 4th control end, and the 7th end couples the 4th end, and the 8th termination is received this grid high voltage, and the 4th control end receives this logic control signal;

One first electric capacity, is coupled between this second clock signal and this second control end; And

One logic control element, receives at least one reference signal, and couples the 3rd control end and the 4th control end so that this logic control signal to be provided.

28. active-matrix organic LED display panels according to claim 27, is characterized in that, this at least one reference signal comprises this luminous start signal or i-1 the luminous signal that luminous controling unit provides, and this first clock signal.

29. active-matrix organic LED display panels according to claim 28, is characterized in that, this logic control element comprises:

One the 5th transistor, has one the 9th end, 1 the tenth end and one the 5th control end, and the tenth termination is received this grid high voltage, and the 5th control end receives this luminous start signal or i-1 the luminous signal that luminous controling unit provides;

One the 6th transistor, has 1 the tenth one end, 1 the 12 end and one the 6th control end, and the tenth one end receives this grid low-voltage, and the 12 end provides this logic control signal, and the 6th control end couples the 9th end;

One the 7th transistor, there is 1 the 13 end, 1 the 14 end and one the 7th control end, the 13 end couples the 12 end, and the 14 termination is received this grid high voltage, and the 7th control end receives this luminous start signal or i-1 the luminous signal that luminous controling unit provides; And

One second electric capacity, is coupled between this first clock signal and the 9th end.

30. active-matrix organic LED display panels according to claim 29, is characterized in that, the 5th control end and the 7th control end couple this second end.

31. active-matrix organic LED display panels according to claim 29, is characterized in that, the 5th control end and the 7th control end couple this first end.

32. active-matrix organic LED display panels according to claim 29, is characterized in that, the 5th control end couples this first end, and the 7th control end couples this second end.

33. active-matrix organic LED display panels according to claim 29, is characterized in that, this logic control element also comprises:

One the 8th transistor, has 1 the tenth five terminal, 1 the 16 end and one the 8th control end, and the tenth five terminal couples this first end, and the 16 end couples the 5th control end and the 7th control end, and the 8th control end receives this second clock signal; And

One the 3rd electric capacity, is coupled between the 5th control end and this grid high voltage.

34. active-matrix organic LED display panels according to claim 25, is characterized in that, this first clock signal is identical with the work period of this second clock signal.

35. active-matrix organic LED display panels according to claim 34, is characterized in that, the pulse bandwidth of described luminous signal is inversely proportional to the work ratio of this first clock signal.

36. active-matrix organic LED display panels according to claim 34, is characterized in that, the pulse bandwidth of described luminous signal is proportional to the pulse bandwidth of this luminous start signal.

37. active-matrix organic LED display panels according to claim 25, is characterized in that, each described pixel comprises:

One the 9th transistor, has 1 the 17 end, 1 the 18 end and one the 9th control end, and the 18 termination is received an initial voltage, and the 9th control end receives one first sweep signal;

The tenth transistor, has 1 the 19 end, one the 20 end and 1 the tenth control end, and the 19 termination is received a system high voltage, and the tenth control end receives corresponding luminous signal;

The 11 transistor, has one the 20 one end, one the 22 end and 1 the 11 control end, and the 20 one end couples the 20 end, and the 11 control end couples the 17 end;

The tenth two-transistor, has one the 23 end, one the 24 end and 1 the 12 control end, and the 23 end couples the 11 control end, and the 24 end couples the 22 end, and the 12 control end receives one second sweep signal;

The 13 transistor, has one the 20 five terminal, one the 26 end and 1 the 13 control end, and the 20 five terminal couples the 20 end, and the 26 termination is received a data voltage, and the 13 control end receives this second sweep signal;

The 14 transistor, has one the 27 end, one the 28 end and 1 the 14 control end, and the 27 end couples the 22 end, and the 14 control end receives corresponding luminous signal;

One Organic Light Emitting Diode, the anode of this Organic Light Emitting Diode couples the 28 end, and the negative electrode of this Organic Light Emitting Diode receives a system low-voltage; And

One storage capacitors, is coupled between this system high voltage and the 17 end.