CN103943502B - Fin formula field effect transistor and forming method thereof - Google Patents

Abstract

A fin field effect transistor and its forming method, wherein the forming method of the fin field effect transistor includes: providing a semiconductor substrate, the semiconductor substrate has a first region and a second region, the first region and There are raised fins in the second region and a gate structure on the fins; first sidewalls are formed on both sides of the gate structure in the first region, and part of the fins covered by the first sidewalls The portion constitutes a first negative covering region; second sidewalls are formed on both sides of the gate structure in the second region, the width of the second sidewalls is smaller than the width of the first sidewalls, and the second sidewalls The covered part of the fin constitutes a second negative covering region; ion implantation is performed on the fins on both sides of the gate structure in the first region and the second region to form a source region and a drain region. The fin field effect transistor forming method of the present invention can form fin field effect transistors with different threshold voltages, and the process is simple.

Description

Fin field effect transistor and method of forming the same

technical field

The invention relates to the technical field of semiconductors, in particular to a fin field effect transistor and a forming method thereof.

Background technique

With the advancement of integrated circuit technology, the integration level of the chip is getting higher and higher, and the scale is getting larger and larger, but the power consumption of the chip is also increasing. A single chip usually includes a core logic transistor area and an input/output (I/O) transistor area. The threshold voltage of the core logic transistor is low to reduce system power consumption, and the threshold voltage of the input/output transistor is high to ensure high drive capability and breakdown voltage. Therefore, how to obtain transistors with different threshold voltages on a single chip has become the focus of research.

Please refer to FIG. 1, which is a schematic structural diagram of a MOS transistor in the prior art, including: a semiconductor substrate 100; a gate dielectric layer 102 located on the semiconductor substrate 100; a work function layer 103 located on the gate dielectric layer 102 ; the gate electrode layer 104 located on the work function layer 103; the sidewalls 105 located on both sides of the dielectric layer 102, the work function layer 103 and the gate electrode layer 104; The source region and the drain region 106 in the semiconductor substrate 100 on the side. In the MOS transistors of the prior art, the threshold voltage of the MOS transistor is adjusted by changing the work function difference between the gate electrode of the MOS transistor and the gate dielectric layer by selecting an appropriate material for the work function layer 103, such as TiN, TaAl or TiC. , to obtain transistors with different threshold voltages on the same chip, so that the threshold voltage of the input/output transistor is higher, and the threshold voltage of the core logic transistor is lower. Since the work function layer 103 is usually a multi-layer structure, and the materials of the work function layer applied to NMOS transistors and PMOS transistors are different, the formation process is complicated. Especially in the fin field effect transistor, the work function layer is formed on the fin protruding from the semiconductor substrate, which further increases the difficulty of the process and the cost is high.

Therefore, the prior art method for forming fin field effect transistors with multiple threshold voltages is complicated in process and high in cost.

For other methods of forming multi-threshold voltage transistors, reference may also be made to US Patent Application Publication No. US2011/0248351A1.

Contents of the invention

The problem solved by the invention is that the process of forming multi-threshold voltage transistors in the prior art is complicated and the cost is high.

In order to solve the above problems, the present invention proposes a method for forming a fin field effect transistor, comprising: providing a semiconductor substrate, the semiconductor substrate has a first region and a second region, and the first region and the second region There are protruding fins and a gate structure on the fins, the gate structure covers part of the top and sidewalls of the fins; a second gate structure is formed on both sides of the gate structure in the first region. A side wall, the part of the fin covered by the first side wall constitutes a first negative cover area; a second side wall is formed on both sides of the gate structure in the second region, and the width of the second side wall is smaller than the The width of the first sidewall, the part of the fins covered by the second sidewall constitutes the second negative cover region; ion implantation is performed on the fins on both sides of the gate structure in the first region and the second region to form source and drain regions.

Optionally, the width of the second negative masking area is smaller than the width of the first negative masking area.

Optionally, the width of the first negative masking region ranges from 300 angstroms to 500 angstroms.

Optionally, the width of the second negative masking region ranges from 10 angstroms to 50 angstroms.

Optionally, the fin field effect transistor formed in the first region serves as an input/output transistor.

Optionally, the doping concentration of the first negative covering region is the same as that of the channel region of the input/output transistor.

Optionally, the method further includes performing ion implantation on the first negative covering region at the drain region end of the input/output transistor to form an inversion doped region.

Optionally, the doping type of the inverse doping region is opposite to that of the source region and the drain region of the input/output transistor.

Optionally, the width of the inversion doped region ranges from 1 angstrom to 300 angstrom.

Optionally, the fin field effect transistor formed in the second region serves as a core logic transistor.

Optionally, the doping concentration of the second negative covering region is the same as that of the channel region of the core logic transistor.

Optionally, the first sidewall and the second sidewall are made of high dielectric constant material.

Optionally, the high dielectric constant material is one or more of HfO ₂ , Al ₂ O ₃ , ZrO ₂ , HfSiO, HfSiON, HfTaO and HfZrO.

Optionally, the method further includes performing pre-amorphization ion implantation on the fins on both sides of the gate structure in the first region and the second region.

Optionally, the implanted ions of the pre-amorphization ion implantation are Si, C, Ge, Xe or Ar.

Correspondingly, the present invention also proposes a fin field effect transistor, comprising: a semiconductor substrate, the semiconductor substrate has a first region and a second region, and the first region and the second region have raised a fin; a gate structure located on the fin, the gate structure covering part of the top and sidewalls of the fin; first sidewalls located on both sides of the gate structure in the first region, the Part of the fin covered by the first sidewall constitutes a first negative cover area; second sidewalls located on both sides of the gate structure in the second region, the width of the second sidewall is greater than that of the first sidewall The part of the fin covered by the second spacer constitutes the second negative cover area; the source region and the drain region in the fin located on both sides of the gate structure in the first region and the second region.

Optionally, the width of the second negative masking area is smaller than the width of the first negative masking area.

Optionally, the first area is an input/output transistor area, and the second area is a core logic transistor area.

Optionally, it also includes an inversion doped region located in the first negative covering region at the drain region end of the input/output transistor, the doping type of the inversion doped region is the same as that of the source of the input/output transistor The doping types of the region and the drain region are opposite, and the width of the inversion doping region ranges from 1 angstrom to 300 angstroms.

Optionally, the first sidewall and the second sidewall are made of high dielectric constant material.

Compared with the prior art, the present invention has the following advantages:

In the method for forming a fin field effect transistor according to an embodiment of the present invention, first sidewalls are formed on both sides of the gate structure in the first region, and second sidewalls are formed on both sides of the gate structure in the second region. The widths of the first side wall and the second side wall are different, and the widths of the first negative covering area under the first side wall and the second negative covering area under the second side wall are different. In a FinFET with a negative cover region, different widths of the negative cover region lead to different effective channel widths of the subsequently formed FinFET, which changes the electric field distribution in the channel region and affects the FinFET. threshold voltage. The embodiment of the present invention utilizes the influence of the width of the negative covering region on the threshold voltage of the FinFET, and controls the width of the sidewalls formed in the first region and the second region during the formation of the FinFET. The widths of the first negative cover region and the second negative cover region are controlled to obtain fin field effect transistors with different threshold voltages, and the process is simple and the cost is low.

Further, in the method for forming a fin field effect transistor in the embodiment of the present invention, the fin field effect transistor formed in the first region is used as an input/output transistor, since the input/output transistor usually requires a higher threshold voltage and Therefore, ion implantation is performed on the first negative covering region at the drain region end of the input/output transistor to form an inversion doped region. The doping type of the inversion doping region is opposite to the doping type of the source region and the drain region of the input/output transistor, and a potential barrier is formed between the inversion doping region and the drain region, further improving the breakdown and threshold voltages of the input/output transistors described above.

Correspondingly, the FinFETs in the embodiment of the present invention are formed by the above method, so the FinFETs located in the first region and the FinFETs located in the second region have different threshold voltages.

Description of drawings

FIG. 1 is a schematic structural diagram of a MOS transistor in the prior art;

FIG. 2 to FIG. 6 are structural schematic diagrams of the forming process of the fin field effect transistor according to the embodiment of the present invention.

detailed description

It can be seen from the background art that in the prior art, the process of forming the fin field effect transistor with multiple threshold voltages is complicated and the cost is high.

The inventors of the present invention have studied the formation method of a fin field effect transistor with a negative cover region (Underlap), and found that because the negative cover region is not subjected to lightly doped drain implantation (LDD) and halo implantation (Halo Implantation), the The above-mentioned negative covering region can increase the width of the effective channel region of the fin field effect transistor and alleviate the short channel effect. Moreover, the widths of different negative cover regions have different influences on the electric field distribution in the channel region of the fin field effect transistor, and have different effects on the threshold voltage. Therefore, fin field effects with different threshold voltages can be obtained by controlling the width of the formed negative cover region. transistor.

Based on the above studies, the inventors of the present invention proposed a method for forming a fin field effect transistor, forming first sidewalls and second sidewalls with different widths on both sides of the gate structure in the first region and the second region of the semiconductor substrate. Two sidewalls, because the width of the first negative cover area under the first side wall is different from that of the second negative cover area under the second side wall, the fin field effect transistor formed in the first area The threshold voltage of the fin field effect transistor formed in the second region is different from that of the fin field effect transistor. The process difficulty of forming fin field effect transistors with different threshold voltages is reduced, and the manufacturing cost is low.

The specific embodiments will be described in detail below in conjunction with the accompanying drawings, and the above-mentioned purpose and advantages of the present invention will be more clear.

FIG. 2 to FIG. 6 are structural schematic diagrams of the forming process of the fin field effect transistor according to the embodiment of the present invention.

Please refer to FIG. 2 , a semiconductor substrate 200 is provided, the semiconductor substrate 200 has a first region I and a second region II, the first region I and the second region II have protruding fins 202 located in the The gate structure 203 on the fin 202 , the gate structure 203 covers part of the top and sidewall of the fin 202 .

The semiconductor substrate 200 may be silicon or silicon-on-insulator (SOI), and the semiconductor substrate 200 may also be germanium, silicon germanium, gallium arsenide, or germanium-on-insulator. The semiconductor substrate 200 has a first region I and a second region II, and the first region I and the second region II are respectively used to form fin field effect transistors with different threshold voltages. The surface of the semiconductor substrate 200 has a raised fin 202, and the connection between the fin 202 and the semiconductor substrate 200 can be integrated, for example, the fin 202 is connected to the semiconductor substrate 200 The raised structure formed after etching. The gate structure 203 is located on the fin 202 , and the gate structure 203 covers part of the top and sidewall of the fin 202 . In this embodiment, the gate structure 203 includes a gate dielectric layer and a gate electrode layer (not shown), the material of the gate dielectric layer is silicon oxide, and the material of the gate electrode layer is polysilicon.

In another embodiment, the gate structure is a dummy gate, and the material of the dummy gate is polysilicon. The dummy gate is used to reduce the thermal budget of the subsequently formed high dielectric constant gate dielectric layer and metal gate electrode in the gate-last formation process of the high dielectric constant gate dielectric layer and the metal gate (HKMG). After the dummy gate is removed in a subsequent process, a high dielectric constant gate dielectric layer and a metal gate are sequentially formed at the position of the dummy gate.

In this embodiment, a shallow trench isolation structure 201 (STI) located on the surface of the semiconductor substrate 200 and covering part of the sidewall of the fin 202 is also included. The shallow trench isolation structure 201 is used to isolate different fins in the semiconductor substrate 200, the material of the shallow trench isolation structure 201 is silicon oxide, and the formation method of the shallow trench isolation structure can refer to The existing technology will not be repeated here.

Please refer to FIG. 3. FIG. 3 is a schematic cross-sectional structure diagram along the AA1 direction during the process of forming a fin field effect transistor on the basis of FIG. The wall 204 , and the part of the fin 202 covered by the first side wall 204 constitutes a first negative covering area (not shown).

Specifically, a first photoresist layer (not shown) is first formed, the first photoresist layer covers the second region II, and the first photoresist layer is used to protect the The fin portion 202 and the gate structure 203 in the second region II; secondly, a first spacer material layer (not shown) is formed on the fin portion 202 in the first region I by using physical vapor deposition, chemical vapor deposition or atomic layer deposition process As shown in the figure), the first sidewall material layer covers the gate structure 203 in the first region I, and the first sidewall material layer has a relatively high dielectric constant, for example, the first sidewall material layer It is one or more of HfO ₂ , Al ₂ O ₃ , ZrO ₂ , HfSiO, HfSiON, HfTaO and HfZrO; then the first sidewall material layer is etched back by a dry etching process, because the dry etching The etching has better directionality. After etching back the first sidewall material layer, only the first sidewall material layer located on both sides of the gate structure 203 in the first region I remains to form the first sidewall 204, removing the first sidewall material layer located on the top of the gate structure 203 in the first region I and the rest of the region; removing the first photoresist layer.

After the first sidewall 204 is formed, the part of the fin 202 covered by the first sidewall 204 constitutes a first negative covering area. Since lightly doped drain region implantation and halo implantation will not be performed in the first negative cover region in the subsequent process, the doping concentration of the first negative cover region is the same as that of the fin field effect transistor in the first region I formed subsequently. The doping concentration and doping type of the channel region are the same, which can increase the effective channel width of the FinFET in the first region I and alleviate the short channel effect. And because the first spacer 204 has a higher dielectric constant, the capacitance value of the first negative cover region can be increased, so that the driving current of the fin field effect transistor subsequently formed in the first region I will not be affected by the first The lower doping concentration of the negative cover region results in lower driving current.

In this embodiment, the fin field effect transistors formed in the first region I are used as input/output transistors, and the input/output transistors generally need to have a relatively high threshold voltage. The width range of the first negative masking region is 300 Ř500 Å, and the width range of the first negative masking region can be controlled by adjusting the width of the first sidewall 204 . In a FinFET with a negative cover region, different widths of the negative cover region will result in different effective channel widths of the FinFET, different electric field distributions in the channel region, and different threshold voltages of the FinFET. different, and the threshold voltage of the FinFET will increase with the increase of the width of the negative cover region. In this embodiment, the width of the first negative covering region is larger, and the threshold voltage of the formed input/output transistor is also higher.

Referring to FIG. 4 , second sidewalls 205 are formed on both sides of the gate structure 203 in the second region II, and the width of the second sidewalls 205 is smaller than the width of the first sidewalls 204 . Part of the fin portion 202 covered by the side wall 205 constitutes a second negative covering area (not shown).

Specifically, first form a second photoresist layer (not shown), the second photoresist layer covers the first region I, and the second photoresist layer is used to protect the first region in subsequent processes The fin portion 202, gate structure 203 and first sidewall 204 of I; secondly, a second sidewall material is formed on the fin portion 202 of the second region II by using physical vapor deposition, chemical vapor deposition or atomic layer deposition process layer (not shown), the second sidewall material layer covers the gate structure 203 in the second region II, the second sidewall material layer has a relatively high dielectric constant, and the second sidewall material layer The material layer is one or more of HfO ₂ , Al ₂ O ₃ , ZrO ₂ , HfSiO, HfSiON, HfTaO and HfZrO, and the second sidewall material layer can be the same as or different from the material of the first sidewall 204; Etching back the second sidewall material layer by using a dry etching process to form second sidewalls 205 on both sides of the gate structure 203 in the second region II; removing the second photoresist layer.

After the second sidewall 205 is formed, the part of the fin 202 covered by the second sidewall 205 constitutes a second negative covering region, and the doping concentration of the second negative covering region is the same as that of the fins formed in the second region II. The doping concentration of the channel region of the field effect transistor is the same. In this embodiment, the fin field effect transistor formed in the second region II is used as a core logic transistor, and the threshold voltage of the core logic transistor is relatively low, so as to reduce power consumption of the core logic transistor. Please continue to refer to FIG. 4, in the process of forming the core logic transistor located in the second region II, the width of the second sidewall 205 is smaller than the width of the first sidewall 204, and the second sidewall 205 The width and the width of the first side wall 204 refer to the width of the contact surface between the bottom of the second side wall 205 and the first side wall 204 and the fin 202. In this embodiment, the second The width of the negative masking area ranges from 10 angstroms to 50 angstroms. Therefore, the width of the second negative shielding region located under the second sidewall 205 is smaller than the width of the first negative shielding region located under the first sidewall 204, since the threshold voltage of the FinFET increases with the negative shielding The threshold voltage of the core logic transistor is also smaller than that of the input/output transistor.

Please refer to FIG. 5. In this embodiment, the fin field effect transistor formed in the first region I is used as an input/output transistor. In order to further improve the threshold voltage and breakdown voltage of the input/output transistor, the Ion implantation is performed on the first negative covering region where the drain region end of the input/output transistor is to be formed to form an inversion doped region 206 . It should be noted that, for the sake of simplicity and clarity, FIG. 5 only shows a schematic cross-sectional structure diagram of the input/output transistor located in the first region I.

Specifically, a third photoresist layer (not shown) is formed, the third photoresist layer covers the second region II, and the third photoresist layer is used to protect the region during the subsequent ion implantation process. The second region II; then perform ion implantation on the first negative covering region of the drain terminal of the input/output transistor to form an inversion doped region 206 . It should be noted that the implantation direction of the ion implantation process is along the channel direction of the input/output transistor, and has an included angle with the surface of the semiconductor substrate 200, so that only the input/output transistor is treated during the implantation process. Ion implantation is performed on the first negative cover region at the end of the drain region to form an inverse doped region 206, and due to the shielding effect of the gate structure 203, the first negative cover region at the end of the source region of the input/output transistor to be formed will not be affected. region for ion implantation.

The doping type of the inverse doping region 206 is opposite to that of the source region and the drain region of the I/O transistor. In this embodiment, the input/output transistor is an NMOS transistor, the source region and the drain region are N-type doped, and the doping type of the reverse-type doped region 206 is P-type, such as boron ions, phosphorus ions Or gallium ion doping. In this embodiment, BF ₂ is used for ion implantation in the first negative covering region at the drain region end of the input/output transistor, and the width of the inversion doped region 206 ranges from 1 angstrom to 300 angstrom. Since the doping type of the inversion doping region 206 is opposite to the doping type of the source region and the drain region of the input/output transistor, a potential barrier is formed between the inversion doping region 206 and the drain region, further The breakdown voltage and threshold voltage of the input/output transistor are improved.

In another embodiment, the input/output transistor is a PMOS transistor, the source region and the drain region are P-type doped, and the doping type of the reverse-type doped region is N-type, such as phosphorus ions, arsenic ion or antimony ion doping.

Referring to FIG. 6 , ion implantation is performed on the fins 202 on both sides of the gate structure 203 in the first region I and the second region II to form a source region 207 and a drain region 208 .

In this embodiment, the first region I and the second region II are used to form NMOS transistors, and N-type ion implantation is performed on the fins 202 on both sides of the gate structure 203 in the first region I and the second region II For example, phosphorus ions, arsenic ions or antimony ions can be implanted to form the source region 207 and the drain region 208 . It should be noted that, the direction of the ion implantation is perpendicular to the channel direction of the NMOS transistor, and has an included angle with the surface of the semiconductor substrate 200, so that only the gate structure 203 Ion implantation is performed on the fins 202 on both sides, and due to the shielding effect of the gate structure 203, ion implantation will not be performed on the first negative covering region of the first region I and the second negative covering region of the second region II, Affects the doping concentration of the first negative covering region and the second negative covering region.

In another embodiment, the first region I and the second region II are used to form PMOS transistors, and P-type ion implantation is performed on the fins on both sides of the gate structure of the first region I and the second region II For example, boron ions, phosphorus ions or gallium ions can be implanted to form source regions and drain regions.

In another embodiment, before forming the source region and the drain region, pre-amorphization ion implantation (PAI: Pre- Amorphization Implantation), the pre-amorphization ion implantation can convert the single crystal material on the surface of the fin where the source region and the drain region are to be formed into an amorphous material. During the subsequent ion implantation of the source region and the drain region, since the fin surface material is an amorphous material, the crystal lattice arrangement is irregular, and the scattering of implanted ions is enhanced, so that the distribution of implanted ions is more concentrated and the tail is shorter , which is conducive to improving the performance of the formed fin field effect transistor. The particles implanted in the pre-amorphization are Si, C, Ge, Xe or Ar.

Correspondingly, please continue to refer to FIG. 6, the present invention also proposes a fin field effect transistor, including: a semiconductor substrate 200, the surface of the semiconductor substrate 200 has a first region I and a second region II, the first There are raised fins 202 in the first region I and the second region II; a gate structure 203 located on the fins 202, the gate structure 203 covers part of the top and sidewalls of the fins 202; The first sidewalls 204 on both sides of the gate structure 203 in the first region I, and the part of the fins 202 covered by the first sidewalls 204 form a first negative covering area (not shown); The second sidewalls 205 on both sides of the gate structure 203 in region II, the width of the second sidewalls 205 is smaller than the width of the first sidewalls 204, and the width of the first sidewalls 204 and the second sidewalls 205 The material is a high dielectric constant material; the part of the fins 202 covered by the second spacer 205 forms a second negative cover area (not shown); the gate structure 203 located in the first region I and the second region II The source region 207 and the drain region 208 in the fin portion 202 on both sides.

In this embodiment, the first area I is an input/output transistor area, and the second area II is a core logic transistor area. The width of the second negative masking area is smaller than the width of the first negative masking area. In this embodiment, an inversion doped region 206 located in the first negative cover region at the drain region 208 end of the input/output transistor is also included, and the doping type of the inversion doped region 206 is the same as that of the input The source region 207 and the drain region 208 of the output transistor have opposite doping types, and the width of the inverse doping region 206 ranges from 1 angstrom to 300 angstroms.

The fin field effect transistor of this embodiment is formed using the above-mentioned fin field effect transistor forming method, therefore, the fin field effect transistor located in the first region I and the fin field effect transistor located in the second region II have different threshold voltage.

In summary, compared with the prior art, the present invention has the following advantages:

In the method for forming a fin field effect transistor according to an embodiment of the present invention, first sidewalls are formed on both sides of the gate structure in the first region, and second sidewalls are formed on both sides of the gate structure in the second region. The widths of the first side wall and the second side wall are different, and the widths of the first negative covering area under the first side wall and the second negative covering area under the second side wall are different. In a FinFET with a negative cover region, different widths of the negative cover region lead to different effective channel widths of the subsequently formed FinFET, which changes the electric field distribution in the channel region and affects the FinFET. threshold voltage. The embodiment of the present invention utilizes the influence of the width of the negative covering region on the threshold voltage of the FinFET, and controls the width of the sidewalls formed in the first region and the second region during the formation of the FinFET. The widths of the first negative cover region and the second negative cover region are controlled to obtain fin field effect transistors with different threshold voltages, and the process is simple and the cost is low.

Further, in the method for forming a fin field effect transistor according to the embodiment of the present invention, the first region is used to form an input/output transistor. Since the input/output transistor usually requires a relatively high threshold voltage and breakdown voltage, therefore, Ion implantation is performed on the first negative covering region at the drain region end of the input/output transistor to form an inversion doped region. The doping type of the inversion doping region is opposite to the doping type of the source region and the drain region of the input/output transistor, and a potential barrier is formed between the inversion doping region and the drain region, further improving the breakdown and threshold voltages of the input/output transistors described above.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention, and any person skilled in the art can utilize the methods and techniques disclosed above to analyze the technical aspects of the present invention without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not depart from the content of the technical solution of the present invention, all belong to the protection of the technical solution of the present invention. scope.

Claims (19)

1. A kind of 1. forming method of fin formula field effect transistor, it is characterised in that including：

   Semiconductor substrate is provided, the Semiconductor substrate has first area and second area, the first area and the secondth area There is raised fin, the grid structure on the fin, the top of fin described in the grid structure covering part in domain Portion and side wall；

   Form the first side wall in the grid structure both sides of the first area, the part fin of first side wall covering forms the One negative covering area；

   The second side wall is formed in the grid structure both sides of the second area, the width of second side wall is less than first side The width of wall, the part fin of the second side wall covering form the second negative covering area；

   Ion implanting is carried out to the fin of the first area and the grid structure both sides of second area, forms source region and drain region；

   Wherein, the fin formula field effect transistor that the first area is formed as input/output transistors, first side wall Material is high dielectric constant material, the doping concentration of the channel region in the described first negative fin for covering area and first area and is mixed Miscellany type is identical.
2. 2. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that the second negative covering area Width be less than described first it is negative cover area width.
3. 3. the forming method of fin formula field effect transistor as claimed in claim 2, it is characterised in that the first negative covering area Width range be 300 angstroms~500 angstroms.
4. 4. the forming method of fin formula field effect transistor as claimed in claim 2, it is characterised in that the second negative covering area Width range be 10 angstroms~50 angstroms.
5. 5. the forming method of fin formula field effect transistor as claimed in claim 4, it is characterised in that the first negative covering area Doping concentration it is identical with the doping concentration of the input/output transistors channel region.
6. 6. the forming method of fin formula field effect transistor as claimed in claim 4, it is characterised in that also include to described defeated Enter/the first negative area that covers at the drain region end of output transistor carries out ion implanting, form transoid doped region.
7. 7. the forming method of fin formula field effect transistor as claimed in claim 6, it is characterised in that the transoid doped region Doping type is opposite with the source region and drain region doping type of the input/output transistors.
8. 8. the forming method of fin formula field effect transistor as claimed in claim 7, it is characterised in that the transoid doped region Width range is 1 angstrom~300 angstroms.
9. 9. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that the second area is formed Fin formula field effect transistor as core logic transistor.
10. 10. the forming method of fin formula field effect transistor as claimed in claim 9, it is characterised in that the second negative covering The doping concentration in area is identical with the doping concentration of the core logic transistor channel region.
11. 11. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that second side wall Material is high dielectric constant material.
12. 12. the forming method of the fin formula field effect transistor as described in claim 1 or 11, it is characterised in that the high dielectric Constant material is HfO₂、Al₂O₃、ZrO₂, one or more in HfSiO, HfSiON, HfTaO and HfZrO.
13. 13. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that also include to described the The fin of one region and the grid structure both sides of second area carries out pre-amorphous ion implanting.
14. 14. the forming method of fin formula field effect transistor as claimed in claim 13, it is characterised in that it is described it is pre-amorphous from The injection ion of son injection is Si, C, Ge, Xe or Ar.
15. A kind of 15. fin formula field effect transistor, it is characterised in that including：

    Semiconductor substrate, the Semiconductor substrate have a first area and second area, in the first area and second area Fin with projection；

    Grid structure on the fin, the top of fin and side wall described in the grid structure covering part；

    The first side wall positioned at the grid structure both sides of the first area, the part fin of first side wall covering form the One negative covering area；

    The second side wall positioned at the grid structure both sides of the second area, the width of second side wall are less than first side The width of wall, the part fin of the second side wall covering form the second negative covering area；

    Source region and drain region in the fin of the first area and the grid structure both sides of second area；

    Wherein, the fin formula field effect transistor that the first area is formed as input/output transistors, first side wall Material is high dielectric constant material, the doping concentration of the channel region in the described first negative fin for covering area and first area and is mixed Miscellany type is identical.
16. 16. fin formula field effect transistor as claimed in claim 15, it is characterised in that the width in the second negative covering area is small In the described first negative width for covering area.
17. 17. fin formula field effect transistor as claimed in claim 15, it is characterised in that the first area is input/output Transistor area, the second area are core logic transistor region.
18. 18. fin formula field effect transistor as claimed in claim 17, it is characterised in that also include being located at the input/output The drain region end of transistor first it is negative cover area in transoid doped region, the doping type of the transoid doped region with it is described defeated Enter/source region of output transistor and drain region doping type be on the contrary, the width range of the transoid doped region is 1 angstrom~300 angstroms.
19. 19. fin formula field effect transistor as claimed in claim 15, it is characterised in that the material of second side wall is Gao Jie Permittivity material.