CN103944568A - Sampling clock generation circuit for multichannel time interleaving analog-digital converter - Google Patents
Sampling clock generation circuit for multichannel time interleaving analog-digital converter Download PDFInfo
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Abstract
本发明涉及一种用于多通道时间交织模数转换器的采样时钟产生电路，由多相位时钟产生模块、占空比恢复电路和通道选择模块构成，其中多相位时钟产生模块产生多通道数模转换器所需的多相位时钟信号，同时对多相位时钟信号的相位误差进行补偿，保证模数转换器通道间的采样时钟的准确性；占空比恢复电路将多相位时钟产生模块产生的多相位时钟进行边沿调整操作，即进行占空比恢复，输出的多相位时钟信号作为采样保持电路的采样时钟信号；通道选择模块接收外部串口写入的控制码，判断需要的内部通道数，并控制内部通道的开启和关断，同时根据控制码来选择多相位脉冲模块内部多相位时钟，以实现不同通道选择下采样时钟地生成。
The invention relates to a sampling clock generation circuit for a multi-channel time-interleaved analog-to-digital converter, which is composed of a multi-phase clock generation module, a duty ratio recovery circuit and a channel selection module, wherein the multi-phase clock generation module generates a multi-channel digital-analog The multi-phase clock signal required by the converter, and at the same time compensate the phase error of the multi-phase clock signal to ensure the accuracy of the sampling clock between the channels of the analog-to-digital converter; The phase clock performs an edge adjustment operation, that is, restores the duty ratio, and the output multi-phase clock signal is used as the sampling clock signal of the sample and hold circuit; the channel selection module receives the control code written by the external serial port, judges the number of internal channels required, and controls The internal channel is turned on and off, and at the same time, the internal multi-phase clock of the multi-phase pulse module is selected according to the control code, so as to realize the generation of down-sampling clocks selected by different channels.
Description
Technical field
The present invention relates to a kind of sampling clock for the time-interleaved analog to digital converter of multichannel and produce circuit, belong to integrated circuit mixed-signal designs field, be mainly used in the error that reduces sampling clock in the time-interleaved transducer of multichannel, improve the performance of transducer.
Background technology
Black in 1980 and Hodges propose the time-interleaved ADC technology of multichannel for the first time, this technology is by the sub-ADC concurrent working of multiple low sampling rates, interweave thereby same input signal sampling is improved to sampling rate by sampling clock, this technology has reduced the requirement of each sub-ADC in the situation that realizing identical sample rate, and it is more and more applied in high-speed, high precision transducer.
Although the time-interleaved analog to digital converter of multichannel can improve sample rate, but accordingly also can be because interchannel mismatch produces error, interchannel error mainly comprises three kinds: sampling clock error, gain error and mismatch error, other document has also increased interchannel bandwidth error, but wherein first three is planted as main source of error.Along with the appearance of the time-interleaved technology of multichannel, collimation technique to these three kinds of errors is also constantly suggested, it is mainly divided into foreground collimation technique and background calibration technology two classes, foreground calibration needs reference-input signal, result after changing by analog to digital converter is compared with reference result, obtain needing the result of compensation, fed back to again in actual input, the advantage of the method is that calibration structure is fairly simple, but shortcoming is to interrupt the normal work of transducer, and can not realize real time calibration.Background calibration can be calibrated in real time, and can in the time that transducer is worked, carry out, but it is often more difficult from unknown input, to extract error, and the general main mode by statistics obtains error and then compensates.Due to the continuity in order to ensure system applies and agility, it is more extensive that background calibration technology is applied.
In general, mismatch error is a kind of DC error, can be regarded as systematic error, with maximum be the method based on random copped wave (chopping), remove signal DC component by after input signal is modulated, obtain offset error by cumulative statistics, again it is compensated to elimination error, finally output is carried out recovering its DC component after demodulation, the method can well be eliminated the impact of mismatch error, but it should be noted that and introduce the impact on speed and precision after chopping switch.For eliminating gain error, it mainly also has foreground collimation technique and background calibration technology, but background calibration method is increasing on the basis of hardware costs, it tends to more adopt the mode of foreground calibration to eliminate this error to the improvement of performance not obvious.
Along with the fast development of high-speed, high precision transducer, utilize the time-interleaved technology of multichannel to realize the sample rate of GSPS more and more general, therefore harsher to the requirement of interchannel sampling clock error, often become the bottleneck of ultrahigh speed converter design.Same, also be divided into foreground calibration and background calibration for the calibration of sampling clock error, foreground calibration needs reference-input signal, this reference signal can be ramp signal, triangular signal or sinusoidal signal, but this situation in frequency applications has increased the cost of hardware greatly, and the method itself just has great defect, can not calibrate according to environmental change.Background calibration method mainly contains following four kinds of modes: mismatch compensation and delay-locked loop (DLL) technology of the sampling hold circuit of the overall situation, overall sampling clock, clock.The sampling hold circuit of the overall situation has fundamentally been eliminated the sampling clock error between the time-interleaved converter channel of multichannel, need the sampling hold circuit of high-speed, high precision, but the basic thought of it and time-interleaved technology is runed counter to, it is not the performance that simply improves transducer by increasing the mode of power consumption, increase greatly the difficulty of design, in actual design, do not adopted in this way; Overall situation sampling clock technology is sampled after by global clock signal and channel sample clock signal synchronization, but in sampling process, introduce overall sampling switch like this and affected precision, the clock feedthrough of sampling switch and channel charge inject and have brought new error; Clock mismatch compensation technology adopts complicated filter bank structure to reduce interchannel sampling clock error, and except improving hardware costs, the nonlinearity erron of system self has no idea to eliminate; Delay-locked loop (DLL) technology is the structure that interchannel sampling clock error is eliminated in a kind of current application more widely, but obtain higher precision and need more controllable time delay line unit, this has just limited speed, so will carry out as requested compromise between speed and precision.
Fig. 1 has introduced the principle of overall sampling clock technology, as the clock CLKi(i=1 of each passage, 2 ... M) and when overall sampling clock CLK is high simultaneously, input signal is sampled, and the single channel sampling clock sampling time is the half in overall sampling clock cycle, and every channel clock CLKi is ability step-down after overall sampling clock CLK is low level always, because the sampling time is determined by the trailing edge of overall sampling clock CLK, eliminate the phase error of interchannel sampling clock CLKi.Also can produce new error owing to introducing overall sampling switch: overall sampling switch is introduced parasitic capacitance, in the time that single channel clock CLKi disconnects, the electric charge of parasitic capacitance can be lost, impact keeps the precision of setting up of phase place, and this mismatch will cause that imbalance is spuious in multipath A/D converter output, and then reduction signal to noise ratio, and overall sampling switch also can affect the imbalance of single channel analog to digital converter, gain and nonlinearity erron, the decline that brings analog to digital converter dynamic property because clock feedthrough and channel charge inject while disconnecting.
Fig. 2 has provided a kind of implementation of clock mismatch compensation technology, and the structure of described implementation comprises input resolution filter 201, sub-ADC202, interpolation filter 203, digital filter 204 and reconfiguration unit 205.Input signal enters resolution filter 201 and is decomposed in different frequency bands, and resolution filter 201 can be both that continuous time filter can be also discrete time filter, in the higher situation of operating frequency, needs to adopt simulated time filter.Then the signal after decomposing enters each sub-ADC202 and changes, the digital signal obtaining enters interpolation filter 203 and carries out digital interpolative computing, its result enters digital filter 204 and carries out filtering, finally enter reconfiguration unit 205 output signal is reconstructed, thereby adopt input resolution filter 201 and digital filter 204 to average and to realize compensation sampling clock error.But owing to introducing analog filter, increase hardware costs and power consumption, and design difficulty is further strengthened.
Fig. 3 has provided the method for eliminating multi-channel sampling clocking error based on delay-locked loop.With clock mismatch compensation technology difference be, the method is by transducer Output rusults is carried out to error extraction and compensation, but sampling clock error between multichannel is calibrated.Described delay-locked loop comprises phase discriminator 301, charge pump 302, low pass filter 303, controllable time delay line 304 and clock distributing network 305.Phase discriminator 301 receives the feedback clock signal of input clock signal and clock distributing network 305, carry out phase place compare operation, and the result of described compare operation is input to charge pump 302, the time of being opened and being turn-offed by control charge pump 302 is adjusted the output voltage of low pass filter 303, output voltage after described adjustment is input in controllable time delay line 305, adjusts the phase place of output clock by closed-loop control.The quantity that delay-locked loop can arrange controllable time delay line 304 internal delay time unit obtains equiphase clock signal of the poor precision of out of phase, but delay-locked loop is in order to realize locking, requiring input clock signal and differing of feedback clock signal is zero, that is to say, feedback clock signal is to obtain an input clock signal delay integer clock cycle, this has just increased difficulty to the design of whole loop, in order to ensure high phase alignment precision, the quantity of delay unit can be a lot, be difficult to ensure that it is at high-frequency work if adopt digital method to realize, if adopt analogy method to realize, need to ensure that delay unit has good noise inhibiting ability, any power supply in the time that transducer is worked, the noise of substrate coupling all can affect the precision of its phase alignment, and in clock distributing network 305, the mismatch in the Clock Distribution path of each multi-channel sampling clock will further increase the error of multi-channel sampling clock.
In the time-interleaved A/D converter with high speed and high precision of multichannel, interchannel gain error, offset error and sampling clock error can affect the Static and dynamic performance of transducer, reduce conversion accuracy, need to calibrate for error to it, and interchannel sampling clock error has become the bottleneck of Ultrahigh speed data converter design, the method of transducer output data being added up to extraction interchannel sampling clock error and compensation is difficult to obtain good effect, therefore, how to obtain better multi-channel sampling clock and just become a kind of trend of current circuit design.
Summary of the invention
The object of the invention is to overcome the above-mentioned deficiency of prior art, provide a kind of sampling clock for the time-interleaved analog to digital converter of multichannel to produce circuit, this sampling clock produces circuit can produce the required multichannel equiphase sampling clock of multipath A/D converter, in addition interchannel clocking error is carried out to calibration design, can ensure can obtain equiphase multi-channel sampling clock signal under high-frequency clock, improve the sampling precision of sampling hold circuit in analog to digital converter.
Above-mentioned purpose of the present invention is mainly achieved by following technical solution:
A kind of sampling clock for the time-interleaved analog to digital converter of multichannel produces circuit, comprise multiphase clock generation module, duty ratio recovery circuit and channel selecting module, described multiphase clock generation module comprises two phase clock module and leggy pulse module, wherein:
Two phase clock module: the global clock signal of outside input is carried out after anti-phase obtaining anti-phase global clock signal, described global clock signal and anti-phase global clock signal are carried out to phase difference calibration, and global clock signal and anti-phase global clock signal after calibration are exported to leggy pulse module;
Leggy pulse module: receive path is selected global clock signal and the anti-phase global clock signal after the control signal 2 of module output and the calibration of two phase clock module output, global clock signal after described calibration and inversion clock signal are carried out respectively to two points of computings of phase place by inner several multiphase clock generation units, and respectively two results of two points of computings of phase place are carried out to phase difference calibration, obtain the poor pulse signal of a series of equiphases, by described output of pulse signal to duty ratio recovery circuit;
Duty ratio recovery circuit: the pulse signal receiving from leggy pulse module is carried out to duty ratio recovery, and export sampled clock signal to outside multipath A/D converter;
Channel selecting module: receive the control signal 1 that outside serial ports writes, the inner passage number needing according to described control signal judgement, and control unlatching and the shutoff of inner passage, select the quantity of the inner multiphase clock generation unit of leggy pulse module simultaneously according to described control signal 1, and selection result is exported to leggy pulse module as control signal 2.
Produce circuit at the above-mentioned sampling clock for the time-interleaved analog to digital converter of multichannel, two phase clock module comprises monolateral along phase discriminator, the first filter, differential amplifier and controllable time delay line, the wherein monolateral anti-phase global clock signal that receives the outside global clock signal of inputting and the output of controllable time delay line along phase discriminator, carry out phase demodulation operation, obtain two groups of square-wave signals, export to the first filter, the first filter receives described two groups of square-wave signals, extracts DC component, and two groups of DC component are exported to differential amplifier, differential amplifier is asked difference operation to two groups of DC component signals, to ask difference operation result to be input to controllable time delay line as control signal 3, controllable time delay line receives the global clock signal of outside input and the control signal 3 of amplifier output, the phase place of adjusting global clock signal obtains reverse global clock signal, in the time of 180 ° of the phase place of reverse global clock and the phase phasic differences of global clock signal, complete phase alignment, global clock signal after calibration and reverse global clock signal are exported to leggy pulse module, reverse global clock signal after calibration is exported to monolateral along phase discriminator simultaneously.
Produce circuit at the above-mentioned sampling clock for the time-interleaved analog to digital converter of multichannel, leggy pulse module is made up of the multistage multiphase clock generation unit with same structure, every grade of multiphase clock generation unit comprises pulse-generating circuit and several phase alignment circuit, wherein: pulse-generating circuit receive path is selected global clock signal and the anti-phase global clock signal after the control signal 2 of module output and the calibration of two phase clock module output, select the quantity of inner multiphase clock generation unit according to described control signal 2, global clock signal and anti-phase global clock signal are carried out obtaining pulse signal after phase bit arithmetic, by described output of pulse signal to phase alignment circuit, described pulse signal is carried out respectively two points of computings of phase place by several phase alignment circuit, and respectively two results of two points of computings of phase place are carried out to phase difference calibration, obtain the poor pulse signal of a series of equiphases, by described output of pulse signal to duty ratio recovery circuit.
Produce circuit at the above-mentioned sampling clock for the time-interleaved analog to digital converter of multichannel, each phase alignment circuit comprises bilateral along phase discriminator, charge pump, the second filter and delay line, the wherein bilateral pulse signal along the output of phase detector received pulse generation circuit and the pulse signal of delay line output, and two pulse signals are carried out to phase demodulation operation, obtain two groups of square-wave signals, export to charge pump; Charge pump receives described two groups of square-wave signals, adjusts the output voltage of charge pump by square-wave signal, and the voltage signal of output after adjusting is to the second filter; The second filter carries out filtering to the voltage signal after adjusting, and extracts DC component and is input to delay line as control signal 4; Delay line received pulse produces the pulse signal of circuit output and the control signal 4 of the second filter output, described pulse signal is carried out to two points of computings of phase place and obtain two pulse signals, when the phase difference of described two pulse signals is that the pulse signal rising edge of input is to the half of trailing edge time difference, complete phase alignment, and the pulse signal after calibration is exported to the bilateral pulse-generating circuit along phase discriminator and next stage multiphase clock generation unit simultaneously.
Produce circuit at the above-mentioned sampling clock for the time-interleaved analog to digital converter of multichannel, duty ratio recovery circuit comprises edge Circuit tuning, buffer circuit, the 3rd filter and differential amplifier, wherein edge Circuit tuning receives the control signal 5 of differential amplifier output and the pulse signal of leggy pulse module output, described pulse signal rising edge and trailing edge are gone out to the time difference of now to be adjusted, and the pulse signal after adjusting is exported to buffer circuit and the 3rd filter simultaneously, the 3rd filter pulse signals is carried out integral operation, extract the common-mode voltage of pulse signal, the common-mode voltage of pulse signal is exported to differential amplifier, described common-mode voltage and target voltage are asked difference operation by difference differential amplifier, will ask difference operation result to export to edge Circuit tuning as control signal 5, after pulse signal after buffer circuit reception is adjusted cushions, obtain clock signal and export to outside multipath A/D converter, in the time that the time difference that pulse signal rising edge in edge Circuit tuning goes out now time difference to trailing edge and described trailing edge go out now to next rising edge equates, edge Circuit tuning completes adjustment process, the duty ratio of pulse signal is constant 50%, is finally cushioned rear output and had the clock signal of 50% constant duty ratio by buffer circuit.
Produce circuit at the above-mentioned sampling clock for the time-interleaved analog to digital converter of multichannel, in the time that integral operation result equates with target voltage, edge adjustment no longer changes, and finally exports the clock signal with 50% constant duty ratio by buffer circuit.
The present invention's beneficial effect is compared with prior art:
(1), a kind of sampling clock for the time-interleaved analog to digital converter of multichannel that proposes of the present invention produces circuit, do not rely on input reference signal, can realize the elimination to sampling clock error between multichannel, can not affect the normal work of analog to digital converter;
(2) a kind of sampling clock for the time-interleaved analog to digital converter of multichannel that, the present invention proposes produces circuit, being different from the first Technology Need in background technology introduces overall sampling clock switch and has affected the precision calibrating for error, the present invention adopts the mode of phase place dichotomy to produce step by step the poor clock signal of equiphase, and the poor clock signal of adjacent phase is calibrated, can eliminate sampling clock error completely;
(3) a kind of sampling clock for the time-interleaved analog to digital converter of multichannel that, the present invention proposes produces circuit, the second technology in background technology that is different from utilizes the output of transducer to extract sampling clock error, do not need complicated bank of filters, can accurately extract interchannel sampling clock error simultaneously, in the time that generating, eliminates sampling clock interchannel error, the cost that has reduced hardware, has reduced cost, has improved the precision of calibration simultaneously;
(4) a kind of sampling clock for the time-interleaved analog to digital converter of multichannel that, the present invention proposes produces circuit, the third technology in background technology that is different from adopts delay-locked loop to generate the poor sampled clock signal of the equiphase method of error between calibrated channel simultaneously, do not need to carry out cycle alignment by input clock with through the feedback clock of clock distributing network, so just there is not trading off in speed and precision, can meet the harsh requirement to interchannel sampling clock error in high-speed applications;
(5), sampling clock of the present invention produce circuit in the case of not changing the operating state of high-speed AD converter, the error of multi-channel sampling clock is calibrated; This circuit can carry out structure expansion, can make the mode of operation of analog to digital converter more flexible, can realize the switching that different channel selecting down-sampling clocks generate, the mode of employing dichotomy produces successively has equiphase clock signal, do not need complicated filter construction to realize the calibration of interchannel phase place, make analog to digital converter can take into account the precision that sampling clock calibrates for error the in the situation that of high speed operation simultaneously.
Brief description of the drawings
Fig. 1 is the schematic diagram of overall sampling clock technology;
Fig. 2 is the schematic diagram of clock mismatch compensation technology;
Fig. 3 is the schematic diagram of delay locked loop technique;
Fig. 4 is the structural representation that sampling clock of the present invention produces circuit;
Fig. 5 is the structure chart of two phase clock module of the present invention;
Fig. 6 is a kind of circuit theory diagrams of two phase clock module of the present invention;
Fig. 7 is the structural representation of leggy pulse module of the present invention;
Fig. 8 is the structural representation of multiphase clock generation unit in leggy pulse module of the present invention;
Fig. 9 is the bilateral circuit theory diagrams along phase discriminator in leggy pulse module of the present invention;
Figure 10 is the structural representation of duty ratio recovery circuit of the present invention;
Figure 11 is the circuit theory diagrams of duty ratio recovery circuit of the present invention;
Figure 12 is the sequential chart of duty ratio recovery circuit work of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail:
Be illustrated in figure 4 the structural representation that sampling clock of the present invention produces circuit, sampling clock generation circuit of the present invention is made up of multiphase clock generation module 400, duty ratio recovery circuit 410, channel selecting module 420 as seen from the figure.Wherein multiphase clock generation module 400 produces the required multi-phase clock signal of multichannel digital to analog converter, the phase error of multi-phase clock signal is compensated simultaneously, ensures the accuracy of the interchannel sampling clock of digital to analog converter.The multiphase clock that duty ratio recovery circuit 410 is used for multiphase clock generation module to produce carries out edge simultaneous operation with input global clock signal, the pulse signal that is about to receive from leggy pulse module carries out duty ratio recovery, and the multi-phase clock signal of its output is as the sampled clock signal of outside multipath A/D converter sampling hold circuit.Channel selecting module 420 receives the control code (control signal 1) that outside serial ports (SPI) writes, the inner passage number needing according to described control signal judgement, and control unlatching and the shutoff of inner passage, select the inner multiphase clock of leggy pulse module according to described control signal 1 simultaneously, generate to realize different channel selecting down-sampling clocks.
Multiphase clock generation module 400 is made up of two phase clock module 401 and leggy pulse module 402.Wherein two phase clock module 401 carries out the global clock signal of outside input after anti-phase to obtain anti-phase global clock signal, global clock signal and anti-phase global clock signal are carried out to phase difference calibration, and global clock signal and anti-phase global clock signal after calibration are exported to leggy pulse module.Leggy pulse module 402 receive paths are selected global clock signal and the anti-phase global clock signal after the control signal 2 of module output and the calibration of two phase clock module output, global clock signal after calibration and inversion clock signal are carried out respectively to two points of computings of phase place step by step by inner several multiphase clock generation units, and respectively two results of two points of computings of phase place are carried out to phase difference calibration, obtain the poor pulse signal of a series of equiphases, by output of pulse signal to duty ratio recovery circuit, in the situation that not introducing labyrinth, ensure between leggy pulse signal, to there is equal phase difference.
Be illustrated in figure 5 the structure chart of two phase clock module of the present invention, two phase clock module 401 comprises monolateral along phase discriminator 501, the first filter 502, differential amplifier 503 and controllable time delay line 504 as seen from the figure, the wherein monolateral anti-phase global clock signal that receives the outside global clock signal of inputting and the output of controllable time delay line along phase discriminator 501, carry out phase demodulation operation, obtain two groups of square-wave signals, export to the first filter 502.Be specially: the phase bit comparison of the monolateral rising edge of mainly realizing input signal along phase discriminator 501, the time of the rising edge to input signal compares, output obtains one group of square-wave signal, the width of the high level of one of them square-wave signal 505 is carved into the time width in moment that the rising edge of clock signal occurs while having reacted that the rising edge of input clock signal occurs, the width of the high level of another square-wave signal 506 is carved into the time width in moment that the next cycle rising edge of input clock signal occurs while having reacted that the rising edge of clock signal occurs.This group square-wave signal is input in the first filter 502.
The first filter 502 receives two groups of square-wave signals, extracts DC component, and two groups of DC component are exported to differential amplifier 503.Differential amplifier 503 is asked difference operation to two groups of DC component signals, will ask difference operation result to be input to controllable time delay line 504 as control signal 3.Controllable time delay line 504 receives the global clock signal of outside input and the control signal 3 of amplifier output, the phase place of adjusting global clock signal obtains reverse global clock signal, in the time of 180 ° of the phase place of reverse global clock and the phase phasic differences of global clock signal, complete phase alignment, global clock signal after calibration and reverse global clock signal are exported to leggy pulse module 402, the reverse global clock signal after calibration is exported to monolateral along phase discriminator 501 simultaneously.
Because clock signal is the time delay version (phase place with time delay from be consistent in essence) of input clock signal, can be described by relation below: the cycle of input clock signal is T, the moment that first rising edge occurs is t0, the moment that first rising edge of output clock occurs is t1, note t1=t0+ Δ t1(Δ t1>0), the high level width Delta t1 of first square-wave signal, the moment that second rising edge of input clock signal occurs is t0+T, note t0+T=t1+ Δ t2, the high level width Delta t2 of second square-wave signal, in the time of Δ t1=Δ t2, complete time delay adjustment process, there is t1=t0+T/2, the rising edge of establishing input clock from phase place analysis is 0 ° of phase place, next rising edge is 360 ° of phase places, the rising edge of output clock is 180 ° of phase places, also can say the clock signal that has obtained respectively homophase (0 ° of phase place) and anti-phase (180 ° of phase places) through two phase clock module.When make above-mentioned equation be false due to noise effect, circuit will be calibrated until error concealment this error.
Be illustrated in figure 6 a kind of circuit theory diagrams of two phase clock module of the present invention, as seen from the figure, monolaterally formed by 6 metal-oxide-semiconductors along phase discriminator 600, wherein M1, M2 are for input is to pipe, M3～M6 forms a cross coupling inverter, it is a positive feedback structure, can complete fast input signal phase demodulation.The first filter 610 carries out integration to identified result and extracts DC component, set it as the input of difference differential amplifier 620, difference differential amplifier 620 compares these two DC quantity, residual quantity is outputed in controllable time delay line 640, it is made up of a Current Control inverter, can control charging current and discharging current, thereby the time that the edge of realizing control inputs clock signal occurs, the phase place of clock signal is modulated, it is final in the time that the phase place of input and output clock signal is being related to of homophase (0 ° of phase place) and anti-phase (180 ° of phase places), the DC quantity that filter 610 is exported is identical, the residual quantity of difference differential amplifier 630 is output as 0, the charging and discharging currents of controllable time delay line 640 equates, in the time that phase difference relation changes, this module can be calibrated phase error, until phase difference is got back to dynamic balance state.In the time that phase difference is greater than 180 °, there is residual quantity in differential amplifier, controlled signal is adjusted the electric current of controllable time delay line 630, and charging current is greater than discharging current, the moment that trailing edge of clock signal occurs postpones backward, and the moment that rising edge occurs can in advance, finally dwindle phase difference until equal 180 ° to realize dynamic equilibrium; Otherwise, in the time that phase difference is less than 180 °, there is residual quantity in differential amplifier, controlled signal is adjusted the electric current of controllable time delay line 630, and charging current is less than discharging current, the moment that trailing edge of clock signal occurs can be leading, and the moment that rising edge occurs can postpone backward, finally dwindles phase difference until equal 180 ° and realizes dynamic equilibrium.
Be illustrated in figure 7 the structural representation of leggy pulse module of the present invention, leggy pulse module 402 is made up of the multistage multiphase clock generation unit with same structure as seen from the figure, be used for producing multichannel and adopt the required pulse signal of sampling clock of protecting circuit, along with increasing progressively of progression, the pulse number of generation is exponential and increases progressively.If a total M level, the output of M level produces 2
(M)the individual pulse signal with equiphase poor (for rising edge), as the first order in Fig. 7 700, the second level 710 ...Every grade of multiphase clock generation unit comprises pulse-generating circuit and several phase alignment circuit, wherein: pulse-generating circuit receive path is selected global clock signal and the anti-phase global clock signal after the control signal 2 of module output and the calibration of two phase clock module output, select the quantity of inner multiphase clock generation unit according to control signal 2, global clock signal and anti-phase global clock signal are carried out obtaining pulse signal after phase bit arithmetic, by this output of pulse signal to phase alignment circuit; This pulse signal is carried out respectively two points of computings of phase place by several phase alignment circuit, and respectively two results of two points of computings of phase place are carried out to phase difference calibration, obtain the poor pulse signal of a series of equiphases, and by output of pulse signal poor equiphase to duty ratio recovery circuit.
If required progression M=2, except the work of two phase clock module, in leggy pulse module, there is the work of one-level (two groups) multiphase clock generation unit, pulse-generating circuit 701 receives homophase and inversion clock signal, produce two pulse signals, respectively pulse signal P1 and pulse signal P2, P1 high level width be in-phase clock rising edge occur time be carved into inversion clock rising edge and go out the time width of now, P2 high level width is that inversion clock rising edge goes out go out now now time width to in-phase clock rising edge, then enter into calibration delay unit 702, when being carried out to delay process, the pulse signal of input obtains two pulse signals, it is respectively the pulse signal of former pulse signal and time delay version, the time that its rising edge occurs is the half of former pulse signal rising edge to the time width of trailing edge, phase place, the phase place of former pulse signal is 0 °, the phase place of trailing edge is 180 °, the time that the rising edge of the pulse signal of time delay version occurs is 90 ° phase place, in like manner, input inversion clock signal is exported the pulse signal of former pulse signal and time delay version, the phase place of former pulse signal is 180 °, the phase place of trailing edge is 180 °, time delay version pulse signal is 270 °, export altogether 4 pulse signals that equiphase is poor by first order leggy generation unit, phase place is respectively 0 °, 90 °, 180 ° and 270 °.
If required progression M=3, except the work of two phase clock module, in leggy pulse module, there is the work of two-stage (six groups) multiphase clock generation unit, 4 poor pulse signals of equiphase that first order multiphase clock generation unit obtains are input in second level leggy generation unit 710, be input to after the multiphase clock generation unit of the second level, produce respectively four group pulse signals, respectively (P1, P3), (P3, P2), (P2, and (P4 P4), P1), it is (0 ° that corresponding phase is closed, 90 °), (90 °, 180 °), (180 °, 270 °) and (270 °, 360 °), four group pulse high level width are the poor width of rising edge time of occurrence of input pulse signal.These pulses obtain the pulse signal of former pulse signal and time delay behind correcting time delay unit 712, phase place, four pulse signals of input are respectively 0 °, 90 °, 180 ° and 270 °, the phase place of exporting the pulse signal of time delay is respectively 45 °, 135 °, 225 ° and 315 °, obtains altogether 8 pulse signals that equiphase is poor.By controlling the operating state of more multistage leggy generation unit, can obtain the poor pulse signal of more equiphases.
Be illustrated in figure 8 the structural representation of multiphase clock generation unit in leggy pulse module of the present invention, multiphase clock generation unit is made up of pulse-generating circuit 800 and phase alignment circuit 810.Pulse-generating circuit 800 is made up of a simple synchronizer 801 and inverter, input signal CLK1 and CLK2 are input pulse signal, the rising edge of CLK2 lags behind CLK1, by obtaining required pulse signal after synchronizer 801 and inverter, its high level width is the time difference of the rising edge of input pulse signal.
Phase alignment circuit 810 is realized by a delay-locked loop, comprise bilateral along phase discriminator 811, charge pump 812, the second filter 813, delay line 814, the wherein bilateral pulse signal along phase detector 811 received pulses generation circuit outputs and the pulse signal of delay line output, and two pulse signals are carried out to phase demodulation operation, obtain two groups of square-wave signals, export to charge pump.Bilateral along phase discriminator 811 can pulse signals rising edge and the phase place of trailing edge differentiate simultaneously, it can adopt the circuit shown in Fig. 9 to realize (Fig. 9 is the bilateral circuit theory diagrams along phase discriminator in leggy pulse module of the present invention); The implementation of itself and above-mentioned pulse-generating circuit is similar, input signal CLK1 and CLK2 are input pulse signal, the rising edge of CLK2 lags behind CLK1, and the width of output pulse P1 and P2 high level has reacted respectively the time difference of CLK1 rising edge to time difference of CLK2 rising edge and CLK2 rising edge to CLK1 trailing edge.It should be noted that the coupling except ensureing synchronizer unit 901 and 911, also will make inverter 902 and transmission gate 913 will keep strict conformance on gate delay.
Charge pump 812 receives two groups of square-wave signals, adjusts the output voltage of charge pump 812 by square-wave signal, and the voltage signal of output after adjusting is to the second filter 813; The second filter 813 carries out filtering to the voltage signal after adjusting, and extracts DC component and is input to delay line 814 as control signal 4; Delay line 814 received pulses produce the pulse signal of circuit output and the control signal 4 of the second filter output, described pulse signal is carried out to two points of computings of phase place and obtain two pulse signals, when the phase difference (being the time difference that rising edge occurs) of described two pulse signals is that the pulse signal rising edge of input is to the half of trailing edge time difference, complete phase alignment, and the pulse signal after calibration is exported to the bilateral pulse-generating circuit along phase discriminator 811 and next stage multiphase clock generation unit simultaneously.
The poor pulse signal of multiple equiphases producing is because width is smaller, directly can be owing to switching and having reduced sampling precision fast as sampled clock signal, the present invention adopts duty ratio recovery circuit pulse signal to be reverted to the clock signal with 50% duty ratio, its structure is (structural representation that Figure 10 is duty ratio recovery circuit of the present invention) as shown in figure 10, duty ratio recovery circuit 1000 comprises edge Circuit tuning 1001, buffer circuit 1002, the 3rd filter 1003 and differential amplifier 1004, wherein edge Circuit tuning 1001 receives control signal 5 that differential amplifier 1004 exports and the pulse signal of leggy pulse module output, described pulse signal rising edge and trailing edge are gone out to the time difference of now to be adjusted, and the pulse signal after adjusting is exported to buffer circuit 1002 and the 3rd filter 1003 simultaneously, the 3rd filter 1003 pulse signals are carried out integral operation, extract the common-mode voltage of pulse signal, the common-mode voltage of pulse signal is exported to differential amplifier 1004, described common-mode voltage and target voltage are asked difference operation by difference differential amplifier 1004, will ask difference operation result to export to edge Circuit tuning 1001 as control signal 5, after pulse signal after buffer circuit 1002 receptions are adjusted cushions, obtain clock signal and export to outside multipath A/D converter.In the time that the time difference that pulse signal rising edge in edge Circuit tuning goes out now time difference to trailing edge and this trailing edge go out now to next rising edge equates (in the time that common-mode voltage equates with target voltage), edge Circuit tuning completes adjustment process, the duty ratio of pulse signal is constant 50%, is finally cushioned rear output and had the clock signal of 50% constant duty ratio by buffer circuit 1002.
Be the circuit theory diagrams of duty ratio recovery circuit of the present invention as shown in figure 11, Figure 11 is a kind of circuit implementation of duty ratio recovery circuit.Edge Circuit tuning 1100 is made up of a current adjustment unit, can control charging current and discharging current respectively.Filter 1120 can be realized with simple RC circuit.And difference differential amplifier can be with one simply with the difference Cascode realization of common-mode feedback, generally the voltage of Vmid is set for to the half of working power voltage.Specific works sequential is referring to the explanation (Figure 12 is the sequential chart of duty ratio recovery circuit work of the present invention) of Figure 12.When the common mode component extracting is greater than Vmid, illustrate that the duty ratio of output pulse is greater than 50%, capacitor C 3 is charged, capacitor C 4 is discharged, Circuit tuning 1100 discharging currents in edge are greater than charging current, and the time of exporting the appearance of pulse trailing edge can be leading, and duty ratio can reduce; Otherwise, when the common mode component extracting is less than Vmid, illustrate that the duty ratio of output pulse is less than 50%, capacitor C 3 is discharged, capacitor C 4 is charged, Circuit tuning 1100 discharging currents in edge are less than charging current, and the time of exporting the rising edge appearance of pulse can be leading, and duty ratio can increase, finally, in the time that the duty ratio of output pulse equals 50%, charging and discharging currents is constant, thereby duty ratio also no longer changes.
The above; be only the embodiment of the best of the present invention, but protection scope of the present invention is not limited to this, is anyly familiar with in technical scope that those skilled in the art disclose in the present invention; the variation that can expect easily or replacement, within all should being encompassed in protection scope of the present invention.
The content not being described in detail in specification of the present invention belongs to professional and technical personnel in the field's known technology.
Claims (6)
1. the sampling clock for the time-interleaved analog to digital converter of multichannel produces circuit, it is characterized in that: comprise multiphase clock generation module, duty ratio recovery circuit and channel selecting module, described multiphase clock generation module comprises two phase clock module and leggy pulse module, wherein:
Two phase clock module: the global clock signal of outside input is carried out after anti-phase obtaining anti-phase global clock signal, described global clock signal and anti-phase global clock signal are carried out to phase difference calibration, and global clock signal and anti-phase global clock signal after calibration are exported to leggy pulse module;
Leggy pulse module: receive path is selected global clock signal and the anti-phase global clock signal after the control signal 2 of module output and the calibration of two phase clock module output, global clock signal after described calibration and inversion clock signal are carried out respectively to two points of computings of phase place by inner several multiphase clock generation units, and respectively two results of two points of computings of phase place are carried out to phase difference calibration, obtain the poor pulse signal of a series of equiphases, by described output of pulse signal to duty ratio recovery circuit;
Duty ratio recovery circuit: the pulse signal receiving from leggy pulse module is carried out to duty ratio recovery, and export sampled clock signal to outside multipath A/D converter;
Channel selecting module: receive the control signal 1 that outside serial ports writes, the inner passage number needing according to described control signal judgement, and control unlatching and the shutoff of inner passage, select the quantity of the inner multiphase clock generation unit of leggy pulse module simultaneously according to described control signal 1, and selection result is exported to leggy pulse module as control signal 2.
2. a kind of sampling clock for the time-interleaved analog to digital converter of multichannel according to claim 1 produces circuit, it is characterized in that: described two phase clock module comprises monolateral along phase discriminator, the first filter, differential amplifier and controllable time delay line, the wherein monolateral anti-phase global clock signal that receives the outside global clock signal of inputting and the output of controllable time delay line along phase discriminator, carry out phase demodulation operation, obtain two groups of square-wave signals, export to the first filter, the first filter receives described two groups of square-wave signals, extracts DC component, and two groups of DC component are exported to differential amplifier, differential amplifier is asked difference operation to two groups of DC component signals, to ask difference operation result to be input to controllable time delay line as control signal 3, controllable time delay line receives the global clock signal of outside input and the control signal 3 of amplifier output, the phase place of adjusting global clock signal obtains reverse global clock signal, in the time of 180 ° of the phase place of reverse global clock and the phase phasic differences of global clock signal, complete phase alignment, global clock signal after calibration and reverse global clock signal are exported to leggy pulse module, reverse global clock signal after calibration is exported to monolateral along phase discriminator simultaneously.
3. a kind of sampling clock for the time-interleaved analog to digital converter of multichannel according to claim 1 produces circuit, it is characterized in that: described leggy pulse module is made up of the multistage multiphase clock generation unit with same structure, every grade of multiphase clock generation unit comprises pulse-generating circuit and several phase alignment circuit, wherein: pulse-generating circuit receive path is selected global clock signal and the anti-phase global clock signal after the control signal 2 of module output and the calibration of two phase clock module output, select the quantity of inner multiphase clock generation unit according to described control signal 2, global clock signal and anti-phase global clock signal are carried out obtaining pulse signal after phase bit arithmetic, by described output of pulse signal to phase alignment circuit, described pulse signal is carried out respectively two points of computings of phase place by several phase alignment circuit, and respectively two results of two points of computings of phase place are carried out to phase difference calibration, obtain the poor pulse signal of a series of equiphases, by described output of pulse signal to duty ratio recovery circuit.
4. a kind of sampling clock for the time-interleaved analog to digital converter of multichannel according to claim 3 produces circuit, it is characterized in that: described each phase alignment circuit comprises bilateral along phase discriminator, charge pump, the second filter and delay line, the wherein bilateral pulse signal along the output of phase detector received pulse generation circuit and the pulse signal of delay line output, and two pulse signals are carried out to phase demodulation operation, obtain two groups of square-wave signals, export to charge pump; Charge pump receives described two groups of square-wave signals, adjusts the output voltage of charge pump by square-wave signal, and the voltage signal of output after adjusting is to the second filter; The second filter carries out filtering to the voltage signal after adjusting, and extracts DC component and is input to delay line as control signal 4; Delay line received pulse produces the pulse signal of circuit output and the control signal 4 of the second filter output, described pulse signal is carried out to two points of computings of phase place and obtain two pulse signals, when the phase difference of described two pulse signals is that the pulse signal rising edge of input is to the half of trailing edge time difference, complete phase alignment, and the pulse signal after calibration is exported to the bilateral pulse-generating circuit along phase discriminator and next stage multiphase clock generation unit simultaneously.
5. a kind of sampling clock for the time-interleaved analog to digital converter of multichannel according to claim 1 produces circuit, it is characterized in that: described duty ratio recovery circuit comprises edge Circuit tuning, buffer circuit, the 3rd filter and differential amplifier, wherein edge Circuit tuning receives the control signal 5 of differential amplifier output and the pulse signal of leggy pulse module output, described pulse signal rising edge and trailing edge are gone out to the time difference of now to be adjusted, and the pulse signal after adjusting is exported to buffer circuit and the 3rd filter simultaneously, the 3rd filter pulse signals is carried out integral operation, extract the common-mode voltage of pulse signal, the common-mode voltage of pulse signal is exported to differential amplifier, described common-mode voltage and target voltage are asked difference operation by difference differential amplifier, will ask difference operation result to export to edge Circuit tuning as control signal 5, after pulse signal after buffer circuit reception is adjusted cushions, obtain clock signal and export to outside multipath A/D converter, in the time that the time difference that pulse signal rising edge in edge Circuit tuning goes out now time difference to trailing edge and described trailing edge go out now to next rising edge equates, edge Circuit tuning completes adjustment process, the duty ratio of pulse signal is constant 50%, is finally cushioned rear output and had the clock signal of 50% constant duty ratio by buffer circuit.
6. a kind of sampling clock for the time-interleaved analog to digital converter of multichannel according to claim 5 produces circuit, it is characterized in that: in the time that integral operation result equates with target voltage, edge adjustment no longer changes, and finally exports the clock signal with 50% constant duty ratio by buffer circuit.
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| US11962309B2 (en) | 2022-06-06 | 2024-04-16 | Changxin Memory Technologies, Inc. | Phase adjusting circuit, delay locking circuit, and memory |
| CN118157678A (en) * | 2024-03-25 | 2024-06-07 | 北京领丰视芯科技有限责任公司 | A high frame rate parallel digital readout circuit, analog-to-digital converter and electronic equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7852245B2 (en) * | 2007-08-10 | 2010-12-14 | Marvell World Trade Ltd. | Method and apparatus for calibrating a replica digital-to-analog converter |
| CN102761319A (en) * | 2012-04-27 | 2012-10-31 | 北京时代民芯科技有限公司 | Clock circuit capable of realizing stable duty ratio and phase calibration |
| CN103312329A (en) * | 2013-05-23 | 2013-09-18 | 电子科技大学 | Correcting method and corrector used for sampling time mismatch of time-interweaving ADC (analog to digital converter) |
-
2014
- 2014-04-08 CN CN201410141378.3A patent/CN103944568B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7852245B2 (en) * | 2007-08-10 | 2010-12-14 | Marvell World Trade Ltd. | Method and apparatus for calibrating a replica digital-to-analog converter |
| CN102761319A (en) * | 2012-04-27 | 2012-10-31 | 北京时代民芯科技有限公司 | Clock circuit capable of realizing stable duty ratio and phase calibration |
| CN103312329A (en) * | 2013-05-23 | 2013-09-18 | 电子科技大学 | Correcting method and corrector used for sampling time mismatch of time-interweaving ADC (analog to digital converter) |
Non-Patent Citations (1)
| Title |
|---|
| 朱志东 等: "一种宽带高性能TIADC时钟发生器", 《数据采集与处理》 * |
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