CN103928342B - A kind of silicon nanowires tunneling field-effect transistor and preparation method thereof - Google Patents
A kind of silicon nanowires tunneling field-effect transistor and preparation method thereof Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 172
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 172
- 239000010703 silicon Substances 0.000 title claims abstract description 172
- 239000002070 nanowire Substances 0.000 title claims abstract description 117
- 230000005641 tunneling Effects 0.000 title claims abstract description 54
- 238000002360 preparation method Methods 0.000 title claims abstract description 40
- 238000002353 field-effect transistor method Methods 0.000 title abstract description 7
- 239000010410 layer Substances 0.000 claims abstract description 105
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 59
- 238000000034 method Methods 0.000 claims abstract description 40
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 30
- 238000005260 corrosion Methods 0.000 claims abstract description 26
- 230000007797 corrosion Effects 0.000 claims abstract description 26
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 21
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 20
- 239000001301 oxygen Substances 0.000 claims abstract description 20
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims abstract description 18
- 239000011241 protective layer Substances 0.000 claims abstract description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 14
- 230000008569 process Effects 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000001259 photo etching Methods 0.000 claims abstract description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 7
- 230000005669 field effect Effects 0.000 claims description 42
- 150000002500 ions Chemical class 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 12
- 238000007254 oxidation reaction Methods 0.000 claims description 12
- 229910052681 coesite Inorganic materials 0.000 claims description 7
- 229910052906 cristobalite Inorganic materials 0.000 claims description 7
- 229910052682 stishovite Inorganic materials 0.000 claims description 7
- 229910052905 tridymite Inorganic materials 0.000 claims description 7
- 239000007788 liquid Substances 0.000 claims description 6
- 238000002161 passivation Methods 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 239000003989 dielectric material Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000009776 industrial production Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 15
- 230000007246 mechanism Effects 0.000 description 6
- 230000008859 change Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 241000209094 Oryza Species 0.000 description 3
- 235000007164 Oryza sativa Nutrition 0.000 description 3
- 230000003321 amplification Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 235000012149 noodles Nutrition 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 235000009566 rice Nutrition 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000002090 nanochannel Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
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Abstract
The present invention provides a kind of silicon nanowires tunneling field-effect transistor and preparation method thereof, including step：1）One SOI substrate, including bottom silicon, oxygen buried layer and top layer silicon are provided；2）The top silicon layer is thinned and forms silicon dioxide layer in surface；3）Silicon nanowires raceway groove, source region and drain region are formed using photoetching process and wet corrosion technique；4）Protective layer is formed in the side of the source region, the week side of boss in drain region and silicon nanowires raceway groove, the opposite side of the silicon nanowires raceway groove is corroded using wet corrosion technique, forms the silicon nanowires raceway groove with triangular-section；5）Oxide layer is formed in the silicon nanowires channel surface；6）Form source region and drain region；7）Make source electrode and drain electrode.The silicon nanowires of the present invention is based on top-down methods, is realized and made using silicon nitride sidewall protection and TMAH anisotropy etch stop, technical process is simple, and controllability is strong, and completely compatible with existing semiconductor technology, cost is relatively low, suitable for industrial production.
Description
Technical field
The present invention relates to a kind of semiconductor device structure and preparation method thereof, more particularly to a kind of silicon nanowires tunnelling field
Effect transistor and preparation method thereof.
Background technology
In recent years, as the continuous diminution of device size, the performance of integrated circuit have obtained large increase, integrated level is continuous
Rise, cost constantly declines but the continuous reduction of cmos device size brings some problems, it is further developed and is limited
System.(1) MOSFET raceway groove, which shortens, causes static leakage to become big, and (2) MOSFET Sub-Threshold Characteristic is by basic physical principle
Limitation, switching rate are limited in gate voltage and often change 60mV curent change an order of magnitude, i.e., universal described 60mV/dec
Subthreshold swing (SS) limitation.These have become the maximum obstruction that device size continues to zoom out, therefore reduce the quiet of device
State is leaked electricity, and the switching rate for improving device has become and too impatient to wait needs to solve the problems, such as.
To solve the above problems, researcher proposes the various new device based on different operating principle, one kind is logical
The device of feedback or gain mechanism method enhancing amplification characteristic is crossed, another is that Current mechanism does not directly rely on spy with temperature
The device of property.This two classes device can be referred to as the device based on amplification mechanism and the device based on tunneling effect.
Device based on amplification mechanism mainly has the SOI transistor of part depletion, negative grid capacitor element and ionization by collision transistor.
Device based on tunneling mechanism has Schottky-barrier MOSFET, FN tunneling transistors and direct tunneling transistor, tunnelling field
Effect transistor (TFET).But at present there are certain usability problems in them mostly.The SOI transistor of part depletion has back
Residual effect should, i.e. the hole of cylinder accumulation reduce the threshold voltage of device, it is necessary to long time could it is compound fall these holes
Make ringing back to original threshold voltage；Negative grid capacitor element is limited by some special ferroelectric materials；Ionization by collision is brilliant
The threshold voltage of body pipe is unstable, poor reliability, and needs very high drain-source voltage；Schottky-barrier MOSFET and FN tunnellings are brilliant
Body pipe has excessively poor leakage current characteristic；And directly tunneling transistor is due to needing sufficiently thin dielectric layer so as to be sent out between source and drain
Raw carrier tunnelling, can not also realize the preparation of device in kind at present.
Tunneling field-effect device is a kind of device of the tunnel-effect work based on carrier, because its excellent subthreshold value is special
Property and extremely low leakage current and receive much concern.In order to preferably play the performance advantage of tunneling device, tunneling mechanism is employed
Onto different components structure, feature possessed by new device structure is coordinated to be expected to further improve device performance.Because silicon is received
Rice noodles have excellent electrical and mechanical characteristic, larger specific surface area, excellent grid-control ability, silicon nanowires tunneling field-effect
Device is one of them.
However, inexpensive, the extensive preparation of silicon nanowires tunneling field-effect transistor still suffers from some difficulties.
CN102956709A discloses a kind of bi-material layers gate nano line tunneling field-effect device and its manufacture method, and the patent is using etching
Form silicon column, oxidation, the method for corrosion scale carry out the preparation of silicon nanowires, what this specific lithographic method resulted in
Silicon nanometer size heterogeneity, controllability are poor.CN103558279A and document (IEEE Electron Device
Letters, 33 (11), 1535-1537,2012) silicon nanowires is formed using lithographic method in, manufacturing process needs to use electronics
The expensive equipment such as beam exposure carry out photoetching, and this make it that cost of manufacture is higher.CN101375398A, CN102412301A and document
Using bottom-to-top method growth nano wire, this side in (Applied Physics Letter, 92,193504,2008)
The nano wire that method is prepared is difficult to operate and positioned easily by catalyst contamination.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide a kind of silicon nanowires tunneling field-effect
Transistor and preparation method thereof, it is high for solving silicon nanowires tunneling field-effect transistor in the prior art and cost of manufacture, it is fixed
The problem of position difficulty etc..
In order to achieve the above objects and other related objects, the present invention provides a kind of silicon nanowires tunneling field-effect transistor
Preparation method, including step：
1) SOI substrate is provided, the SOI substrate includes bottom silicon, oxygen buried layer and top layer silicon；
2) the top silicon layer is thinned and forms silicon dioxide layer in the top silicon surface；
3) silicon nanowires raceway groove is defined using photoetching process and is connected to the source region at the silicon nanowires raceway groove both ends, leakage
Area's figure, silicon nanowires raceway groove, source region and drain region are formed using wet corrosion technique；
4) protective layer is formed in the side of the source region, the week side of boss in drain region and silicon nanowires raceway groove, using wet etching work
Skill is corroded to the opposite side of the silicon nanowires raceway groove, forms the silicon nanowires raceway groove with triangular-section；
5) protective layer is removed, oxide layer is formed in the silicon nanowires channel surface using thermal oxidation technology；
6) source region and drain region are formed by ion implantation technology and annealing process respectively；
7) source electrode and drain electrode are made, and makes gate electrode in the source region, drain region surface.
As a kind of preferred scheme of the preparation method of the silicon nanowires tunneling field-effect transistor of the present invention, step 2) bag
Include step：
Oxidation 2-1) is carried out to the top layer silicon using thermal oxidation technology and forms silicon dioxide layer, until residual thickness is 20
~80nm top layer silicon；
Silicon dioxide layer described in HF solution corrosions 2-2) is used until obtaining silicon dioxide layer of the thickness for 100~200nm.
As a kind of preferred scheme of the preparation method of the silicon nanowires tunneling field-effect transistor of the present invention, step 3)
In, anisotropic wet corrosion is carried out to the top layer silicon using TMAH corrosive liquids, to form the silicon nanowires raceway groove, source region
And drain region, wherein, corrosion temperature is 50~80 DEG C, and etching time is 5~10min.
As the present invention silicon nanowires tunneling field-effect transistor preparation method a kind of preferred scheme, step 4)
Wet etching includes：
The silicon dioxide layer of the silicon nanowires channel surface is removed using HF solution, while exposed oxygen buried layer is carried out
Corrosion is formed until exposing the groove of the top layer silicon；
The silicon nano-channel is corroded using TMAH corrosive liquids, until forming the silicon nanometer with triangular-section
Wire channel.
As a kind of preferred scheme of the preparation method of the silicon nanowires tunneling field-effect transistor of the present invention, in step 7)
Gate electrode be made in the groove.
As a kind of preferred scheme of the preparation method of the silicon nanowires tunneling field-effect transistor of the present invention, step 4)
In, the material of the protective layer is silicon nitride, the channel width with triangular-section silicon nanowires raceway groove be 30~
100nm。
As a kind of preferred scheme of the preparation method of the silicon nanowires tunneling field-effect transistor of the present invention, step 5) institute
The thickness for the oxide layer stated is 10~30nm.
As a kind of preferred scheme of the preparation method of the silicon nanowires tunneling field-effect transistor of the present invention, step 6) bag
Include step：
6-1) using photoresist and dielectric layer as mask, carry out the first conductive type ion and inject to form source region, the source region
Ion doping concentration be about 1e20cm-3~1e21cm-3；
6-2) using photoresist and dielectric layer as mask, carry out the second conductive type ion and inject to form drain region.
As the present invention silicon nanowires tunneling field-effect transistor preparation method a kind of preferred scheme, described first
Conduction type is p-type, and the second conduction type is N-type；Or first conduction type is N-type, the second conduction type is p-type.
As a kind of preferred scheme of the preparation method of the silicon nanowires tunneling field-effect transistor of the present invention, the medium
Layer is SiO2、Si3N4, polysilicon or above-mentioned material multiple-level stack.
As a kind of preferred scheme of the preparation method of the silicon nanowires tunneling field-effect transistor of the present invention, step 7) is also
It is included in the step of device surface forms passivation layer, the passivation layer is SiO2、Si3N4, high-K gate dielectric material or above-mentioned material
Multiple-level stack.
The present invention also provides a kind of silicon nanowires tunneling field-effect transistor, including：
Bottom silicon；
Oxygen buried layer, it is incorporated into the bottom silicon face；
Silicon nanowires raceway groove, it is formed on the oxygen buried layer, the cross sectional shape of the silicon nanowires raceway groove is triangle；
Source region and drain region, it is formed on the oxygen buried layer and positioned at the both ends of the silicon nanowires raceway groove；
Oxide layer, it is formed at the nanowire channel surface；
Source electrode, drain electrode, it is respectively formed in the source region, drain region surface.
As a kind of preferred scheme of the silicon nanowires tunneling field-effect transistor of the present invention, in the oxygen buried layer formed with
Groove, formed with gate electrode in the groove.
As the present invention silicon nanowires tunneling field-effect transistor a kind of preferred scheme, the silicon nanowires raceway groove
Channel width is 30~100nm.
As a kind of preferred scheme of the silicon nanowires tunneling field-effect transistor of the present invention, the thickness of the oxide layer is
10~30nm.
As a kind of preferred scheme of the silicon nanowires tunneling field-effect transistor of the present invention, the ion doping of the source region
Type is p-type, and the ion doping concentration in the drain region is N-type；Or the ion doping type of the source region is N-type, the drain region
Ion doping concentration be p-type.
As a kind of preferred scheme of the silicon nanowires tunneling field-effect transistor of the present invention, the ion doping of the source region
Concentration is 1e20cm-3~1e21cm-3。
As described above, the present invention provides a kind of silicon nanowires tunneling field-effect transistor and preparation method thereof, the making
Method includes step：1) SOI substrate is provided, the SOI substrate includes bottom silicon, oxygen buried layer and top layer silicon；2) it is thinned described
Push up silicon layer and form silicon dioxide layer in the top silicon surface；3) silicon nanowires raceway groove and company are defined using photoetching process
Be connected to source region, the drain region figure at the silicon nanowires raceway groove both ends, using wet corrosion technique formed silicon nanowires raceway groove, source region and
Drain region；4) protective layer is formed in the side of the source region, the week side of boss in drain region and silicon nanowires raceway groove, using wet corrosion technique pair
The opposite side of the silicon nanowires raceway groove is corroded, and forms the silicon nanowires raceway groove with triangular-section；5) described in removing
Protective layer, oxide layer is formed in the silicon nanowires channel surface using thermal oxidation technology；6) ion implantation technology is passed through respectively
And annealing process forms source region and drain region；7) source electrode and drain electrode are made in the source region, drain region surface.The silicon of the present invention is received
Rice noodles are based on top-down methods, are realized and made using silicon nitride sidewall protection and TMAH anisotropy etch stop, technique
Process is simple, and controllability is strong, and completely compatible with existing semiconductor technology, cost is relatively low, suitable for industrial production.
Brief description of the drawings
Fig. 1 is shown as the structure that the preparation method step 1) of the silicon nanowires tunneling field-effect transistor of the present invention is presented
Schematic diagram.
Fig. 2 is shown as the structure that the preparation method step 2) of the silicon nanowires tunneling field-effect transistor of the present invention is presented
Schematic diagram.
The preparation method step 3) that Fig. 3 a~Fig. 4 is shown as the silicon nanowires tunneling field-effect transistor of the present invention is presented
Structural representation, wherein, Fig. 3 b are overlooking the structure diagram, and Fig. 3 a are the cross section structure schematic diagram of A-A ' in Fig. 3 b.
The preparation method step 4) that Fig. 5~Fig. 6 is shown as the silicon nanowires tunneling field-effect transistor of the present invention is presented
Structural representation.
Fig. 7 is shown as the structure that the preparation method step 5) of the silicon nanowires tunneling field-effect transistor of the present invention is presented
Schematic diagram.
Fig. 8 is shown as the structure that the preparation method step 6) of the silicon nanowires tunneling field-effect transistor of the present invention is presented
Schematic diagram.
The preparation method step 7) of silicon nanowires tunneling field-effect transistor that Fig. 9 a~Fig. 9 b are shown as the present invention is in
Existing structural representation, wherein, Fig. 9 b are overlooking the structure diagram, and Fig. 9 a are the cross section structure schematic diagram of A-A ' in Fig. 9 b.
Component label instructions
101 bottom silicon
102 oxygen buried layers
103 top layer silicons
104 silicon dioxide layers
105 source regions
106 drain regions
107 silicon nanowires raceway grooves
108 protective layers
109 oxide layers
110 source electrodes
111 drain electrodes
112 gate electrodes
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Refer to Fig. 1~Fig. 9 b.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, the component relevant with the present invention is only shown in schema then rather than according to package count during actual implement
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout kenel may also be increasingly complex.
As shown in Fig. 1~Fig. 9 b, the present embodiment provides a kind of preparation method of silicon nanowires tunneling field-effect transistor, bag
Include step：
As shown in figure 1, step 1) is carried out first, there is provided a SOI substrate, the SOI substrate include bottom silicon 101, bury oxygen
Layer 102 and top layer silicon 103.
In the present embodiment, for the bottom silicon 101 to be lightly doped or low-doped P-type silicon substrate, its crystal orientation is that (100) take
To.
As shown in Fig. 2 then carrying out step 2), the top silicon layer is thinned and forms silica in the top silicon surface
Layer 104.
Specifically, the step includes step：
Oxidation 2-1) is carried out to the top layer silicon 103 using thermal oxidation technology and forms silicon dioxide layer 104, until remaining wall
The top layer silicon 103 for 20~80nm is spent, in the present embodiment, the thickness of remaining top layer silicon 103 is 50nm.
Silicon dioxide layer 104 described in HF solution corrosions 2-2) is used until obtaining silica of the thickness for 100~200nm
Layer 104, in the present embodiment, the thickness of the silicon dioxide layer 104 is 150nm, and the mask layer of subsequent technique is used as using it.
As shown in Fig. 3 a~Fig. 4, wherein, Fig. 3 b are overlooking the structure diagram, and Fig. 3 a are the cross section structure of A-A ' in Fig. 3 b
Schematic diagram, step 3) is then carried out, silicon nanowires raceway groove 107 is defined using photoetching process and is connected to the silicon nanowires ditch
The source region 105 at the both ends of road 107, the figure of drain region 106, using wet corrosion technique formed silicon nanowires raceway groove 107, source region 105 and
Drain region 106.
Specifically, in step 3), anisotropic wet corrosion is carried out to the top layer silicon 103 using TMAH corrosive liquids, with
The silicon nanowires raceway groove 107, source region 105 and drain region 106 are formed, wherein, corrosion temperature is 50~80 DEG C, etching time 5
~10min.In the present embodiment, corrosion temperature is 60 DEG C, etching time 8min.The source region 105 of the present embodiment formation, drain region
106 and silicon nanowires raceway groove 107 cross sectional shape to be trapezoidal.
As shown in figures 5 and 6, step 4) is then carried out, in the source region 105, the week side of boss in drain region 106 and silicon nanowires ditch
The side in road 107 forms protective layer 108, the opposite side of the silicon nanowires raceway groove 107 is carried out using wet corrosion technique rotten
Erosion, form the silicon nanowires raceway groove 107 with triangular-section.
In the present embodiment, the material of the protective layer 108 is silicon nitride.The silicon nitride be formed at the source region 105,
The surface of the silicon dioxide layer 104 on drain region 106 and its surface, and the side of the silicon nanowires groove, expose the silicon and receive
Another layer of rice noodles groove and partial oxygen buried layer 102.
Specifically, the wet etching of step 4) includes：
The silicon dioxide layer 104 on the surface of silicon nanowires raceway groove 107 is removed using HF solution, while oxygen is buried to exposed
Layer 102 carries out corrosion and formed until exposing the groove of the top layer silicon 103；
The silicon nano-channel is corroded using TMAH corrosive liquids, until forming the silicon nanometer with triangular-section
Wire channel 107.
As an example, the channel width with triangular-section silicon nanowires raceway groove 107 is 30~100nm, at this
In embodiment, the cross sectional shape of the silicon nanowires raceway groove 107 is equilateral triangle, channel width 50nm.
As shown in fig. 7, then carrying out step 5), the protective layer 108 is removed, using thermal oxidation technology in the silicon nanometer
The surface of wire channel 107 forms oxide layer 109.
As an example, the thickness of the oxide layer 109 is 10~30nm.
As shown in figure 8, then carry out step 6), respectively by ion implantation technology and annealing process formed source region 105 and
Drain region 106.
Specifically, step 6) includes step：
6-1) using photoresist and dielectric layer as mask, carry out the first conductive type ion and inject to form source region 105, the source
The ion doping concentration in area 105 is about 1e20cm-3~1e21cm-3；
6-2) using photoresist and dielectric layer as mask, carry out the second conductive type ion and inject to form drain region 106.
As an example, first conduction type is p-type, the second conduction type is N-type；Or first conduction type is
N-type, the second conduction type are p-type.In the present embodiment, first conduction type is p-type, the injection ion used for boron,
Second conduction type is N-type, and the injection ion used is phosphorus.
As an example, the dielectric layer is SiO2、Si3N4, polysilicon or above-mentioned material multiple-level stack.In the present embodiment
In, the dielectric layer is SiO2And Si3N4The lamination of composition.
As shown in Fig. 9 a~Fig. 9 b, wherein, Fig. 9 b are overlooking the structure diagram, and Fig. 9 a are the cross section structure of A-A ' in Fig. 9 b
Schematic diagram, step 7) is finally carried out, make source electrode 110 and drain electrode 111 in the source region 105, the surface of drain region 106, and make
Make gate electrode 112.
As an example, the gate electrode 112 is made in the groove that step 4) is formed.The source electrode 110, drain electrode
111 and the material of gate electrode 112 be the metal material such as Al, Cu.
As an example, step 7) is also included in the step of device surface forms passivation layer, the passivation layer is SiO2、
Si3N4, high-K gate dielectric material or above-mentioned material multiple-level stack.
As shown in Fig. 9 a~Fig. 9 b, wherein, Fig. 9 b are overlooking the structure diagram, and Fig. 9 a are the cross section structure of A-A ' in Fig. 9 b
Schematic diagram, the present embodiment also provide a kind of silicon nanowires tunneling field-effect transistor, including：
Bottom silicon 101；
Oxygen buried layer 102, it is incorporated into the surface of bottom silicon 101；
Silicon nanowires raceway groove 107, it is formed on the oxygen buried layer 102, the cross sectional shape of the silicon nanowires raceway groove 107 is
Triangle；
Source region 105 and drain region 106, it is formed on the oxygen buried layer 102 and positioned at the two of the silicon nanowires raceway groove 107
End；
Oxide layer 109, it is formed at the nanowire channel surface；
Source electrode 110, drain electrode 111, it is respectively formed in the source region 105, the surface of drain region 106.
As an example, the bottom silicon 101 is is lightly doped or low-doped P-type silicon substrate, its crystal orientation is (100) orientation.
As an example, formed with groove in the oxygen buried layer 102, formed with gate electrode 112 in the groove.
As an example, the channel width of the silicon nanowires raceway groove 107 is 30~100nm.
As an example, the thickness of the oxide layer 109 is 10~30nm.
As an example, the ion doping type of the source region 105 is p-type, the ion doping concentration in the drain region 106 is N
Type；Or the ion doping type of the source region 105 is N-type, the ion doping concentration in the drain region 106 is p-type.
As an example, the ion doping concentration of the source region 105 is 1e20cm-3~1e21cm-3。
As described above, the present invention provides a kind of silicon nanowires tunneling field-effect transistor and preparation method thereof, the making
Method includes step：1) SOI substrate is provided, the SOI substrate includes bottom silicon 101, oxygen buried layer 102 and top layer silicon 103；2)
The top silicon layer is thinned and forms silicon dioxide layer 104 in the top silicon surface；3) silicon nanometer is defined using photoetching process
Wire channel 107 and the source region 105 at the both ends of silicon nanowires raceway groove 107, the figure of drain region 106 are connected to, using wet etching work
Skill forms silicon nanowires raceway groove 107, source region 105 and drain region 106；4) in the source region 105, the week side of boss in drain region 106 and silicon nanometer
The side of wire channel 107 forms protective layer 108, and the opposite side of the silicon nanowires raceway groove 107 is entered using wet corrosion technique
Row corrosion, forms the silicon nanowires raceway groove 107 with triangular-section；5) protective layer 108 is removed, using thermal oxidation technology
Oxide layer 109 is formed in the surface of silicon nanowires raceway groove 107；6) source is formed by ion implantation technology and annealing process respectively
Area 105 and drain region 106；7) source electrode 110 and drain electrode 111 are made in the source region 105, the surface of drain region 106.The silicon of the present invention
Nano wire is based on top-down methods, is realized and made using silicon nitride sidewall protection and TMAH anisotropy etch stop, work
Skill process is simple, and controllability is strong, and completely compatible with existing semiconductor technology, cost is relatively low, suitable for industrial production.So this
Invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (10)
1. a kind of preparation method of silicon nanowires tunneling field-effect transistor, it is characterised in that including step：
1) SOI substrate is provided, the SOI substrate includes bottom silicon, oxygen buried layer and top layer silicon；
2) be thinned the top layer silicon and in the top layer silicon face formed silicon dioxide layer, wherein, obtain residual thickness be 20~
80nm top layer silicon, and thickness is the structure of 100~200nm silicon dioxide layer；
3) silicon nanowires raceway groove is defined using photoetching process and is connected to the source region at the silicon nanowires raceway groove both ends, drain region figure
Shape, silicon nanowires raceway groove, source region and drain region are formed using wet corrosion technique；
4) protective layer is formed in the side of the source region, the week side of boss in drain region and silicon nanowires raceway groove, is gone using wet corrosion technique
Except the silicon nanowires channel surface opposite side does not cover the silicon dioxide layer of the region exposure of the protective layer, while to exposed
Oxygen buried layer carry out corrosion and formed until exposing the groove of the bottom silicon；Using wet corrosion technique to the silicon nanowires ditch
The opposite side in road is corroded, until the silicon nanowires raceway groove with triangular-section is formed, wherein, including first make required formation
Silicon nanowires apex it is exposed, then corrode remaining top layer silicon to form the technique of the nano wire with triangular-section, it is described
Channel width with triangular-section silicon nanowires raceway groove is 30~100nm；
5) protective layer is removed, oxide layer is formed in the silicon nanowires channel surface using thermal oxidation technology；
6) source region and drain region are formed by ion implantation technology and annealing process respectively；
7) source electrode and drain electrode are made in the source region, drain region surface, and in making gate electrode in the groove.
2. the preparation method of silicon nanowires tunneling field-effect transistor according to claim 1, it is characterised in that：Step 2)
Including step：
Oxidation 2-1) is carried out to the top layer silicon using thermal oxidation technology and forms silicon dioxide layer, until residual thickness be 20~
80nm top layer silicon；
Silicon dioxide layer described in HF solution corrosions 2-2) is used until obtaining silicon dioxide layer of the thickness for 100~200nm.
3. the preparation method of silicon nanowires tunneling field-effect transistor according to claim 1, it is characterised in that：Step 3)
In, anisotropic wet corrosion is carried out to the top layer silicon using TMAH corrosive liquids, to form the silicon nanowires raceway groove, source region
And drain region, wherein, corrosion temperature is 50~80 DEG C, and etching time is 5~10min.
4. the preparation method of silicon nanowires tunneling field-effect transistor according to claim 1, it is characterised in that：Step 4)
Wet etching include：
The silicon dioxide layer of the silicon nanowires channel surface is removed using HF solution, while exposed oxygen buried layer is corroded
Formed until exposing the groove of the top layer silicon；
The silicon nanowires raceway groove is corroded using TMAH corrosive liquids, until forming the silicon nanowires with triangular-section
Raceway groove.
5. the preparation method of silicon nanowires tunneling field-effect transistor according to claim 1, it is characterised in that：Step 4)
In, the material of the protective layer is silicon nitride.
6. the preparation method of silicon nanowires tunneling field-effect transistor according to claim 1, it is characterised in that：Step 5)
The thickness of described oxide layer is 10~30nm.
7. the preparation method of silicon nanowires tunneling field-effect transistor according to claim 1, it is characterised in that：Step 6)
Including step：
6-1) using photoresist and dielectric layer as mask, carry out the first conductive type ion inject to form source region, the source region from
Sub- doping concentration is 1e20cm-3~1e21cm-3；
6-2) using photoresist and dielectric layer as mask, carry out the second conductive type ion and inject to form drain region.
8. the preparation method of silicon nanowires tunneling field-effect transistor according to claim 7, it is characterised in that：Described
One conduction type is p-type, and the second conduction type is N-type；Or first conduction type is N-type, the second conduction type is p-type.
9. the preparation method of silicon nanowires tunneling field-effect transistor according to claim 7, it is characterised in that：Given an account of
Matter layer is SiO2、Si3N4, polysilicon or above-mentioned material multiple-level stack.
10. the preparation method of silicon nanowires tunneling field-effect transistor according to claim 1, it is characterised in that：Step
7) also it is included in the step of device surface forms passivation layer, the passivation layer is SiO2、Si3N4, high-K gate dielectric material or above-mentioned
The multiple-level stack of material.
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| CN103558279A (en) * | 2013-11-15 | 2014-02-05 | 中国科学院上海微系统与信息技术研究所 | Biosensor based on silicon nanowire tunneling field effect transistor and manufacturing method of biosensor |
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