CN103928320B - The preparation method of trench gate carborundum insulated gate bipolar transistor - Google Patents
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Abstract
The invention discloses the preparation method of a kind of trench gate carborundum insulated gate bipolar transistor, mainly solve the problem that current carborundum insulated gate bipolar transistor preparation cost is too high.Implementation step includes: 1. select the p-type silicon carbide substrates that structural behaviour is excellent, cuts thinning to this substrate back and polishes oxygen cutting face；2. pass sequentially through ion implanting in substrate face, form N well region, N+Body contact area, p-well region；3. etch groove in substrate face, then growth trench gate oxide layer, and carry out polysilicon deposit, make polysilicon fill up groove；4. at substrate back ion implanting cushion and collecting zone；5. high annealing, activates implanted dopant；6. prepare device electrode.Compared with the conventional method, the present invention need not the Withstand voltage layer that epitaxial growth is blocked up, saves a large amount of production cost, simplifies processing step, can be used for inverter, Switching Power Supply and illumination circuit field.
Description
Technical field
The invention belongs to microelectronics technology, relate to the preparation method of semiconductor device, a kind of trench gate structure SiC IGBT utilizing substrate to serve as Withstand voltage layer, can be widely used for the fields such as converter, inverter, Switching Power Supply, lighting circuit and motor.
Technical background
Carborundum insulated gate bipolar transistor, i.e. SiC IGBT, is the novel high pressure-resistant device grown up based on carbofrax material.The solid-state main flow device of field of power electronics application at present is Si IGBT, and it turns off voltage is 0.6～6.5kV.Through the development of 30 years, Si IGBT reached the limit of performance and device architecture, and along with new application developments such as electric automobile, photovoltaic and wind energy green energy resource, intelligent grids, it is desirable to leap new in power electronic devices performance.The breakthrough of the SiC semiconductor material with wide forbidden band of low micropipe defect density, makes a new generation's power electronic devices be possibly realized.The material structure of broad stopband causes the improvement of the performances such as semiconductor device Low dark curient, elevated operating temperature and Flouride-resistani acid phesphatase.Wide bandgap semiconductor SiC has the critical breakdown electric field of an order of magnitude higher than Si, it is meant that the shutoff drift layer of SiC power electronic devices can be thinner and have higher doping content, cause SiC with Si equivalent device compared with there is the conducting resistance of a low magnitude；Higher carrier saturation velocity causes higher operating frequency；Higher thermal conductivity will improve heat dissipation, make device can be operated in higher power density.
The mid-90 in 20th century proposes a kind of new ideas, i.e. IGBT uses U-channel grid structure, and it have employed uses for reference, from large-scale integrated technique, the silicon dry etching technology of coming.In trench gate IGBT, grid voltage forms electron accumulation layer in drift region, enhances the electronics in PIN diode and injects, improves the carrier concentration on surface.And MOS structure " T " the font conductive path in original IGBT shortens to two parallel vertical conductive vias, raceway groove, from laterally becoming longitudinally, causes cell density to reduce, thus adds the channel area in per device area, and then reduce channel resistance；And groove grid eliminate JFET effect, do not have electric current " bottleneck " region.So compared with planar gate IGBT, trench gate IGBT can be greatly reduced on-state voltage drop, thus reaches more excellent trading off between on-state voltage drop and shutoff energy.Additionally, relative to PNP transistor electric current, the increase of PIN diode electric current proportion can effectively suppress latching effect, so trench gate IGBT has bigger SOA safety operation area than planar gate IGBT.
The processing step of traditional trench gate SiC IGBT is as follows: first grown buffer layer on substrate silicon face；Grow the extension Withstand voltage layer of 50～200 μ m-thick the most on the buffer layer；Then on Withstand voltage layer, well region, launch site and heavy doping body contact area are formed by ion implanting；Then at substrate face etching groove, groove gate oxide, depositing polysilicon groove grid are grown；Finally deposit, the metal contact of lithographic device.Deficiency of both the existence of this method: one is that preparation cost is high.Such as, SiC epitaxial device is expensive, and epitaxial process power consumption is big；Two be grow big compared with the technical difficulty of thick SiC epitaxial layer, such as growing 100 μm and the epitaxial layer of above thickness, its technological requirement is high, the most only as Cree etc., top silicon carbide device company just can accomplish, therefore, technical bottleneck problem limits the universal of high-power SiC IGBT and application.
Summary of the invention
Present invention aim at proposing the novel processing step of a kind of trench gate carborundum insulated gate bipolar transistor, high to solve prior art preparation cost, the problem that technology difficulty is big, it is achieved the universal and application of high-power SiC IGBT.
Technical scheme comprises the following steps:
(1) selecting the p-type SiC substrate of zero micro-pipe, its base plane dislocation is 104/cm-3, substrate concentration is 3 × 1014～8 × 1014cm-3, the back side along this p-type SiC substrate is cut so that it is is thinned to 100 μm, then is polished facet successively, aoxidizes and remove removing oxide layer；
(2) the p-type SiC substrate front Nitrogen ion at described zero micro-pipe carries out twice N trap ion implanting: implantation dosage is 1.5 × 10 for the first time12cm-2～7.5 × 1012cm-2, Implantation Energy is 300～700Kev；Implantation dosage 8 × 10 for the second time11cm-2～4 × 1012cm-2Implantation Energy is 200～450Kev, forms N well region；
(3) in N well region upper left side and top-right region, heavy doping N is carried out with Nitrogen ion+Ion implanting: implantation dosage is 9 × 1013～7 × 1014cm-2, Implantation Energy is 150～300Kev, forms body contact area；
(4) ion implanting is carried out at territory, N well region upper middle zone Al ion: implantation dosage is 3 × 1014cm-2～1 × 1015cm-2, Implantation Energy is 150～300Kev, forms p-well region；
(5) depositing a layer thickness in the p-type SiC substrate of whole zero micro-pipe is the SiO of 0.2um2, zone line lithographic trenches window on p-well region, and this window bottom SiC substrate is carried out etching groove, until groove is positioned at below N trap, make p-well region be spaced as left and right two parts, these left and right two parts become launch site；
(6) bottom and sidewall to the above-mentioned groove etched aoxidize, and form trench gate oxide layer；
(7) in the long groove having trench gate oxide layer, low pressure hot wall chemical vapor deposition method growing polycrystalline silicon is used, until polysilicon fills up groove；
(8) back side aluminium ion in the p-type SiC substrate of described zero micro-pipe carries out ion implanting, and implantation dosage is 4 × 1012cm-2～3 × 1013cm-2, Implantation Energy is 400～600Kev, forms p-type cushion；
(9) N is carried out at p-type surface on back side of SiC substrate Nitrogen ion+Ion implanting, implantation dosage is 4 × 1013～2 × 1014cm-2, Implantation Energy is 200～350Kev, forms collecting zone；
(10) the p-type SiC substrate of described zero micro-pipe is placed at 1700 DEG C carries out high annealing 8～15 minutes, activating all implanted dopants；
(11) the p-type SiC substrate front at described zero micro-pipe etches the side wall of polysilicon gate, then deposits titanium coating and nickel metal layer, go forward side by side row metal photoetching and etching in this substrate face successively, draws emitter stage and grid；
(12) it is 1 μm nickel metal layer at aforementioned p-type surface on back side of SiC substrate deposition thickness, draws colelctor electrode；
(13) by completing the substrate after above-mentioned steps metal sintering 4～7 minutes at a temperature of 900 DEG C, element manufacturing is completed.
Due to the fact that selection does not has the p-type SiC substrate of micro-tubular structure to prepare trench gate IGBT device, it is not necessary to carry out extension, directly can prepare device by ion implanting；Simultaneously because eliminate epitaxy technique, and then reduce preparation difficulty, save preparation cost and time, very big must save resource and the energy.
Accompanying drawing explanation
Fig. 1 is existing trench gate carborundum insulated gate bipolar transistor structure chart；
Fig. 2 is the flow chart that the present invention prepares Fig. 1 device；
Fig. 3 is the process schematic representation that the present invention prepares Fig. 1 device.
Detailed description of the invention
Equipment used in the present invention mainly has thermal oxidation furnace, ion implantation apparatus, magnetic control sputtering device, polysilicon deposition apparatus.
As it is shown in figure 1, the trench gate carborundum insulated gate bipolar transistor that the present invention is to be prepared, its structure includes p-type SiC substrate 1, N well region 2, N+Body contact area 3, launch site 4, trench gate oxide layer 5, polysilicon groove grid 6, cushion 7, collecting zone 8, SiO2Side wall 9, titanium coating 10, nickel metal layer 11.Wherein, p-type SiC substrate 1 is lightly doped substrate, the top of p-type SiC substrate 1 is N well region 2, the upper left corner of N well region 2 and Shi Ti contact area, the upper right corner 3, the central region of N well region 2 is polysilicon groove grid 6, and trench gate oxide layer 5 is wrapped in bottom and the sidewall of polysilicon groove grid 6, launch site 4 is positioned at substrate top, is clipped in polysilicon groove grid 6 the right and left, collecting zone 8 is positioned at the bottom of substrate, and cushion 7 is positioned at the top of collecting zone 8, SiO2Side wall 9 is positioned at the left and right sides of polysilicon groove grid 6 the top, and titanium coating 10 lays respectively at N+Body contact area 3, launch site 4, the top of polysilicon groove grid 6, nickel metal layer 11 lays respectively at the lower section of collecting zone 8 and the top of titanium coating 10.
The present invention prepares the method for described trench gate carborundum insulated gate bipolar transistor, provides following three kinds of embodiments:
Embodiment 1: be 10 in base plane dislocation4/cm-3, substrate concentration be 3 × 1014cm-3Zero micro-tubular structure p-type SiC substrate on, prepare trench gate carborundum insulated gate bipolar transistor.
With reference to Fig. 2 and Fig. 3, the present embodiment to realize step as follows:
Step 1: substrate processing.
Selecting base plane dislocation is 104/cm-3, substrate concentration be 3 × 1014cm-3Zero micro-tubular structure p-type SiC substrate, along this p-type SiC substrate 1 the back side cut make it be thinned to 100 μm；After facet is polished, wet-oxygen oxidation 20 minutes at 950 DEG C, then remove removing oxide layer, recover facet structure and flatness.
Step 2:N trap ion implanting.
(2.1) low pressure chemical vapor deposition mode is used to deposit, in the p-type SiC substrate front after above-mentioned process, the SiO that a layer thickness is 0.1 μm2, then the Al that deposition thickness is 1 μm is as the barrier layer of N~+ implantation, gluing makes N trap injection region window by lithography；
(2.2) N trap injection region window is carried out twice ion implanting: at 650 DEG C, first use the Implantation Energy of 300Kev, 1.5 × 1012cm-2Implantation dosage carry out a N~+ implantation, then use the Implantation Energy of 200Kev, 8 × 1011cm-2Implantation dosage carry out secondary N~+ implantation, form N well region 2, such as a in Fig. 3.
Step 3: body contact area ion implanting.
Complete the p-type SiC substrate front gluing of above-mentioned technique, making the upper left corner and the upper right corner window of N well region 2 by lithography, use Nitrogen ion to carry out a heavy doping N the two window+Ion implanting, implantation dosage is 9 × 1013cm-2, Implantation Energy is 150Kev, forms body contact area 3, such as b in Fig. 3.
Step 4:P well region ion implanting.
(4.1) p-type SiC substrate front gluing in occlusion body contact area, make the zone line window of N well region 2 by lithography, this window carries out a P with aluminium ion+Ion implanting, implantation dosage 3 × 1014cm-2, Implantation Energy is 150Kev, forms p-well region, such as c in Fig. 3；
(4.2) Al and SiO of p-type SiC substrate front deposit is removed2。
Step 5: etching groove.
(5.1) low pressure chemical phase method is used to deposit the SiO that a layer thickness is 0.2 μm on the whole front through the p-type SiC substrate of multistep ion implanting2Layer；
(5.2) at above-mentioned SiO2Magnetron sputtering one layer on layerTi film as ICP etch mask, then gluing, make trench openings by lithography, carry out ICP etching until below N well region, form the groove through p-well region, such as d in Fig. 3；Finally removing photoresist, remove etch mask and clean, the process conditions of ICP etching are: ICP coil power 850W, source power 100W, reacting gas SF6And O2It is respectively 48sccm and 12sccm.
(5.3) through the etching groove of p-well region, p-well region is divided into left and right two parts, with these left and right two parts as launch site 4.
Step 6: the growth of trench gate oxide layer.
At 1200 DEG C, the p-type SiC substrate front completing etching groove is carried out dry-oxygen oxidation 2 hours, form, at channel bottom and sidewall, the trench gate oxide layer 5 that thickness is 40nm；Then at the N of 1050 DEG C2Anneal under atmosphere, reduce SiO2The roughness of film surface, such as e in Fig. 3.
Step 7: trench polysilicon silicon deposit.
There is the front of the p-type SiC substrate of trench gate oxide layer 5 in growth, use low pressure hot wall chemical vapor deposition method growing polycrystalline silicon so that it is fill up groove, such as f in Fig. 3；Then gluing photoetching, etches polycrystalline silicon layer, form polysilicon groove grid；Finally removing photoresist, clean, wherein, the process conditions of growing polycrystalline silicon are: ambient temperature is 650 DEG C,
Deposit pressure is 80Pa, and reacting gas is silane and hydrogen phosphide, and carrier gas is helium.
Step 8: cushion ion implanting.
P is carried out at the back side of p-type SiC substrate+Ion implanting, implantation dosage is 4 × 1012cm-2, Implantation Energy is 400Kev, forms cushion 7, such as g in Fig. 3.
Step 9: collector area ion implanting.
N is carried out at the p-type surface on back side of SiC substrate Nitrogen ion containing cushion+Ion implanting, implantation dosage is 4 × 1013cm-2, Implantation Energy is 200Kev, forms collector area 8, such as g in Fig. 3.
Step 10: above-mentioned prepared p-type SiC substrate being placed in the ar gas environment of 1700 DEG C, carries out high annealing, the time is 15 minutes, activates implanted dopant.
Step 11: prepare emitter stage and grid in substrate face.
(11.1) in the front gluing photoetching of aforementioned p-type SiC substrate, the SiO of groove grid is etched2Side wall 9, such as h in Fig. 3；
(11.2) using magnetron sputtering method p-type SiC substrate front after etching side wall 9 to deposit titanium coating and nickel metal layer 11 successively, wherein, titanium coating thickness is 50nm, and nickel metal layer thickness is 150nm；Gluing, development the most on the metal layer, carries out metal erosion and forms emitter stage and grid, then remove photoresist, clean, such as i in Fig. 3.
Step 12: prepare colelctor electrode at substrate back.
It is 1 μm nickel metal layer at the p-type surface on back side of SiC substrate deposition thickness completing grid and prepared by emitter stage, draws colelctor electrode, such as i in Fig. 3；
Step 13: will complete substrate metal sintering 4 minutes at a temperature of 900 DEG C after above-mentioned steps, to complete element manufacturing.
Embodiment 2: be 10 in base plane dislocation4/cm-3, substrate concentration be 6 × 1014cm-3The SiC substrate of p-type without micro-tubular structure on, prepare trench gate carborundum insulated gate bipolar transistor.
With reference to Fig. 2 and Fig. 3, the present embodiment to realize step as follows:
Step A: substrate processing.
This step is identical with the step 1 of embodiment 1.
Step B:N trap ion implanting.
(b1) this step is identical with the step of embodiment 1 (2.1)；
(b2) N trap injection region window is carried out twice ion implanting: at 650 DEG C, first use the Implantation Energy of 500Kev, 4.5 × 1012cm-2Implantation dosage carry out a N~+ implantation, then use the Implantation Energy of 350Kev, 1 × 1012cm-2Implantation dosage carry out secondary N~+ implantation, form N well region 2, such as a in Fig. 3.
Step C: complete the p-type SiC substrate front gluing of above-mentioned technique, makes N well region 2 upper left corner and upper right corner window by lithography, uses Nitrogen ion to carry out a heavy doping N the two window+Ion implanting, implantation dosage is 3 × 1014cm-2, Implantation Energy is 250Kev, forms body contact area 3, such as b in Fig. 3.
Step D: p-type SiC substrate front gluing in occlusion body contact area, make the window of N well region 2 zone line by lithography, carries out a P with aluminium ion on this window+Ion implanting, implantation dosage 6 × 1014cm-2, Implantation Energy is 220Kev, forms p-well region, such as c in Fig. 3；Then remove except Al and SiO of p-type SiC substrate front deposit2Barrier layer.
Step E: etching groove.
This step is identical with the step 5 of embodiment 1.
Step F: at 1200 DEG C, carries out dry-oxygen oxidation 3 hours to the p-type SiC substrate front completing etching groove, forms, at channel bottom and sidewall, the trench gate oxide layer 5 that thickness is 60nm；Then at the N of 1050 DEG C2Anneal under atmosphere, reduce SiO2The roughness of film surface, such as e in Fig. 3.
Step G: trench polysilicon silicon deposit.
This step is identical with the step 7 of embodiment 1.
Step H: carry out P at the back side of p-type SiC substrate+Ion implanting, implantation dosage is 8 × 1012cm-2, Implantation Energy is 500Kev, forms cushion 7, such as g in Fig. 3.
Step I: carry out N at the p-type surface on back side of SiC substrate nitrogen containing cushion+Ion implanting, implantation dosage is 8 × 1013cm-2, Implantation Energy is 250Kev, forms collector area 8, such as g in Fig. 3.
Step J: above-mentioned prepared p-type SiC substrate being placed in the ar gas environment of 1700 DEG C, carries out high annealing, the time is 10 minutes, activates implanted dopant.
Step K: prepare emitter stage and grid in substrate face.
This step is identical with the step 11 of embodiment 1.
Step L: prepare colelctor electrode at substrate back.
This step is identical with the step 12 of embodiment 1.
Step M: will complete substrate metal sintering 11 minutes at a temperature of 900 DEG C after above-mentioned steps, to complete element manufacturing.
Embodiment 3: be 10 in base plane dislocation4/cm-3, substrate concentration be 8 × 1014cm-3The SiC substrate of p-type without micro-tubular structure on, prepare trench gate carborundum insulated gate bipolar transistor.
With reference to Fig. 2 and Fig. 3, the present embodiment to realize step as follows:
The first step: substrate processing.
This step is identical with the step 1 of embodiment 1.
Second step: using low pressure chemical vapor deposition mode to deposit Al that a layer thickness the is 1.2 μm barrier layer as N~+ implantation in the p-type SiC substrate front through above-mentioned process, gluing makes N trap injection region window by lithography；At 650 DEG C, N well region window is carried out twice ion implanting, the most first with the Implantation Energy of 700Kev, 7.5 × 1012cm-2Implantation dosage carry out a N~+ implantation, then with the Implantation Energy of 450Kev, 4 × 1012cm-2Implantation dosage carry out secondary N~+ implantation, form N well region 2, such as a in Fig. 3.
3rd step: complete the p-type SiC substrate front gluing of above-mentioned technique, makes the upper left corner and the upper right corner window of N well region 2 by lithography, uses Nitrogen ion to carry out a heavy doping N the two window+Ion implanting, implantation dosage is 7 × 1014cm-2, Implantation Energy is 300Kev, forms body contact area 3, such as b in Fig. 3.
4th step: p-type SiC substrate front gluing in occlusion body contact area, make the zone line window of N well region 2 by lithography, on this window with aluminium ion carry out energy be 300Kev, dosage 1 × 1015cm-2A P+Ion implanting, forms p-well region 4；Then the Al barrier layer of p-type SiC substrate front deposit is removed, such as c in Fig. 3.
5th step: etching groove.
This step is identical with the step 5 of embodiment 1.
6th step: at 1200 DEG C, carries out dry-oxygen oxidation 4 hours to the p-type SiC substrate front completing etching groove, forms, at channel bottom and sidewall, the trench gate oxide layer 5 that thickness is 75nm；Then at the N of 1050 DEG C2Anneal under atmosphere, reduce SiO2The roughness of film surface, such as e in Fig. 3.
7th step: trench polysilicon silicon deposit.
This step is identical with the step 7 of embodiment 1.
8th step: it is 3 × 10 that the back side aluminium ion in p-type SiC substrate carries out dosage13cm-2, energy be the P of 600Kev+Ion implanting, forms cushion 7, such as g in Fig. 3.
9th step: carrying out dosage at the p-type surface on back side of SiC substrate Nitrogen ion containing cushion is 2 × 1014cm-2, energy be the N of 350Kev+Ion implanting, forms collector area 8, such as g in Fig. 3.
Tenth step: the p-type SiC substrate after above-mentioned steps is placed in the ar gas environment of 1700 DEG C, carries out high annealing, and the time is 8 minutes, activates implanted dopant.
11st step: prepare emitter stage and grid in substrate face.
This step is identical with the step 11 of embodiment 1.
12nd step: prepare colelctor electrode at substrate back.
This step is identical with the step 12 of embodiment 1.
13rd step: will complete substrate metal sintering 7 minutes at a temperature of 900 DEG C after above-mentioned steps, to complete element manufacturing.
Claims (3)
1. a preparation method for trench gate carborundum insulated gate bipolar transistor, comprises the following steps:
(1) selecting the p-type SiC substrate of zero micro-pipe, its base plane dislocation is 104/cm-3, substrate concentration is
3×1014～8 × 1014cm-3, the back side along this p-type SiC substrate is cut so that it is be thinned to 100 μm, then to facet successively
It is polished, aoxidizes and remove removing oxide layer；
(2) the p-type SiC substrate front Nitrogen ion at described zero micro-pipe carries out twice N trap ion implanting: note for the first time
Entering dosage is 1.5 × 1012cm-2～7.5 × 1012cm-2, Implantation Energy is 300～700Kev；Implantation dosage for the second time
8×1011cm-2～4 × 1012cm-2Implantation Energy is 200～450Kev, forms N well region；
(3) in N well region upper left side and top-right region, heavy doping N is carried out with Nitrogen ion+Ion implanting: implantation dosage
It is 9 × 1013～7 × 1014cm-2, Implantation Energy is 150～300Kev, forms body contact area；
(4) ion implanting is carried out at territory, N well region upper middle zone Al ion: implantation dosage is
3×1014cm-2～1 × 1015cm-2, Implantation Energy is 150～300Kev, forms p-well region；
(5) depositing a layer thickness in the p-type SiC substrate of whole zero micro-pipe is the SiO of 0.2um2, on p-well region
Zone line lithographic trenches window, and this window bottom SiC substrate is carried out etching groove, until groove is positioned under N trap
Side, makes p-well region be spaced as left and right two parts, and these left and right two parts become launch site；
(6) bottom and sidewall to the above-mentioned groove etched aoxidize, and form trench gate oxide layer；
(7) in the long groove having trench gate oxide layer, low pressure hot wall chemical vapor deposition method growing polycrystalline silicon is used, until
Polysilicon fills up groove, and its deposition temperature is 650 DEG C, and deposit pressure is 80Pa, and reacting gas is silane and hydrogen phosphide, carries
Fortune body is helium；
(8) back side aluminium ion in the p-type SiC substrate of described zero micro-pipe carries out ion implanting, and implantation dosage is
4×1012cm-2～3 × 1013cm-2, Implantation Energy is 400～600Kev, forms p-type cushion；
(9) N is carried out at the p-type surface on back side of SiC substrate Nitrogen ion containing p-type cushion+Ion implanting, implantation dosage is
4×1013～2 × 1014cm-2, Implantation Energy is 200～350Kev, forms collecting zone；
(10) the p-type SiC substrate of described zero micro-pipe is placed at 1700 DEG C carries out high annealing 8～15 minutes, activate institute
There is implanted dopant；
(11) the p-type SiC substrate front at described zero micro-pipe etches the side wall of polysilicon gate, then in this substrate face
On deposit titanium coating and nickel metal layer successively, go forward side by side row metal photoetching and etching, draw emitter stage and grid；
(12) it is 1 μm nickel metal layer at aforementioned p-type surface on back side of SiC substrate deposition thickness, draws colelctor electrode；
(13) by completing the substrate after above-mentioned steps metal sintering 4～7 minutes at a temperature of 900 DEG C, element manufacturing is completed.
The preparation method of trench gate carborundum insulated gate bipolar transistor the most according to claim 1, its feature exists
Etching groove in described step (5), its process conditions are: ICP coil power 850W, source power 100W, reaction
Gas SF6And O2Flow is respectively 48sccm and 12sccm.
The preparation method of trench gate carborundum insulated gate bipolar transistor the most according to claim 1, it is characterised in that
Trench gate oxide layer growth in described step (6), its process conditions are: temperature is 1200 DEG C, and the time is 2～4 hours.
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| CN111490098A (en) * | 2020-04-17 | 2020-08-04 | 重庆伟特森电子科技有限公司 | Groove type SiC IGBT structure and preparation method thereof |
| CN113270492A (en) * | 2021-05-13 | 2021-08-17 | 重庆邮电大学 | Trench type GaN insulated gate bipolar transistor |
| CN113189637A (en) * | 2021-06-07 | 2021-07-30 | 杭州电子科技大学 | Silicon carbide neutron detector based on double-sided T-shaped grooves |
| CN113838756B (en) * | 2021-09-24 | 2024-08-16 | 南瑞联研半导体有限责任公司 | Device manufacturing method for improving Trench-IGBT wafer micro-deformation |
| CN116666211A (en) * | 2022-02-21 | 2023-08-29 | 珠海零边界集成电路有限公司 | Insulated gate bipolar transistor, manufacturing method thereof, electronic equipment and storage medium |
| CN116666210A (en) * | 2022-02-21 | 2023-08-29 | 珠海零边界集成电路有限公司 | Insulated gate bipolar transistor, manufacturing method thereof, electronic equipment and storage medium |
| CN114975602B (en) * | 2022-07-29 | 2022-11-08 | 深圳芯能半导体技术有限公司 | High-reliability IGBT chip and manufacturing method thereof |
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