CN103928320B - The preparation method of trench gate carborundum insulated gate bipolar transistor - Google Patents

Abstract

The invention discloses a method for preparing a trench gate silicon carbide insulated gate bipolar transistor, which mainly solves the problem of high manufacturing cost of the current silicon carbide insulated gate bipolar transistor. The implementation steps include: 1. Selecting a P-type silicon carbide substrate with excellent structural performance, cutting and thinning the back of the substrate and polishing the oxidized cut surface; ⁺ body contact region, P well region; 3. Etch a trench on the front of the substrate, then grow a trench gate oxide layer, and deposit polysilicon to fill the trench with polysilicon; 4. Ion implantation on the back of the substrate Buffer layer and collector area; 5. High temperature annealing, activation of implanted impurities; 6. Preparation of device electrodes. Compared with the existing method, the present invention does not require epitaxial growth of an excessively thick voltage-resistant layer, saves a lot of production costs, simplifies the process steps, and can be used in the fields of inverters, switching power supplies and lighting circuits.

Description

Fabrication method of trench gate silicon carbide insulated gate bipolar transistor

technical field

The invention belongs to the field of microelectronic technology, and relates to a method for preparing a semiconductor device, in particular to a trench gate structure SiC IGBT using a substrate as a voltage-resistant layer, which can be widely used in frequency converters, inverters, switching power supplies, and lighting circuits and motor fields.

technical background

Silicon carbide insulated gate bipolar transistor, or SiC IGBT, is a new type of high-voltage resistant device developed based on silicon carbide materials. At present, the mainstream solid-state device used in the field of power electronics is Si IGBT, and its turn-off voltage is 0.6-6.5kV. After 30 years of development, Si IGBT has reached the limit of performance and device structure. With the development of new applications such as electric vehicles, photovoltaic and wind energy green energy, and smart grids, a new leap in the performance of power electronic devices is required. The breakthrough of SiC wide bandgap semiconductor material with low micropipe defect density has made a new generation of power electronic devices possible. The wide bandgap material structure leads to the improvement of the performance of semiconductor devices such as low leakage, high operating temperature and radiation resistance. The wide bandgap semiconductor SiC has a critical breakdown electric field an order of magnitude higher than Si, which means that the off-drift layer of SiC power electronic devices can be thinner and have higher doping concentration, resulting in SiC having a lower energy efficiency than Si equivalent devices. An order of magnitude on-resistance; higher carrier saturation velocity leads to higher operating frequency; higher thermal conductivity will improve heat dissipation, allowing the device to work at higher power densities.

In the mid-1990s, a new concept was proposed, that is, the IGBT uses a U-shaped trench gate structure, which uses the silicon dry etching technology borrowed from the large-scale integration process. In the trench gate IGBT, the gate voltage forms an electron accumulation layer in the drift region, which enhances the electron injection in the PIN diode and increases the carrier concentration on the surface. However, the "T"-shaped conductive path of the MOS structure in the original IGBT is shortened to two parallel vertical conductive paths, and the channel changes from horizontal to vertical, resulting in a decrease in cell area, thereby increasing the channel area per unit device area. , thereby reducing the channel resistance; and the groove gate eliminates the JFET effect, and there will be no current "bottleneck" area. Therefore, compared with the planar gate IGBT, the trench gate IGBT can greatly reduce the on-state voltage drop, thereby achieving a better compromise between the on-state voltage drop and the turn-off energy. In addition, relative to the PNP transistor current, the increase in the proportion of the PIN diode current can effectively suppress the latching effect, so the trench gate IGBT has a larger SOA safe operating area than the planar gate IGBT.

The process steps of the traditional trench gate SiC IGBT are as follows: first grow a buffer layer on the silicon surface of the substrate; then grow a 50-200 μm thick epitaxial withstand voltage layer on the buffer layer; then form a well on the withstand voltage layer by ion implantation region, emitter region and heavily doped body contact region; then etch trenches on the front side of the substrate, grow a trench gate oxide layer, and deposit polysilicon trench gates; finally deposit and lithography the metal contacts of devices. There are two disadvantages in this method: the one is that the preparation cost is high. For example, SiC epitaxial equipment is expensive, and the epitaxial process consumes a lot of energy. Second, it is difficult to grow thicker SiC epitaxial layers. Such a top silicon carbide device company can only do it. Therefore, the technical bottleneck problem limits the popularization and application of high-power SiC IGBT.

Contents of the invention

The purpose of the present invention is to propose a novel preparation method of trench-gate silicon carbide insulated gate bipolar transistors, so as to solve the problems of high preparation cost and difficult process in the prior art, and realize the popularization and application of high-power SiC IGBTs.

Technical scheme of the present invention comprises the following steps:

(1) Select a P-type SiC substrate with zero micropipes, its basal plane dislocation is 10 ⁴ /cm ^-3 , and the substrate concentration is 3×10 ¹⁴ to 8×10 ¹⁴ cm ^-3 , along the P-type SiC substrate The backside of the bottom is cut to make it thinner to 100μm, and then the cut surface is polished, oxidized and the oxide layer is removed in sequence;

(2) Perform two N-well ion implantations with nitrogen ions on the front side of the P-type SiC substrate of the zero micropipe: the first implantation dose is 1.5×10 ¹² cm ^-2 to 7.5×10 ¹² cm ^-2 , and the implanted The energy is 300-700Kev; the second implant dose is 8×10 ¹¹ cm ^-2 to 4×10 ¹² cm ^-2 and the energy is 200-450Kev to form an N well region;

(3) In the upper left and upper right regions of the N well region, heavily doped N ⁺ ion implantation with nitrogen ions: the implantation dose is 9×10 ¹³ ~7×10 ¹⁴ cm ^-2 , and the implantation energy is 150~300Kev, form a body contact zone;

(4) Perform ion implantation with Al ions in the upper middle region of the N well region: the implantation dose is 3×10 ¹⁴ cm ^-2 to 1×10 ¹⁵ cm ^-2 , and the implantation energy is 150 to 300Kev to form the P well region;

(5) Deposit a layer of SiO ₂ with a thickness of 0.2um on the entire P-type SiC substrate with zero micropipes, photoetch the trench window in the middle area above the P well region, and conduct the SiC substrate under the window The groove is etched until the groove is located under the N well, so that the P well region is separated into left and right parts, and the left and right parts become the emission region;

(6) Oxidizing the bottom and sidewalls of the etched trench to form a trench gate oxide layer;

(7) growing polysilicon in the trench with the trench gate oxide layer by low-pressure hot-wall chemical vapor deposition until the polysilicon fills the trench;

(8) performing ion implantation with aluminum ions on the backside of the P-type SiC substrate with zero micropipes, the implantation dose is 4×10 ¹² cm ^-2 to 3×10 ¹³ cm ^-2 , and the implantation energy is 400-600Kev, Forming a P-type buffer layer;

(9) Perform N ⁺ ion implantation with nitrogen ions on the back of the P-type SiC substrate, the implantation dose is 4×10 ¹³ to 2×10 ¹⁴ cm ^-2 , and the implantation energy is 200 to 350Kev to form a collector region;

(10) placing the P-type SiC substrate with zero micropipes at 1700° C. for high-temperature annealing for 8 to 15 minutes to activate all implanted impurities;

(11) Etch the sidewall of the polysilicon gate on the front side of the P-type SiC substrate of the zero micropipe, then deposit a titanium metal layer and a nickel metal layer on the front side of the substrate in sequence, and carry out metal photolithography and etching Erosion, leading to the emitter and gate;

(12) Deposit a nickel metal layer with a thickness of 1 μm on the back of the above-mentioned P-type SiC substrate, and lead out the collector;

(13) Metal sintering the substrate after the above steps at a temperature of 900° C. for 4 to 7 minutes to complete device fabrication.

In the present invention, because the P-type SiC substrate without micropipe structure is used to prepare the trench gate IGBT device, the device can be prepared directly by ion implantation without epitaxy; at the same time, because the epitaxy process is omitted, the preparation difficulty is further reduced, and the preparation cost is saved. Cost and time are greatly saved in resources and energy.

Description of drawings

FIG. 1 is a structural diagram of an existing trench gate silicon carbide insulated gate bipolar transistor;

Fig. 2 is the flow chart of the present invention preparation Fig. 1 device;

Fig. 3 is a schematic diagram of the process for preparing the device of Fig. 1 according to the present invention.

detailed description

The equipment used in the present invention mainly includes a thermal oxidation furnace, an ion implanter, a magnetron sputtering apparatus, and polysilicon deposition equipment.

As shown in Figure 1, the trench gate silicon carbide insulated gate bipolar transistor to be prepared in the present invention has a structure comprising a P-type SiC substrate 1, an N well region 2, an N ⁺ body contact region 3, an emitter region 4, a trench Groove gate oxide layer 5, polysilicon groove gate 6, buffer layer 7, collector region 8, SiO ₂ spacer 9, titanium metal layer 10, nickel metal layer 11. Among them, the P-type SiC substrate 1 is a lightly doped substrate, the top of the P-type SiC substrate 1 is the N well region 2, the upper left corner and the upper right corner of the N well region 2 are the body contact region 3, and the N well region 2 The middle area of the polysilicon trench gate 6 is the polysilicon trench gate 6, the trench gate oxide layer 5 wraps the bottom and side walls of the polysilicon trench gate 6, the emitter region 4 is located on the upper part of the substrate, and is sandwiched between the left and right sides of the polysilicon trench gate 6, and the collector region 8 is located on the substrate. At the bottom of the bottom, the buffer layer 7 is located above the collector region 8, the SiO ₂ sidewall 9 is located on the left and right sides of the uppermost polysilicon trench gate 6, and the titanium metal layer 10 is respectively located in the N ⁺ body contact region 3, emitter region 4, Above the polysilicon trench gate 6 , the nickel metal layer 11 is respectively located below the collector region 8 and above the titanium metal layer 10 .

The method for preparing the trench gate silicon carbide insulated gate bipolar transistor of the present invention provides the following three embodiments:

Example 1: On a P-type SiC substrate with a zero micropipe structure with a basal plane dislocation of 10 ⁴ /cm ^-3 and a substrate concentration of 3×10 ¹⁴ cm ^-3 , a trench gate silicon carbide insulated gate bipolar was prepared type transistor.

With reference to Fig. 2 and Fig. 3, the implementation steps of the present embodiment are as follows:

Step 1: Substrate processing.

Select a P-type SiC substrate with zero micropipe structure with a basal plane dislocation of 10 ⁴ /cm ^-3 and a substrate concentration of 3×10 ¹⁴ cm ^-3 , cut along the back surface of the P-type SiC substrate 1 to make it thinner to 100 μm; after polishing the cutting surface, wet oxygen oxidation at 950°C for 20 minutes, then remove the oxide layer, and restore the structure and flatness of the cutting surface.

Step 2: N well ion implantation.

(2.1) Deposit a layer of SiO ₂ with a thickness of 0.1 μm on the front of the P-type SiC substrate after the above treatment by low-pressure chemical vapor deposition, and then deposit Al with a thickness of 1 μm as a barrier layer for nitrogen ion implantation , the window of the N well implantation region is etched out by photolithography;

(2.2) Perform two ion implantations on the window of the N well implantation region: at 650°C, first perform a nitrogen ion implantation with an implantation energy of 300Kev and an implantation dose of 1.5×10 ¹² cm ^-2 , and then use an implantation energy of 200Kev, The implantation dose of 8×10 ¹¹ cm ^-2 is implanted with nitrogen ions twice to form the N well region 2, as shown in Fig. 3 a.

Step 3: Ion implantation in the body contact region.

Glue is applied on the front side of the P-type SiC substrate after the above process, and the upper left and upper right windows of the N well region 2 are photoetched, and nitrogen ions are used to perform a heavily doped N ⁺ ion implantation on these two windows, and the implantation dose is 9×10 ¹³ cm ^-2 , the implantation energy is 150Kev, forming a body contact region 3, as shown in b in Fig. 3 .

Step 4: Ion implantation in the P well region.

(4.1) Apply glue on the front side of the P-type SiC substrate including the body contact region, and photoetch the middle region window of the N well region 2, and perform a P ⁺ ion implantation on the window with an implantation dose of 3×10 ¹⁴ cm ^-2 , the implantation energy is 150Kev to form a P well region, as shown in c in Figure 3;

(4.2) Removing Al and SiO ₂ deposited on the front side of the P-type SiC substrate.

Step 5: Trench etching.

(5.1) Deposit a _SiO2 layer with a thickness of 0.2 μm on the entire front surface of the P-type SiC substrate after multi-step ion implantation by low-pressure chemical vapor method;

(5.2) Magnetron sputtering a layer on the above _SiO2 layer The Ti film is used as an ICP etching mask, and then the glue is applied, and the trench window is etched by photolithography, and the ICP etching is carried out until the bottom of the N well region to form a trench passing through the P well region, as shown in Figure 3 d; finally, the glue is removed , remove the etching mask and clean, the process conditions of ICP etching are: ICP coil power 850W, source power 100W, reaction gas SF ₆ and O ₂ are 48sccm and 12sccm respectively.

(5.3) Through the etched groove of the P well region, the P well region is divided into left and right parts, and the left and right parts are used as the emission region 4 .

Step 6: Growth of the trench gate oxide layer.

At 1200°C, perform dry oxygen oxidation on the front side of the P-type SiC substrate after trench etching for 2 hours, and form a trench gate oxide layer 5 with a thickness of 40nm on the bottom and side walls of the trench; then at 1050°C Annealing is performed under N ₂ atmosphere to reduce the roughness of the SiO ₂ film surface, as shown in Figure 3 e.

Step 7: Trench polysilicon deposition.

On the front side of the P-type SiC substrate with the trench gate oxide layer 5 grown, polysilicon is grown by the low-pressure hot-wall chemical vapor deposition method to fill the trench, as shown in Fig. 3 f; Etching the polysilicon layer to form a polysilicon groove gate; finally removing glue and cleaning, wherein the process conditions for growing polysilicon are: the ambient temperature is 650°C,

The deposition pressure is 80Pa, the reaction gas is silane and phosphine, and the carrier gas is helium.

Step 8: Buffer layer ion implantation.

Perform P ⁺ ion implantation on the back of the P-type SiC substrate with an implant dose of 4×10 ¹² cm ^-2 and an implant energy of 400Kev to form a buffer layer 7 , as shown in g in FIG. 3 .

Step 9: Ion implantation in the collector region.

Nitrogen ions were used to implant N ⁺ ions on the back of the P-type SiC substrate containing the buffer layer. The implant dose was 4×10 ¹³ cm ^-2 , and the implant energy was 200Kev to form the collector region 8 , as shown in g in FIG. 3 .

Step 10: Put the above-prepared P-type SiC substrate in an argon environment at 1700° C., perform high-temperature annealing for 15 minutes, and activate the implanted impurities.

Step 11: Prepare emitter and gate on the front side of the substrate.

(11.1) Apply photolithography on the front side of the above-mentioned P-type SiC substrate, and etch out the _SiO2 sidewall 9 of the groove gate, as shown in Figure 3 h;

(11.2) Deposit a titanium metal layer and a nickel metal layer 11 sequentially on the front side of the P-type SiC substrate after the sidewall 9 has been etched by magnetron sputtering, wherein the thickness of the titanium metal layer is 50 nm, and the thickness of the nickel metal layer is 150nm; then apply glue on the metal layer, develop it, perform metal corrosion to form the emitter and grid, and then remove the glue and clean it, as shown in Figure 3 i.

Step 12: Prepare a collector on the back of the substrate.

Deposit a nickel metal layer with a thickness of 1 μm on the back of the P-type SiC substrate that has completed the gate and emitter preparations, and lead out the collector, as shown in Figure 3 i;

Step 13: Sinter the substrate after the above steps at a temperature of 900° C. for 4 minutes to complete the fabrication of the device.

Example 2: On a P-type SiC substrate without a micropipe structure with a basal plane dislocation of 10 ⁴ /cm ^-3 and a substrate concentration of 6×10 ¹⁴ cm ^-3 , a trench gate silicon carbide insulated gate double polar transistor.

With reference to Fig. 2 and Fig. 3, the implementation steps of the present embodiment are as follows:

Step A: Substrate treatment.

This step is the same as Step 1 of Example 1.

Step B: N well ion implantation.

(b1) This step is the same as the step (2.1) of Example 1;

(b2) Perform two ion implantations on the window of the N-well implantation region: at 650°C, first perform a nitrogen ion implantation with an implantation energy of 500Kev and an implantation dose of 4.5×10 ¹² cm ^-2 , and then use an implantation energy of 350Kev, A second nitrogen ion implantation is performed with an implantation dose of 1×10 ¹² cm ^-2 to form an N well region 2 , as shown in a in FIG. 3 .

Step C: Apply glue on the front side of the P-type SiC substrate that has completed the above process, and photoetch the windows in the upper left corner and upper right corner of the N well region 2, and perform a heavily doped N ⁺ ion implantation on these two windows using nitrogen ions. The dose is 3×10 ¹⁴ cm ^-2 , the implantation energy is 250Kev, and the body contact region 3 is formed, as shown in b in Fig. 3 .

Step D: Apply glue on the front side of the P-type SiC substrate including the body contact region, and photoetch a window in the middle area of the N well region 2, and perform a P ⁺ ion implantation on the window with an implantation dose of 6×10 ¹⁴ cm ^-2 , the implantation energy is 220Kev to form a P well region, as shown in c in Figure 3; then remove the Al and SiO ₂ barrier layer deposited on the front side of the P-type SiC substrate.

Step E: trench etching.

This step is the same as Step 5 of Example 1.

Step F: Perform dry oxygen oxidation on the front side of the P-type SiC substrate after trench etching at 1200° C. for 3 hours, and form a trench gate oxide layer 5 with a thickness of 60 nm on the bottom and side walls of the trench; Annealing was performed under N ₂ atmosphere at 1050°C to reduce the roughness of the SiO ₂ film surface, as shown in Fig. 3 e.

Step G: trench polysilicon deposition.

This step is the same as Step 7 of Example 1.

Step H: Perform P ⁺ ion implantation on the back of the P-type SiC substrate with an implant dose of 8×10 ¹² cm ^-2 and an implant energy of 500Kev to form a buffer layer 7 , as shown in g in FIG. 3 .

Step I: Implant N ⁺ ions with nitrogen on the back of the P-type SiC substrate containing the buffer layer, the implant dose is 8×10 ¹³ cm ^-2 , and the implant energy is 250Kev to form the collector region 8 , as shown in g in FIG. 3 .

Step J: placing the above-prepared P-type SiC substrate in an argon environment at 1700° C., performing high-temperature annealing for 10 minutes, and activating the implanted impurities.

Step K: preparing an emitter and a gate on the front side of the substrate.

This step is the same as Step 11 of Embodiment 1.

Step L: preparing a collector on the back of the substrate.

This step is the same as Step 12 of Embodiment 1.

Step M: Metal sintering the substrate after the above steps at a temperature of 900° C. for 11 minutes to complete device fabrication.

Example 3: On a P-type SiC substrate without a micropipe structure with a basal plane dislocation of 10 ⁴ /cm ^-3 and a substrate concentration of 8×10 ¹⁴ cm ^-3 , a trench gate silicon carbide insulated gate bipolar was prepared type transistor.

With reference to Fig. 2 and Fig. 3, the implementation steps of the present embodiment are as follows:

The first step: substrate processing.

This step is the same as Step 1 of Example 1.

Step 2: Deposit a layer of Al with a thickness of 1.2 μm on the front of the above-treated P-type SiC substrate by low-pressure chemical vapor deposition as a barrier layer for nitrogen ion implantation, and coat the N well implantation area by photolithography Window: Perform two ion implantations on the window of the N well region at 650°C, that is, first perform a nitrogen ion implantation with an implantation energy of 700Kev and an implantation dose of 7.5×10 ¹² cm ^-2 , and then use an implantation energy of 450Kev and a 4× The implantation dose of 10 ¹² cm ^-2 is implanted with nitrogen ions twice to form the N well region 2, as shown in Fig. 3a.

Step 3: Apply glue on the front of the P-type SiC substrate that has completed the above process, and photoetch the upper left and upper right windows of the N well region 2, and use nitrogen ions to perform a heavily doped N ⁺ ion implantation on these two windows , the implantation dose is 7×10 ¹⁴ cm ^-2 , and the implantation energy is 300Kev to form a body contact region 3 , as shown in b in FIG. 3 .

Step 4: Apply glue on the front side of the P-type SiC substrate including the body contact region, and photoetch the middle region window of the N well region 2, and use aluminum ions on the window with an energy of 300Kev and a dose of 1×10 ¹⁵ cm ^{- 2} to form a P well region 4; then remove the Al barrier layer deposited on the front side of the P ^- type SiC substrate, as shown in Figure 3 c.

Step 5: Trench etching.

This step is the same as Step 5 of Example 1.

Step 6: Perform dry oxygen oxidation on the front side of the P-type SiC substrate after trench etching at 1200°C for 4 hours, and form a trench gate oxide layer 5 with a thickness of 75nm on the bottom and side walls of the trench; then Annealing is performed under _N2 atmosphere at 1050 °C to reduce the roughness of the _SiO2 film surface, as shown in Fig. 3 e.

Step 7: Trench polysilicon deposition.

This step is the same as Step 7 of Example 1.

Step 8: Perform P ⁺ ion implantation with aluminum ions at a dose of 3×10 ¹³ cm ^-2 and an energy of 600Kev on the back of the P-type SiC substrate to form a buffer layer 7 , as shown in g in FIG. 3 .

Step 9: Perform N ⁺ ion implantation with nitrogen ions at a dose of 2×10 ¹⁴ cm ^-2 and an energy of 350Kev on the back of the P-type SiC substrate containing a buffer layer to form a collector region 8 , as shown in g in FIG. 3 .

Step 10: Place the P-type SiC substrate after the above steps in an argon environment at 1700° C., perform high-temperature annealing for 8 minutes, and activate the implanted impurities.

Step 11: Prepare the emitter and gate on the front side of the substrate.

This step is the same as Step 11 of Embodiment 1.

Step 12: Prepare a collector on the back of the substrate.

This step is the same as Step 12 of Embodiment 1.

Step 13: Sinter the substrate after the above steps at a temperature of 900° C. for 7 minutes to complete the fabrication of the device.

Claims (3)

1. A preparation method for a trench gate silicon carbide insulated gate bipolar transistor, comprising the following steps: (1) Select a P-type SiC substrate with zero micropipes, its basal plane dislocation is 10 ⁴ /cm ^-3 , and the substrate concentration is 3×10 ¹⁴ to 8×10 ¹⁴ cm ^-3 , along the P-type SiC substrate The backside of the bottom is cut to make it thinner to 100μm, and then the cut surface is polished, oxidized and the oxide layer is removed in sequence; (2) Perform two N-well ion implantations with nitrogen ions on the front side of the P-type SiC substrate of the zero micropipe: the first implantation dose is 1.5×10 ¹² cm ^-2 to 7.5×10 ¹² cm ^-2 , and the implanted The energy is 300-700Kev; the second implant dose is 8×10 ¹¹ cm ^-2 to 4×10 ¹² cm ^-2 and the energy is 200-450Kev to form an N well region; (3) In the upper left and upper right regions of the N well region, heavily doped N ⁺ ion implantation with nitrogen ions: the implantation dose is 9×10 ¹³ ~7×10 ¹⁴ cm ^-2 , and the implantation energy is 150~300Kev, form a body contact zone; (4) Perform ion implantation with Al ions in the upper middle region of the N well region: the implantation dose is 3×10 ¹⁴ cm ^-2 to 1×10 ¹⁵ cm ^-2 , and the implantation energy is 150 to 300Kev to form the P well region; (5) Deposit a layer of SiO ₂ with a thickness of 0.2um on the entire P-type SiC substrate with zero micropipes, photoetch the trench window in the middle area above the P well region, and conduct the SiC substrate under the window The groove is etched until the groove is located under the N well, so that the P well region is separated into left and right parts, and the left and right parts become the emission region; (6) Oxidizing the bottom and sidewalls of the etched trench to form a trench gate oxide layer; (7) Use low-pressure hot-wall chemical vapor deposition to grow polysilicon in the trench with a trench gate oxide layer until the polysilicon fills the trench. The deposition temperature is 650°C and the deposition pressure is 80Pa. The gas is silane and phosphine, and the carrier gas is helium; (8) performing ion implantation with aluminum ions on the backside of the P-type SiC substrate with zero micropipes, the implantation dose is 4×10 ¹² cm ^-2 to 3×10 ¹³ cm ^-2 , and the implantation energy is 400-600Kev, Forming a P-type buffer layer; ( ⁹ ) ^Perform N ⁺ ion implantation with nitrogen ions on the back of the P ^- type SiC substrate containing the P-type buffer layer. electrical area; (10) placing the P-type SiC substrate with zero micropipes at 1700° C. for high-temperature annealing for 8 to 15 minutes to activate all implanted impurities; (11) Etch the sidewall of the polysilicon gate on the front side of the P-type SiC substrate of the zero micropipe, then deposit a titanium metal layer and a nickel metal layer on the front side of the substrate in sequence, and carry out metal photolithography and etching Erosion, leading to the emitter and gate; (12) Deposit a nickel metal layer with a thickness of 1 μm on the back of the above-mentioned P-type SiC substrate, and lead out the collector; (13) Metal sintering the substrate after the above steps at a temperature of 900° C. for 4 to 7 minutes to complete device fabrication. 2. The preparation method of trench gate silicon carbide insulated gate bipolar transistor according to claim 1, characterized in that trench etching in the step (5), its process conditions are: ICP coil power 850W, source The power is 100W, and the flow rates of the reaction gases SF ₆ and O ₂ are 48 sccm and 12 sccm respectively. 3. The method for preparing trench gate silicon carbide insulated gate bipolar transistor according to claim 1, characterized in that the trench gate oxide layer is grown in the step (6), and the process conditions are: the temperature is 1200°C , the time is 2 to 4 hours.