CN103913874A - Array substrate, display device and manufacturing method of array substrate - Google Patents
Array substrate, display device and manufacturing method of array substrate Download PDFInfo
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- CN103913874A CN103913874A CN201310393652.1A CN201310393652A CN103913874A CN 103913874 A CN103913874 A CN 103913874A CN 201310393652 A CN201310393652 A CN 201310393652A CN 103913874 A CN103913874 A CN 103913874A
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- array base
- base palte
- data line
- pixel electrode
- nesa coating
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Abstract
The invention discloses an array substrate, a display device and a manufacturing method of an array substrate. A data line is covered with a transparent conducting film, and burrs or delamination on the data line can be wrapped. When voltage is applied to the data line, voltage difference on different pixel electrodes can be reduced.
Description
Technical field
The present invention relates to display technique field, relate in particular to the manufacture method of a kind of array base palte, display device and array base palte.
Background technology
Along with the maturation of thin film transistor (TFT) (Thin Film Transistor, TFT) technology, TFT liquid crystal display (Liquid Crystal Display, LCD) has become the flat-panel monitor of main flow.Wherein, in liquid crystal display, the structure of array base palte directly affects display quality.
Be illustrated in figure 1 the schematic diagram of existing array base palte, wherein, pixel electrode 11 is electrically connected with source electrode 12.Be illustrated in figure 2 array base palte in Fig. 1 cut-open view along B-B'.
The data line 13 of existing array base palte may have the phenomenon such as burr and layering in its forming process, the existence of those phenomenons, to cause when apply voltage on data line 13 time, between data line 13 and source electrode 12, can produce inhomogeneous electric field, may cause thus the voltage differences on different pixels electrode larger, be reflected in actual display effect and may cause TFT LCD to occur spot (Mura).
Summary of the invention
In view of this, the embodiment of the present invention provides the manufacture method of a kind of array base palte, display device and array base palte.
A kind of array base palte, described array base palte comprises:
Data line, described data line is formed on substrate;
Nesa coating, described nesa coating covers on described data line.
Adopt said structure, nesa coating can wrap the burr on data line or layering, can avoid occurring the larger problem of voltage differences on different pixels electrode when apply voltage on data line time.
Alternatively, described nesa coating directly overlays on described data line.
Because nesa coating can directly overlay on data line, therefore between nesa coating and data line, can there is no insulation course, thereby in reaching the effect of nesa coating cover data line, simplified the structure of array base palte.
Thin film transistor (TFT) in described array base palte is formed on described substrate; Wherein, described thin film transistor (TFT) comprises source electrode, drain electrode, and described drain electrode is electrically connected with described data line; Pixel electrode in described array base palte is formed on described substrate; Wherein, described pixel electrode covers on described source electrode, and described pixel electrode is electrically connected with described source electrode.
Alternatively, described nesa coating and described pixel electrode are same material.
Described nesa coating, described pixel electrode material are transparent conductive material, and described nesa coating and described pixel electrode are positioned at same layer.
The material of described nesa coating and described pixel electrode is tin indium oxide or indium zinc oxide.
A kind of display panel, comprises above-mentioned array base palte.
A kind of display device, comprises above-mentioned display panel.
A manufacture method for array base palte, comprising: on a substrate, form metal level; Described in patterning, metal level is to form data line, source electrode and drain electrode, and wherein said drain electrode is electrically connected with described data line; On described metal level, form transparency conducting layer; Described in patterning, transparency conducting layer is to form pixel electrode and to directly overlay the nesa coating on described data line.
Adopt such scheme, nesa coating is directly overlayed on data line, data line can be wrapped, when apply voltage on data line time, can reduce burr, the impact of layering on the voltage on pixel electrode on data line, thereby avoid occurring the larger problem of voltage differences on different pixels electrode.
Alternatively, described pixel electrode covers on described source electrode, and described pixel electrode is electrically connected with described source electrode.
Separately it should be noted that, because the differentiation of source electrode, drain electrode does not in the art have strict boundary, therefore in the present invention source electrode, drain that both can exchange.Adopt in the text by separately statement of source electrode, drain electrode, just for sake of clarity.
Brief description of the drawings
Fig. 1 is the schematic diagram of the array base palte in background technology;
Fig. 2 is array base palte in Fig. 1 cut-open view along B-B';
Fig. 3 is the schematic diagram of the array base palte in the embodiment of the present invention one;
Fig. 4 is array base palte in Fig. 3 cut-open view along A-A';
Fig. 5 is the schematic flow sheet of the manufacture method of the array base palte in the embodiment of the present invention two;
Fig. 6 a in the embodiment of the present invention two after step 102 is processed the schematic diagram of the array base palte that forms;
Fig. 6 b is array base palte in the 6a cut-open view along A-A';
Fig. 7 a in the embodiment of the present invention two after step 104 is processed the schematic diagram of the array base palte that forms;
Fig. 7 b is array base palte in the 7a cut-open view along A-A';
Fig. 8 a in the embodiment of the present invention two after step 105 is processed the schematic diagram of the array base palte that forms;
Fig. 8 b is array base palte in the 8a cut-open view along A-A';
Fig. 9 a in the embodiment of the present invention two after step 106 is processed the schematic diagram of the array base palte that forms;
Fig. 9 b is array base palte in the 9a cut-open view along A-A'.
Embodiment
The scheme of the embodiment of the present invention, by cover nesa coating on data line, can wrap the burr on data line or layering, when apply voltage on data line time, can reduce the voltage differences on different pixels electrode.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that.Therefore the present invention is not subject to the restriction of following public embodiment.
Embodiment mono-:
The embodiment of the present invention provides a kind of array base palte, comprise substrate, be formed on data line on this substrate, cover this data line nesa coating, be formed at least one thin film transistor (TFT) on this substrate and be formed on the pixel electrode on this substrate.Wherein, thin film transistor (TFT) comprises source electrode and drain electrode, and drain electrode is electrically connected with data line.Alternatively, pixel electrode covers on source electrode and with source electrode and is electrically connected, and nesa coating directly overlays on data line, and aforesaid substrate can be, but not limited to as glass substrate.
It should be noted that, the nesa coating in the embodiment of the present invention can cover data line, also can part cover data line, and the present invention does not limit this.
As shown in Fig. 3 (other devices are not shown), the schematic diagram of a kind of array base palte providing for the embodiment of the present invention one.This array base palte comprises nesa coating 2, drain electrode 3, source electrode 4 and the pixel electrode 5 of the data line 1 represented by dotted line, cover data line 1.Wherein, data line 13 is electrically connected with drain electrode, pixel electrode 5 parts cover on source electrode 4 (part that is source electrode 4 is covered by pixel electrode 5) and be electrically connected with source electrode 4.
As Fig. 4 (other devices are not shown) is depicted as array base palte in Fig. 3 cut-open view along A-A', comprises substrate 6, be formed on data line 1 on substrate 6, be formed on source electrode 4 on substrate 6, the nesa coating 2 of cover data line 1, be formed on substrate 6 and cover the pixel electrode 5 of source electrode 4.Wherein, nesa coating 2 is identical with the material of pixel electrode 5, be transparent conductive material, and nesa coating 2 is positioned at same layer with pixel electrode 5.Particularly, nesa coating 2 can be all tin indium oxide or indium zinc oxide with the material of pixel electrode 5.
In addition, it should be noted that, on substrate 6, also comprise sweep trace and active layer, and insulation course or passivation layer between layers, owing to not being the emphasis place of this enforcement, thus omit and describe in an embodiment, also not shown in Fig. 3, Fig. 4.
The embodiment of the present invention also provides a kind of display panel, comprises array base palte, and the concrete structure of this array base palte is identical with the structure of the array base palte in above-mentioned Fig. 3 and Fig. 4, does not repeat them here.
The embodiment of the present invention also provides a kind of display device, comprises above-mentioned display panel.
In the embodiment of the present invention, the data line of array base palte is covered by nesa coating, and the burr on data line or layering can be wrapped by nesa coating, when apply voltage on data line time, can reduce the voltage differences on different pixels electrode.
Embodiment bis-:
The method for making of array base palte is as shown in Figure 3 and Figure 4 done to concrete introduction below.
As shown in Figure 5, the schematic flow sheet of the manufacture method of a kind of array base palte providing for the embodiment of the present invention two, comprises the following steps:
Step 101: form metal level on substrate 6.
Wherein, substrate 6 can be, but not limited to as glass substrate.Alternatively, form metal level on substrate 6 before, can on substrate 6, first form sweep trace and active layer, and insulation course or passivation layer between layers, on active layer, form again metal level, certainly between active layer and metal level, can have passivation layer or insulation course, the scheme of the embodiment of the present invention does not limit this.
This step 101 is identical with the implementation procedure that forms metal level in prior art on glass substrate, exceeds introduction at this.
Step 102: patterned metal layer is to form data line 1, drain electrode 3 and source electrode 4.
In step 102, can adopt composition technique to form data line 1, drain electrode 3 and source electrode 4.Being the schematic diagram of the array base palte that forms after step 102 is processed as shown in Figure 6 a, is array base palte in the 6a cut-open view along A-A' as shown in Figure 6 b.Wherein, in Fig. 6 a, drain electrode 3 is electrically connected with data line 1.
Step 103: form transparency conducting layer on metal level.
Step 104: patterned transparent conductive layer is to form pixel electrode 5 and to directly overlay the nesa coating 2 on data line 1.
In step 104, can adopt composition technique to form pixel electrode 5 and nesa coating 2.Being the schematic diagram of the array base palte that forms after step 104 is processed as shown in Figure 7a, is array base palte in the 7a cut-open view along A-A' as shown in Figure 7b.From Fig. 7 a, can find out, pixel electrode 5 parts cover on source electrode 4 and with source electrode 4 and are electrically connected.
Step 105: form passivation layer 7 on transparency conducting layer.
As Fig. 8 a, 8b is depicted as the schematic diagram of the array base palte that forms after step 105 is processed, and is array base palte in the 8a cut-open view along A-A' as shown in Figure 8 b.
Step 106: form public electrode 8 on passivation layer 7.
As Fig. 9 a is depicted as the schematic diagram of the array base palte that formed after step 106 is processed, as Fig. 9 b is depicted as array base palte in the 9a cut-open view along A-A'.
In the present embodiment, nesa coating 2 is identical with the material of pixel electrode 5, be transparent conductive material.Particularly, nesa coating 2 can be tin indium oxide or indium zinc oxide with the material of pixel electrode 5.
The embodiment of the present invention also provides a kind of manufacture method of display panel, comprises the manufacture method of above-mentioned array base palte.
The embodiment of the present invention also provides a kind of manufacture method of display device, comprises the manufacture method of above-mentioned display panel.
The scheme of the embodiment of the present invention, by cover nesa coating on data line, can wrap the burr on data line, when apply voltage on data line time, can reduce the voltage differences on different pixels electrode.
Although described the preferred embodiments of the present invention, once those skilled in the art obtain the basic creative concept of cicada, can make other change and amendment to these embodiment.So claims are intended to be interpreted as comprising preferred embodiment and fall into all changes and the amendment of the scope of the invention.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if these amendments of the present invention and within modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (10)
1. an array base palte, is characterized in that, described array base palte comprises:
Data line, described data line is formed on substrate;
Nesa coating, described nesa coating covers on described data line.
2. array base palte as claimed in claim 1, is characterized in that, described nesa coating directly overlays on described data line.
3. array base palte as claimed in claim 1, is characterized in that,
Thin film transistor (TFT) in described array base palte is formed on described substrate; Wherein, described thin film transistor (TFT) comprises source electrode, drain electrode, and described drain electrode is electrically connected with described data line;
Pixel electrode in described array base palte is formed on described substrate; Wherein, described pixel electrode covers on described source electrode, and described pixel electrode is electrically connected with described source electrode.
4. array base palte as claimed in claim 3, is characterized in that, described nesa coating and described pixel electrode are same material.
5. array base palte as claimed in claim 4, is characterized in that, described nesa coating, described pixel electrode material are transparent conductive material, and described nesa coating and described pixel electrode are positioned at same layer.
6. array base palte as claimed in claim 4, is characterized in that, the material of described nesa coating and described pixel electrode is tin indium oxide or indium zinc oxide.
7. a display panel, is characterized in that, comprises the arbitrary described array base palte of claim 1～6.
8. a display device, is characterized in that, comprises display panel claimed in claim 7.
9. a manufacture method for array base palte, is characterized in that, comprising:
On a substrate, form metal level;
Described in patterning, metal level is to form data line, source electrode and drain electrode, and wherein said drain electrode is electrically connected with described data line;
On described metal level, form transparency conducting layer;
Described in patterning, transparency conducting layer is to form pixel electrode and to directly overlay the nesa coating on described data line.
10. the manufacture method of array base palte as claimed in claim 9, is characterized in that, described pixel electrode covers on described source electrode, and described pixel electrode is electrically connected with described source electrode.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310393652.1A CN103913874A (en) | 2013-09-02 | 2013-09-02 | Array substrate, display device and manufacturing method of array substrate |
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| CN201310393652.1A CN103913874A (en) | 2013-09-02 | 2013-09-02 | Array substrate, display device and manufacturing method of array substrate |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1794077A (en) * | 2004-12-24 | 2006-06-28 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and fabricating method thereof |
| CN102169256A (en) * | 2011-05-09 | 2011-08-31 | 深圳市华星光电技术有限公司 | Liquid crystal display, colorful optical filter substrate, thin film transistor substrate and manufacture method thereof |
| KR101258903B1 (en) * | 2012-02-24 | 2013-04-29 | 엘지디스플레이 주식회사 | Liquid crystal display device and the method of fabricating thereof |
| CN103236419A (en) * | 2013-04-26 | 2013-08-07 | 京东方科技集团股份有限公司 | Preparation method of array substrate, array substrate and display device |
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2013
- 2013-09-02 CN CN201310393652.1A patent/CN103913874A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1794077A (en) * | 2004-12-24 | 2006-06-28 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and fabricating method thereof |
| CN102169256A (en) * | 2011-05-09 | 2011-08-31 | 深圳市华星光电技术有限公司 | Liquid crystal display, colorful optical filter substrate, thin film transistor substrate and manufacture method thereof |
| KR101258903B1 (en) * | 2012-02-24 | 2013-04-29 | 엘지디스플레이 주식회사 | Liquid crystal display device and the method of fabricating thereof |
| CN103236419A (en) * | 2013-04-26 | 2013-08-07 | 京东方科技集团股份有限公司 | Preparation method of array substrate, array substrate and display device |
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Application publication date: 20140709 |