CN103855077B - The formed method of semiconductor structure with contact plug - Google Patents
The formed method of semiconductor structure with contact plug Download PDFInfo
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- CN103855077B CN103855077B CN201210517708.5A CN201210517708A CN103855077B CN 103855077 B CN103855077 B CN 103855077B CN 201210517708 A CN201210517708 A CN 201210517708A CN 103855077 B CN103855077 B CN 103855077B
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Abstract
The present invention discloses a kind of semiconductor structure with contact plug and forming method thereof, and semiconductor structure includes a substrate, a transistor, one first inner layer dielectric layer, one second inner layer dielectric layer, one first contact plug, one second contact plug and third contact plug.Transistor is arranged in substrate, and includes a grid and source/drain region.First inner layer dielectric layer is arranged on transistor.First contact plug is arranged in the first inner layer dielectric layer, and its top surface is higher than a top surface of the grid.Second inner layer dielectric layer is set on the first inner layer dielectric layer.Second contacts plug in the second inner layer dielectric layer to be electrically connected the first contact plug.Third contact plug is set in the first inner layer dielectric layer and the second inner layer dielectric layer to be electrically connected grid.
Description
Technical field
The present invention relates to it is a kind of have contact plug the formed method of semiconductor structure, especially for, be to be related to one
Kind semiconductor structure, wherein the top surface of the first contact plug is higher than the top surface of grid.
Background technology
In existing semiconductor industry, polysilicon is widely used in semiconductor element such as metal-oxide semiconductor (MOS)
In (metal-oxide-semiconductor, MOS) transistor, the grid material as standard selects.However, with MOS crystalline substances
Constantly micro, conventional polysilicon gate cause element efficiency to drop to body pipe size because of boron penetration (boronpenetration) effect
It is low and its be difficult to avoid that depletion effects (depletioneffect) the problems such as so that equivalent gate dielectric layer thickness increases
Add, gate capacitance value declines, and then the predicaments such as decline for leading to element driving force.Therefore, semiconductor industry is more tasted with new
Grid material, such as replace traditional polysilicon gate using work function (work function) metal, to as matching
The coordination electrode of high-k (high-k) gate dielectric.
In addition, it is existing formed with metal gates transistor fabrication process after, can also be formed on external circuit with
Metal gates and the source/drain regions of transistor are electrically connected, as the input/output terminal with external electronic signal.So
And in existing manufacture craft, multiple contact plugs being connected up and down would generally be included by connecting the external circuit of source/drain regions,
This so that there is the problem of too high in resistance to external circuit.Also, with the increasingly diminution of component size, connect source/drain
The contact plug in area is easily and metal gate contact generates short-circuit situation, causes element quality decline, and as a needs
It solves the problems, such as.
Invention content
The purpose of the present invention is to provide it is a kind of have contact plug semiconductor structure with and forming method thereof, with promoted
The electrical performance of overall semiconductor structure.
In order to achieve the above object, according to embodiment of the present invention, there is contact plug the present invention provides a kind of
Semiconductor structure is inserted comprising a substrate, a transistor, one first inner layer dielectric layer, one second inner layer dielectric layer, one first contact
Bolt, one second contact plug and third contact plug.Transistor is arranged in substrate, and transistor include a grid and
Source/drain region.First inner layer dielectric layer is arranged on transistor.First contact plug is arranged on the first inner layer dielectric layer
In, the first contact plug electrical connection source/drain regions, and the top surface of the first contact plug is higher than a top surface of grid.In second
Layer dielectric layer is set on the first inner layer dielectric layer.Second contact plug is in the second inner layer dielectric layer with the first contact of electrical connection
Plug.Third contact plug is set in the first inner layer dielectric layer and the second inner layer dielectric layer to be electrically connected grid.
Embodiment according to another preferred forms the semiconductor with contact plug the present invention provides a kind of
The method of structure.One substrate is provided first, is subsequently formed a transistor in substrate, transistor includes a grid and a source
Pole/drain region.Then one first inner layer dielectric layer is formed on transistor.One first contact plug is formed in the first interlayer dielectric
In layer, the first contact plug electrical connection source/drain regions, and the top surface of the first contact plug is higher than a top surface of grid.It is formed
One second inner layer dielectric layer is on the first inner layer dielectric layer.Finally, one second contact plug is formed in the second inner layer dielectric layer
With electrical connection the first contact plug, plug is contacted in the first inner layer dielectric layer and the second inner layer dielectric layer with forming a third
To be electrically connected grid.
Description of the drawings
Fig. 1 to Figure 10 show a kind of step schematic diagram for forming the semiconductor structure with contact plug of the present invention.
Main element symbol description
300 substrate, 324 second barrier layer
302 shallow trench isolation, 326 second metal layer
304 contact hole etching stopping layers 328 second contact plug
306 dielectric layer, 330 third contacts plug
308 first inner layer dielectric layer, 400 transistor
310 first 402 grids of opening
311 first barrier layer, 403 top surface
312 the first metal layer, 404 gate dielectric
314 first contact 406 clearance walls of plug
316 etching stopping layer, 408 source/drain regions
318 second inner layer dielectric layer 408a source/drain regions
320 first 409 metal silicide layers of opening
322 second opening 409a metal silicide layers
Specific embodiment
For the general technology person for being familiar with the technical field of the invention is enable to be further understood that the present invention, hereafter spy enumerates
Several preferred embodiments of the present invention, and attached drawing, the constitution content that the present invention will be described in detail and the work(to be reached appended by cooperation
Effect.
It please refers to Fig.1 to Figure 10, it is depicted that there is the step of semiconductor structure of contact plug for a kind of formation of the present invention
Schematic diagram, wherein Fig. 2 are along the diagrammatic cross-section of AA ' tangent lines in Fig. 1, and Fig. 9 is to illustrate in Figure 10 along the section of AA tangent lines
Figure.As shown in Figures 1 and 2, a substrate 300 is provided first, and multiple shallow trench isolation (shallow are formed in substrate 300
trench isolation,STI)302.Substrate 300 may, for example, be silicon base (silicon substrate), epitaxial silicon
(epitaxial silicon substrate), silicon germanium semiconductor substrate (silicon germanium substrate), carbon
SiClx substrate (silicon carbidesubstrate) or silicon-coated insulated (silicon-on-insulator, SOI) substrate, but
It is not limited with above-mentioned.Then in forming a transistor 400 in substrate 300.Transistor 400 have a grid 402 and a source electrode/
Drain region 408.In present pre-ferred embodiments, transistor 400 is by a post tensioned unbonded prestressed concrete (gate last) semiconductor fabrication work
Skill and form the transistor 400 with metal gates 402.For example, post tensioned unbonded prestressed concrete manufacture craft is first to form one in substrate 300
Dummy gate (not shown), then sequentially form a clearance wall 406, the contact of source/drain region 408, one hole etching stopping layer
(contact etch stop layer, CESL) 304 and one dielectric layer 306 then removes dummy gate to form a groove
(not shown) finally inserts a gate dielectric 404 and a grid 402 in the trench, then carries out a planarization and makes work
Skill causes a top surface 403 of grid 402 to be flushed with dielectric layer 306.In one embodiment, as shown in Fig. 2, gate dielectric
404 have " U-shaped " section, and material can include silica, also may include high-k (high-K) material；Grid
402 can include one or more layers metal material, such as include a workfunction layers (work function metal
Layer), a barrier layer (barrier layer) and a low resistance metal layer.
It is worth noting that, each element in transistor 400 can have different embodiment aspects according to different designs,
For example, as shown in Fig. 2, source/drain regions 408 can be included is grown up (selective epitaxial with selective epitaxial
Growth, SEG) formed germanium silicide (SiGe) or silicon carbide (SiC), be respectively suitable for P type metal oxide semiconductor crystalline substance
Body pipe (PMOS) or N-type metal oxide semiconductor transistor (NMOS).In present pre-ferred embodiments, source/drain regions
408 epitaxial layers included can be projected upwards in substrate 300, and are extended downward into substrate 300.In one embodiment, epitaxial layer
With hexahedron (hexagon is called sigma Σ) or octahedra (octagon) cross sectional shape, and it is generally flat with one
Bottom surface.In another embodiment, this epitaxial layer can further extend to 406 lower section of clearance wall, logical for increasing by 402 lower section of grid
Stress needed for road (channel).Or as shown in figure 3, source/drain regions 408 can also the modes such as ion implanting form source
Pole/drain region 408a, and the shape of source/drain regions 408 can also be adjusted according to the stress needed for 402 down channel of grid
It is whole；And in another embodiment, contact hole etching stopping layer 304 can also have a stress.And in another embodiment of the present invention,
As shown in figure 3, being different from gate dielectric 404 in the embodiment of Fig. 2 is made with " rear high dielectric constant layer (high-klast) "
Make technique and form (i.e. gate dielectric 404 is formed after dummy gate is removed), gate dielectric in the embodiment of Fig. 3
404a be formed with " first high dielectric number of plies layer (high-k first) " manufacture craft (i.e. gate dielectric be dummy gate it
Preceding formation), therefore gate dielectric 404a is that have "-type " section, on the other hand, in the embodiment of Fig. 3, source/drain regions
Also there can be a metal silicide layer (silicide) layer 409a on 408a.Above-mentioned embodiment is merely illustrative, and the present invention is brilliant
Body pipe 400 can have various different embodiment aspects, not repeat one by one herein.Following embodiment will be with transistor in Fig. 2 400
Embodiment aspect is described.
As shown in figure 4, form one first inner layer dielectric layer 308 comprehensively in substrate 300.Then in dielectric layer 306 and
One first opening 310 is formed in first inner layer dielectric layer 308, wherein the first opening 310 can expose source/drain regions 408.Shape
Mode into the first opening 310 forms one first mask layer (not shown) and one for example on the first inner layer dielectric layer 308
One photoresist layer (not shown), and utilize an at least lithography step and at least an etching step patterns the first light respectively
Resist layer and the first mask layer are caused, then removes the first photoresist layer, and utilize the first mask layer after patterning
The first inner layer dielectric layer 308 and dielectric layer 306 are etched for mask, to form the first opening 310.In one embodiment of the invention
In, the first photoresist layer and the first mask layer can have different selections depending on Manufacturing Techniques, for example, the
One photoresist layer is, for example, to be suitble to the photoresist material of 193 nanometers of (nm) wavelength, and under the first photoresist layer
Side can selectivity include a bottom anti-reflecting layer (bottom anti-reflection coating, BARC)；First mask
Layer can be the various materials for being suitable as hard mask, can include one or more layers mask material, these materials are for example
It is silicon nitride (silicon nitride, SiN), silicon oxynitride (silicon oxynitride, SiON), silicon carbide
The advanced patterned film that (siliconcarbide, SiC) or carbon containing organic material, e.g. Applied Materials provide
(advanced pattern film,APF).In a preferred embodiment, mask layer is for example by chemical company of TaiWan, China SHIN-ETSU HANTOTAI
Siliceous anti-reflecting layer (the silicon-containing hard-mask that (Shin-Etsu Chemical Co.Ltd.) is provided
Bottom anti-reflection coating, SHB) and organic dielectric layer (organic dielectric layer,
ODL), wherein SHB layers under photoresist layer, a bottom anti-reflecting layer and mask layer can be used as, and ODL layers are then
The mask layer final as one.
In one embodiment of this invention, a self-aligned metal silicate can be carried out after the first opening 310 is formed
(salicide) manufacture craft forms a metal silicide layer to be open on 310 source/drain regions 408 exposed first
409, an e.g. nickle silicide (NiSi) layer.And in another embodiment of the invention, if the embodiment aspect according to Fig. 3, i.e.,
The step of metal silicide layer 409a is had been formed on the 408a of source/drain regions, then this forms metal silicide can be omitted.
Then as shown in figure 5, forming one first contact plug 314 in the first opening 310.Form the first contact plug
314 method, such as one first barrier layer 311 and a first metal layer 312 are first formed in substrate 300, wherein the first resistance
Conformally (conformally) is filled in the first opening 310 barrier layer 311, and the first metal layer 312 is fully filled with the first opening
310.In one embodiment of this invention, the first barrier layer 311 be, for example, titanium (Ti), titanium nitride (TiN), tantalum titanium (TaN) or
It is that may include multilayer different metal material, such as titanium/titanium oxide etc., but be not limited thereto.The first metal layer 312 includes various
The materials such as low-resistance metal material, e.g. aluminium (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), compared with
Good is tungsten or copper, is most preferably tungsten, and forming appropriate ohm with the source/drain regions 408 with metal silicide layer 409 or lower section connects
It touches (Ohmic contact).In one embodiment of this invention, the first contact plug 314 can have appropriate stress, such as
Forming the first metal layer 312 can when being applied on source/drain regions 408 with compression or stretching stress, this stress
To increase the electrical performance of transistor 400.In one embodiment, if transistor 400 is NMOS, the first metal layer 312 can be with
With stretching stress.Subsequently, a planarization manufacture craft, e.g. chemical mechanical grinding (chemical mechanical are carried out
Polish, CMP) manufacture craft, etching process or the two combination, with remove first opening 310 other than first resistance
Barrier layer 311 and the first metal layer 312, and further remove 308 to one predetermined thickness T of the first inner layer dielectric layer.Such as Fig. 5 institutes
Show, after planarization manufacture craft has been carried out, the top surface 403 of grid 402 is not exposed, and be also covered in first
Layer dielectric layer 308 has predetermined thickness T.In one embodiment of this invention, predetermined thickness T can be more than 100 angstroms, preferably can be between
Between 100 angstroms to 500 angstroms, it is most preferably range between 100 angstroms to 300 angstroms.
As shown in fig. 6, form an etching stopping layer 316 and one second inner layer dielectric layer 318 comprehensively in substrate 300.
In present pre-ferred embodiments, etching stopping layer 316 be, for example, a nitrogenous layer (nitrogen containing layer) or
One carbon-containing bed (carbon containing layer), specifically, can be silicon nitride (SiN), silicon carbide (SiC) or
Carbonitride of silicium (SiCN).Second inner layer dielectric layer 318 can then include one or more layers dielectric layer structure, can pass through one
Chemical gaseous phase depositing (chemicalvapor deposition, CVD), rotary coating (spin-coating) or it is any for
The manufacture craft of dielectric material is formed to be formed.And in one embodiment of this invention, etching stopping layer 316 can also be omitted,
Namely directly the second inner layer dielectric layer 318 is formed on the first inner layer dielectric layer 308.
As shown in fig. 7, a photoetching and etching step are carried out, in the second inner layer dielectric layer 318 and etching stopping layer 316
It is middle to form one second opening 320, to expose the first contact plug 314.In one embodiment of this invention, the second opening is formed
320 mode includes and forms one second mask layer (not shown) and one second photoresist layer (not shown), wherein second
Photoresist layer and the embodiment of the second mask layer are similar to the first photoresist layer and the first mask layer, herein
It repeats no more.In one embodiment of this invention, the width of the second opening 320 can be more than the width of the first contact plug 314, make
The probability of alignment failure can be reduced when must be subsequently stuffed into conductive layer, to increase the margin of manufacture craft.
Then as shown in figure 8, carrying out another photoetching and etching step, in the second inner layer dielectric layer 318, etching stopping layer
316 and first third opening 322 is formed in inner layer dielectric layer 308, wherein third opening 322 can expose grid 402
Top surface 403.In one embodiment of this invention, the mode for forming third opening 322 (is schemed not comprising a third mask layer is formed
Show) an and third photoresist layer (not shown), the wherein embodiment party of third photoresist layer and third mask layer
Formula is similar to the first photoresist layer and the first mask layer.And it is worth noting that, in one embodiment, due to third light
It is the ODL for employing photoresist layer/SHB/ODL three-deckers, wherein bottom to cause resist layer and third mask layer
Layer fills out hole ability, therefore can effectively insert in the second opening 320 with good.After third opening 322 is formd,
Photoresist layer/SHB/ODL three-deckers remove.Subsequently, a cleaning manufacture craft is also optionally carried out, such as with argon
Gas (Ar) cleans the surface of the second opening 320 and third opening 322.
As shown in Figures 9 and 10, one second barrier layer 324 and a second metal layer 326 are formed in substrate 300,
In the second barrier layer 324 can conformally be formed along the surface of the second opening 320 and third opening 322, and second metal layer
326 can be fully filled with the second opening 320 and third opening 322.In one embodiment of this invention, the second barrier layer 324
Can be the material of single-layer or multi-layer, e.g. titanium (Ti), titanium nitride (TiN), tantalum titanium (TaN), titanium/titanium oxide or above-mentioned
Combination；And second metal layer 326 is then comprising various low-resistance metal materials, the e.g. materials such as aluminium, titanium, tantalum, tungsten, niobium, molybdenum, copper
Material, preferably tungsten or copper are most preferably copper, to reduce and the grid 402 of lower section contacts with first resistance value between plug 314.
Then, a planarization manufacture craft is carried out to remove the second barrier layer 324 other than the second opening 320 and third opening 322
And second metal layer 324.As shown in figure 9, the second barrier layer 324 and 324 shape of second metal layer in the second opening 320
Into the second contact plug 328, and the second barrier layer 324 in third opening 322 and second metal layer 324 also shape simultaneously
Plug 330 is contacted into third.
In other embodiment of the present invention, different resistances can also be inserted in the second opening 320 and third opening 322
Barrier layer and metal layer.For example, after can third opening 322 first being inserted a sacrificial layer, the second opening 320 is inserted one
Second barrier layer and second metal layer subsequently remove the sacrificial layer in third opening 322, then in selectivity with other one
Sacrificial layer is covered in the second opening 320, and third opening 322 then is inserted a third barrier layer and a third metal layer.
Finally a planarization manufacture craft is carried out again.In this case, first contact plug 314, second contact plug 328 and
Third contact plug 330 can respectively have different metal layers.In one embodiment, the first contact plug 314 and second
Tungsten can be included by contacting the metal layer in plug 328, and the metal layer in third contact plug 330 can include copper.In addition
In one embodiment, the metal layer of the first contact plug 314 includes tungsten, and the second contact plug 328 and third contact plug 330
Metal layer includes copper.
Finally, a metal interconnecting manufacture craft can be carried out, a metal interconnecting is formed on the second inner layer dielectric layer 318
System (metal interconnection system) (not shown), it includes multiple layer metal interlayer dielectric layer (inter-
Metal dielectric layer, IMD layer) and more metal layers (i.e. so-called metal1, metal 2 ... etc.).
Metal interconnecting system can contact plug 330 by third with the grid 402 for being electrically connected transistor 400 and be connect by second
It touches plug 328 and first and contacts plug 314 to be electrically connected the source/drain regions 408 of transistor 400, to provide transistor 400
Input/output to external signal.
Pass through method proposed by the invention, you can be situated between in dielectric layer 306, the first inner layer dielectric layer 308 and the second internal layer
The first contact plug 314, second contact plug 328 is formd in electric layer 318, (the i.e. so-called Metal of plug 330 is contacted with third
0 layer).As shown in figure 9, the present invention provides a kind of semiconductor structure with contact plug, it is brilliant to include a substrate 300, one
Body pipe 400, one first inner layer dielectric layer 308, one second inner layer dielectric layer 318, one first contact plug 314, one second contact
328 and one third of plug contacts plug 330.Transistor 400 is arranged in substrate 300, and includes a grid 402 and a source
Pole/drain region 408.First inner layer dielectric layer 308 is arranged on transistor 400.First contact plug 314 is arranged on the first internal layer
In dielectric layer 308, the first contact plug 314 is electrically connected source/drain regions 408, and the top surface of the first contact plug 314 is higher than grid
The top surface 403 of pole 402.Second inner layer dielectric layer 318 is set on the first inner layer dielectric layer 308.Second contact plug 328 is in the
In two inner layer dielectric layers 318 be electrically connected this first contact plug 314.Third contact plug 330 is set on the first inner layer dielectric layer
308 and second in inner layer dielectric layer 318 to be electrically connected grid 402.
The one of feature of the present invention is, carrying out such as the planarization manufacture craft of Fig. 5 to form the first contact plug
When 314, the top surface 403 of grid 402 can't be exposed, but can also have the first inner layer dielectric layer 308 of a thickness T.
It is compared with existing technology, the planarization manufacture craft of the prior art would generally be ground to the top surface of grid, therefore meeting during grinding
Easy damage gate 402, and grind necessary simultaneous grinding grid in manufacture craft, gate dielectric, the first contact plug etc.
Element, the selection for lapping liquid are a test.The present invention through the above steps, not only can be to avoid the above-mentioned prior art
The shortcomings that, on the other hand, the second contact plug 328 is being formed come when contacting the first contact plug 314, as shown in figure 9, second connects
There is a height T (the i.e. predetermined thickness of the first inner layer dielectric layer 308 top surface 403 for touching the distance from bottom grid 402 of plug 328
T), this to be not easy to generate short circuit with grid 402 in formation the second contact plug 328, therefore it is well-to-do to increase manufacture craft
It spends (process window).And such manufacture craft also makes be subsequently formed the second different contact plug 328 of depth with
And third contact plug 330, i.e., the second contact plug 328 can be located in the second inner layer dielectric layer 318 and etching stopping layer 316,
And third contact plug 330 can be located at the second inner layer dielectric layer 318,316 and first inner layer dielectric layer 308 of etching stopping layer
In.
In addition in an embodiment of the invention, the first contact plug 314 can have appropriate stress, therefore the present invention
Other than it can reduce the grinding consume to the first contact plug 314, in addition also having is advantageous in that can retain first connects
The stress of plug 314 is touched, to increase the electrical performance of transistor 400.
Another feature of the present invention is, the second opening 320 is formed with etching process with straight with a photoetching
Exposure the first contact plug 314 is connect, is then open 322 to form third with directly exposed with another photoetching and etching process
Grid 402.By the forming step of this two-part, the second contact plug 328 can be promoted and third contacts plug 330
Positioning accurate accuracy.In addition, in another embodiment of the invention, the order for forming the second opening 320 and third opening 322 can be with
Exchange, such as third opening 322 first formed directly to expose grid 402 with a photoetching and etching process, then with
An other photoetching contacts plug 314 to form the second opening 320 with etching process directly to expose first.On the other hand,
The present invention can be applied to other semiconductor products, such as fin field-effect transistor (finFET) and three gate field effect transistors
The manufacture craft of the non-planar transistors such as (tri-gate FET) (non-planarFET), those embodiments belong to the present invention
The range covered.
The foregoing is merely presently preferred embodiments of the present invention, and all equivalent changes done according to the claims in the present invention are with repairing
Decorations should all belong to the covering scope of the present invention.
Claims (20)
1. a kind of method for forming the semiconductor structure with contact plug, comprising：
One substrate is provided；
A transistor is formed in the substrate, which includes a grid and source/drain region；
One first inner layer dielectric layer is formed on the transistor, wherein a bottom surface of first inner layer dielectric layer and the crystal
The top surface of the grid of pipe trims, and first inner layer dielectric layer is a single layer structure；
One first contact plug is formed in first inner layer dielectric layer, which is electrically connected the source/drain regions,
And the top surface of the first contact plug is higher than a top surface of the grid；
One second inner layer dielectric layer is formed on first inner layer dielectric layer；And
One second contact plug is formed to be electrically connected the first contact plug in second inner layer dielectric layer, with forming a third
Plug is contacted in first inner layer dielectric layer and second inner layer dielectric layer to be electrically connected the grid.
2. the method for the semiconductor structure with contact plug is formed as described in claim 1, wherein forming second contact
The step of plug contacts plug with the third includes：
One second opening is formed in second inner layer dielectric layer to expose the first contact plug；
Third opening is formed in second inner layer dielectric layer and first inner layer dielectric layer to expose the grid；And
A second metal layer is inserted in second opening and third opening.
3. the method for the semiconductor structure with contact plug is formed as claimed in claim 2, second is opened wherein being initially formed this
Mouthful, re-form third opening.
4. the method as claimed in claim 2 for forming the semiconductor structure with contact plug, is opened wherein being initially formed the third
Mouthful, re-form second opening.
5. the method for the semiconductor structure with contact plug is formed as described in claim 1, wherein forming first contact
The step of plug, includes：
One first opening is formed in first inner layer dielectric layer to expose the source/drain regions；
A first metal layer is inserted in first opening；And
One planarization manufacture craft.
6. the method as claimed in claim 5 for forming the semiconductor structure with contact plug, wherein carrying out the planarization step
After rapid, also there is first inner layer dielectric layer of a predetermined thickness on the top surface of the grid.
7. the method as claimed in claim 6 for forming the semiconductor structure with contact plug, the wherein predetermined thickness are more than
100 angstroms.
8. the method as claimed in claim 5 for forming the semiconductor structure with contact plug, wherein inserting first gold medal
Before belonging to layer, metal silicide production technique also is automatically aligned to comprising one, with the source/drain of the exposure in first opening
A metal silicide layer is formed in area.
9. the method as described in claim 1 for forming the semiconductor structure with contact plug, wherein the first contact plug
With a stress.
10. the method for semiconductor structure of the formation as described in claim 1 with contact plug is also included to form one and etch and be stopped
Only layer is between first inner layer dielectric layer and second inner layer dielectric layer.
11. a kind of semiconductor structure with contact plug, comprising：
Substrate；
Transistor is set in the substrate, which includes a grid and source/drain region；
First inner layer dielectric layer is set on the transistor, wherein a bottom surface of first inner layer dielectric layer and the crystal
The top surface of the grid of pipe trims, and first inner layer dielectric layer is a single layer structure；
First contact plug, is set in first inner layer dielectric layer, which is electrically connected the source/drain regions,
And the top surface of the first contact plug is higher than a top surface of the grid；
Second inner layer dielectric layer is set on first inner layer dielectric layer；
Second contact plug is set in second inner layer dielectric layer to be electrically connected the first contact plug；And
Third contacts plug, to be electrically connected the grid in first inner layer dielectric layer and second inner layer dielectric layer.
12. the semiconductor structure with contact plug as claimed in claim 11, first internal layer wherein on the grid is situated between
Electric layer has a predetermined thickness.
13. the semiconductor structure with contact plug as claimed in claim 12, the wherein predetermined thickness are more than 100 angstroms.
14. the semiconductor structure with contact plug as claimed in claim 11, the wherein source/drain regions include an extension
Layer, protrudes from the substrate.
15. the semiconductor structure with contact plug as claimed in claim 11, the wherein transistor also include a metallic silicon
Compound layer is set between the first contact plug and the source/drain regions.
16. the semiconductor structure with contact plug as claimed in claim 11, the wherein second contact plug and the third
It contacts plug and all includes a second metal layer.
17. the semiconductor structure with contact plug described in claim 16, wherein the first contact plug include one first
Metal layer, the first metal layer include aluminium, copper, titanium, tantalum, tungsten, niobium or molybdenum.
18. the semiconductor structure with contact plug described in claim 16, wherein the first contact plug include one first
Metal layer, and the first metal layer and the second metal layer are unlike material.
19. the semiconductor structure with contact plug described in claim 11, wherein the first contact plug include one first
Metal layer, this second contact plug include a second metal layer, the third contact plug include a third metal layer, and this first
Metal layer, the second metal layer and the third metal layer are unlike material.
20. the semiconductor structure with contact plug described in claim 11, wherein being also set to comprising an etching stopping layer
Between first inner layer dielectric layer and second inner layer dielectric layer.
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| CN201210517708.5A CN103855077B (en) | 2012-12-05 | 2012-12-05 | The formed method of semiconductor structure with contact plug |
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| CN201210517708.5A CN103855077B (en) | 2012-12-05 | 2012-12-05 | The formed method of semiconductor structure with contact plug |
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| TWI620234B (en) * | 2014-07-08 | 2018-04-01 | 聯華電子股份有限公司 | Method for fabricating semiconductor device |
| KR102400375B1 (en) * | 2015-04-30 | 2022-05-20 | 삼성전자주식회사 | Semiconductor devices and methods of manufacturing the same |
| US9799741B2 (en) | 2015-12-16 | 2017-10-24 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device and method for manufacturing the same |
| US9837539B1 (en) * | 2016-11-29 | 2017-12-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and method of forming |
| DE102020121496A1 (en) * | 2019-09-30 | 2021-04-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | DIFFERENT THROUGH CONTACT CONFIGURATIONS FOR DIFFERENT THROUGH CONTACT AREA REQUIREMENTS |
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| CN101533853A (en) * | 2008-03-13 | 2009-09-16 | 台湾积体电路制造股份有限公司 | Semiconductor structures |
| CN102468328A (en) * | 2010-10-28 | 2012-05-23 | 台湾积体电路制造股份有限公司 | Contact structure for reducing gate resistance and method of making the same |
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| DE10056871B4 (en) * | 2000-11-16 | 2007-07-12 | Advanced Micro Devices, Inc., Sunnyvale | Improved gate contact field effect transistor and method of making the same |
| US6924184B2 (en) * | 2003-03-21 | 2005-08-02 | Freescale Semiconductor, Inc. | Semiconductor device and method for forming a semiconductor device using post gate stack planarization |
| US8749067B2 (en) * | 2010-08-18 | 2014-06-10 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor device and method for forming the same |
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| CN101533853A (en) * | 2008-03-13 | 2009-09-16 | 台湾积体电路制造股份有限公司 | Semiconductor structures |
| CN102468328A (en) * | 2010-10-28 | 2012-05-23 | 台湾积体电路制造股份有限公司 | Contact structure for reducing gate resistance and method of making the same |
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