CN103854587B

CN103854587B - Gate driver circuit and its unit and a kind of display

Info

Publication number: CN103854587B
Application number: CN201410060595.XA
Authority: CN
Inventors: 张盛东; 廖聪维; 胡治晋; 李文杰; 李君梅
Original assignee: Peking University Shenzhen Graduate School
Current assignee: Peking University Shenzhen Graduate School
Priority date: 2014-02-21
Filing date: 2014-02-21
Publication date: 2017-03-01
Anticipated expiration: 2034-02-21
Also published as: CN103854587A

Abstract

This application discloses a kind of gate drive circuit unit, with existing gate drive circuit unit for circuit structure framework, including drive module, low level maintenance module, the first input module and the second input module.By improving to the switching transistor of the first input module and the second input module, extra increase transistor and external control signal, it is achieved thereby that the switching of the many scan patterns of gate drive circuit unit, and gate drive circuit unit is during different working conditions, according to circuit logic and public requirement, farthest it is multiplexed each circuit module, thus improving module utilization ratio, saving hardware spending.Based on above-mentioned gate drive circuit unit, disclosed herein as well is a kind of gate driver circuit and a kind of display.

Description

Grid driving circuit, unit thereof and display

Technical Field

The application relates to the field of electronics, in particular to a display, a grid driving circuit and a grid driving unit circuit thereof.

Background

A Thin Film Transistor (TFT) Panel Display (FPD) is the mainstream of Display technology today. In recent years, gate drive circuit designs (GIA) integrated with TFTs are beginning to be widely used in medium and small size display panels, even large size display panels. Through reasonable circuit design, even if the a-Si TFT is adopted, a GIA circuit with good performance can be obtained, and the requirements of display application in the aspects of circuit response speed, stability, power consumption and the like are met. The display panel integrated with the gate driving circuit has the advantages of narrow frame, high resolution, low price and the like.

Oxide transistors (IGZO TFTs) have high mobility and better stability and are more suitable for high resolution, large area display applications, and therefore IGZO TFTs are more likely to become the mainstream TFT technology in the future. The development of a new high-performance GIA circuit based on IGZO TFTs has attracted considerable attention from researchers. IGZO TFTs can significantly improve the performance of circuits due to advantages such as high mobility. In the case of a-Si or organic TFT, the mobility is too low, and thus many circuit technologies are limited in application, for example, feedback circuit units cannot exhibit their intended utility due to too low speed. The introduction of IGZO TFTs may use flexible or transparent display panels as platforms to implement richer circuit technologies, so that the display panel System (SoP) is more intelligent.

In recent years, integrated gate drive circuit designs featuring multiple scan modes have attracted attention in the TFT FPD industry. Taking the bidirectional scanning mode as an example, the gate driving circuit can sequentially scan not only the gate lines with a small number of orders to the gate lines with a large number of orders but also the gate lines with a large number of orders in coordination with the peripheral clock signal. With the addition of the bidirectional scanning feature, tftftfpd achieves the following benefits: (1) when the FPD is switched between forward and reverse scan modes, a mirror image of the displayed image can be realized in a direction perpendicular to the gate lines. This enhances the operability, interest and user-friendliness of the FPD. (2) The display panel is more flexible in configuration and more convenient to meet the requirements of different designers.

In the prior art, there are generally two methods for implementing a bi-directional integrated gate driving circuit: one is to design two sets of scanning circuits, which are respectively used for realizing forward scanning and reverse scanning; and the second is to increase the electric signal for controlling the scanning direction. The effect of adopting the two methods to realize the grid drive circuit is not ideal. This is because the first method requires a complicated circuit configuration, and the number of TFTs used is almost twice as many as that of the unidirectional scanning gate driver circuit. In the first gate driver circuit, almost always half of the devices are in an idle state in any operation period. The second method can reduce the number of TFTs, but the number of control signals is increased, and these newly added control signals will increase the voltage bias time of the TFTs in the gate driving circuit, and shorten the service life of the gate driving circuit.

In summary, the IGZO TFT is more suitable for designing a multi-mode GIA circuit. For example, the IGZO TFT has a small leakage current, and the refresh frequency of the TFT panel array can be reduced when a still image is displayed, which not only reduces the power consumption of the TFT panel and extends the battery life of the mobile TFT panel, but also has an advantage in reducing eye fatigue of a user. The GIA design of IGZO TFTs then imposes new requirements: for one, the GIA circuit of the IGZO TFT is required to have a plurality of scan patterns; secondly, the scanning pulse with high frequency can be output to display dynamic images, and the static images can be displayed with low refreshing frequency. However, conventional GIA designs do not support the functionality of multiple scan modes. Therefore, it is necessary to research a new GIA scheme of IGZOTFT so that it has a multi-scan mode function, and has a simpler circuit structure and a smaller number of peripheral connection lines.

Disclosure of Invention

The application provides a grid driving circuit, a grid driving unit and a display.

According to a first aspect of the present application, there is provided a gate driving circuit unit comprising:

the first signal input end is used for inputting a first pulse signal.

And the second signal input end is used for inputting a second pulse signal.

The first clock signal input end is used for inputting a first clock signal.

And the signal output end is used for outputting the pulse driving signal.

The driving module is coupled between the first clock signal input end and the signal output end, transmits the first clock signal to the signal output end after the driving control end of the driving module obtains driving voltage, and charges the signal output end in a pull-up mode when the first clock signal is at a high level; when the first clock signal is at a low level, the driving module pulls down the signal output end to discharge.

A low level maintaining module coupled between the signal output terminal and the low level terminal; the low level maintaining module is used for coupling the signal output end to the low level end in response to the high level signal of the first clock signal or the high level signal of the third clock signal and maintaining the low level potential of the signal output end.

The second input module comprises at least one second switching transistor which is cascaded, the at least one second switching transistor which is cascaded is coupled between a second signal input end and a driving control end, a first pole of the first-stage second switching transistor is used for inputting a second clock signal, a second pole of the last-stage second switching transistor is coupled at the driving control end, and a control pole of each second switching transistor is coupled at the second signal input end and used for inputting a second pulse signal; in a reverse scanning mode, the second input module responds to a second pulse signal and a high-level overlapping period signal of a second clock signal to charge the driving control end; in the forward direction scanning mode, when the second pulse signal and the second clock signal are respectively at a high level and a low level, the second input module discharges the driving control end.

The first input module comprises at least one first switching transistor which is cascaded, the at least one first switching transistor which is cascaded is coupled between a first signal input end and a driving control end, a first pole of a first-stage first switching transistor is used for inputting a fourth clock signal, a second pole of a last-stage first switching transistor is coupled at the driving control end, and a control pole of each first switching transistor is coupled at the first signal input end and used for inputting a first pulse signal; in a forward scanning mode, the first input module responds to high-level overlapping period signals of the first pulse signal and the fourth clock signal to charge the driving control end; in the reverse scanning mode, when the first pulse signal and the fourth clock signal are at a high level and a low level, respectively, the first input module discharges the driving control terminal.

The first input module further comprises a fifteenth transistor, a control electrode of the fifteenth transistor is used for inputting a control signal, a first electrode of the fifteenth transistor is coupled to a second electrode of the first-stage first switch transistor, and the second electrode of the fifteenth transistor is coupled to the low-level end; the fifteenth transistor couples the second pole of the first-stage switching transistor to the low-level terminal under the control of the high-level signal of the control signal, and is turned off under the control of the low-level signal of the control signal.

The first clock signal is complementary to the third clock signal.

According to a second aspect of the present application, there is provided another gate driving circuit unit, comprising:

the first signal input end is used for inputting a first pulse signal.

And the second signal input end is used for inputting a second pulse signal.

The first clock signal input end is used for inputting a first clock signal.

And the signal output end is used for outputting the pulse driving signal.

The second input module comprises at least one second cascaded switching transistor, the at least one second cascaded switching transistor is coupled between a second signal input end and a driving control end, a first pole of a first-stage second switching transistor is used for inputting a second clock signal, a second pole of a last-stage second switching transistor is coupled at the driving control end, and a control pole of each second switching transistor is coupled at the second signal input end and used for inputting a second pulse signal; in a reverse scanning mode, the second input module responds to a second pulse signal and a high-level overlapping period signal of a second clock signal to charge the driving control end; in the forward direction scanning mode, when the second pulse signal and the second clock signal are respectively at a high level and a low level, the second input module discharges the driving control end.

The second input module further comprises a sixteenth transistor, a control electrode of the sixteenth transistor is used for inputting a control signal, a first electrode of the sixteenth transistor is coupled to a second electrode of the fourth transistor of the first-stage switch, and the second electrode of the sixteenth transistor is coupled to the low-level end; the sixteenth transistor couples the second pole of the first-stage second switching transistor to the low-level end under the control of the control signal high-level signal, and the sixteenth transistor is turned off under the control of the control signal low-level signal.

The first clock signal is complementary to the third clock signal.

According to a third aspect of the present application, there is provided a gate driving circuit comprising:

n cascaded grid drive circuit units, wherein N is an integer greater than 1. Wherein, the first stage adopts the gate driving circuit unit provided by the first aspect; the final stage employs the gate driving circuit unit provided in the second aspect described above.

According to a fourth aspect of the present application, there is provided a display comprising:

the display panel is provided with a grid line in a first direction and a data line in a second direction;

the signal output end of the gate driving unit in the gate driving circuit is coupled to the corresponding gate line;

the time sequence generating circuit is used for generating various control signals required by the grid driving circuit;

and the data driving circuit is used for generating image data signals and outputting the image data signals to the corresponding data lines in the display panel.

The beneficial effect of this application is: in the gate driving unit circuit provided by the application, the input of the transistor and one path of control signal is additionally added in the first input module and the second input module, so that the control of a scanning mode and a non-scanning mode is realized, the switching between a forward scanning mode and a reverse scanning mode can be realized in the scanning mode, and each module in the gate driving unit circuit is shared by two scanning modes, so that the utilization efficiency of each module is improved.

The shift register unit is further adopted to form a grid driving circuit, and the grid driving circuit and the pixel TFT can be manufactured on a display panel together. The design of the multi-scanning mode integrated gate drive circuit is realized by adopting one set of circuit, the number of components is small, the structure is simple, each component is reasonably utilized, and the integration degree is improved.

In addition, the improved input module in the gate drive circuit provided by the application can realize multi-input logic operation, the circuit structure is simple, and the dependence on the channel width-length ratio of the transistor is small.

Drawings

Fig. 1 is a circuit diagram of a gate driving circuit unit according to an embodiment of the present disclosure;

FIG. 2 is a timing diagram illustrating a forward scan mode of a gate driving circuit unit according to an embodiment of the present invention;

FIG. 3(a) is a structural diagram of a first input module 1 according to an embodiment of the present application,

fig. 3(b) is another structural diagram of a first input module 1 according to an embodiment of the present application;

fig. 4 is a gate driving circuit according to a second embodiment of the present disclosure;

FIG. 5 is a diagram of gate scan signals output by a second gate driving circuit in a forward scan mode according to an embodiment of the present invention;

FIG. 6 is a diagram of gate scan signals output by a second inverse scan mode according to an embodiment of the present application;

fig. 7 is a structural diagram of a third nth-stage gate driving circuit unit according to an embodiment of the present application;

fig. 8 is a diagram of a unit structure of a fourth first-stage gate driving circuit according to an embodiment of the present application;

FIG. 9 is a diagram of a four-level gate driving circuit according to an embodiment of the present disclosure;

fig. 10 is a diagram of a display structure according to a fifth embodiment of the present application;

fig. 11 is a logic transmission circuit structure according to a sixth embodiment of the present application;

fig. 12 is a logic and transmission circuit structure according to a sixth embodiment of the present application;

fig. 13 is a structure of a logic exclusive-or circuit according to a sixth embodiment of the present application.

Detailed Description

It should be understood by those skilled in the art that the gate driving circuit (unit) of the present application is improved in circuit structure by the first input module 1 and the second input module 2, and other modules can adopt the existing mature technical solutions, while in the prior art, other modules are difficult to be exhaustive in the present application. Therefore, other modules of the following embodiments are only to be regarded as illustrative of one or more aspects of the present disclosure, and are not to be considered as the entire contents of the present disclosure. One or more aspects of which include an element or elements of the claims.

The terms in the present application are first explained/defined.

Complementation: when one signal is at high level, the other signal is at low level; when one signal is at low level, the other signal is at high level. It should be noted that the complementarity defined in this embodiment is only limited in the relationship between the levels, and the relationship between the magnitudes of the high and low levels is not strictly limited.

The transistors in this application may be bipolar transistors or field effect transistors. When the transistor is a bipolar transistor, the control electrode of the transistor refers to the base electrode of the bipolar transistor, the first electrode can be the collector electrode or the emitter electrode of the bipolar transistor, and the corresponding second electrode can be the emitter electrode or the collector electrode of the bipolar transistor; when the transistor is a field effect transistor, the control electrode refers to a gate electrode of the field effect transistor, the first electrode may be a drain electrode or a source electrode of the field effect transistor, and the corresponding second electrode may be a source electrode or a drain electrode of the field effect transistor. The transistors in the display are typically Thin Film Transistors (TFTs).

Oxide transistors (IGZO TFTs) are more suitable for high-resolution, large-area display applications due to their high mobility and better stability, and are more likely to become the mainstream TFT technology in the future. The IGZO TFT is adopted to design the GIA circuit, so that the speed of the circuit can be further improved, the stability can be further enhanced, and the power consumption can be further reduced. It is that the IGZO TFT has a smaller leakage current than the silicon-based TFT, so that the refresh frequency of the TFT panel can be reduced when a static image is displayed, thereby reducing the power consumption of the TFT panel.

Relevant studies have shown that leakage current of amorphous or C-axis oriented crystalline IGZO TFTs can be as small as 10^-20A/um, which is several orders of magnitude smaller than silicon-based semiconductor devices. And the sub-threshold slope of the IGZO TFT prepared by the advanced process can approach or even break through the limit value of the sub-threshold slope of the silicon-based semiconductor device. In other words, one of the important characteristics of an IGZO TFT is that it can be turned off more thoroughly. With the excellent turn-off characteristics of IGZO TFTs, the refresh frequency of the TFT panel array may be reduced, which may reduce power consumption of the TFT panel and eye strain for users in some display applications. For example, for a color electronic paper or a color electrowetting display, when displaying a still image, the frame frequency of the TFT panel may be reduced to 0.1Hz or even less; when displaying a dynamic color image, the frame frequency of the TFT panel is restored to the ordinary 60Hz or higher.

In view of this, the embodiments of the present application further describe the present application in detail by taking the transistor as an IGZO TFT as an example. It should be noted that the circuit structure of the present application is also suitable for using other oxide transistors or other transistors with higher mobility and smaller off-state current.

Referring to fig. 1, the gate driving unit circuit in the present embodiment includes: the circuit comprises a first signal input end, a second signal input end, a first clock signal input end, a signal output end, a driving module 3, a low level maintaining module 5, a first input module 1 and a second input module 2.

A first signal input terminal for inputting a first pulse signal V_I1。

A second signal input terminal for inputting a second pulse signal V_I2。

A first clock signal input terminal for inputting a first clock signal V_A。

A signal output terminal for outputting a pulse drive signal V_O。

The driver module 3 is coupled between a first clock signal input and a signal output. After the driving control terminal Q obtains the driving voltage, the first clock signal V is provided_ATo the signal output terminal when the first clock signal V_AWhen the voltage is high level, the driving module 3 pulls up and charges the signal output end; when the first clock signal V_AWhen the voltage is low level, the driving module 3 is used for outputting a signal V_OAnd (4) pulling down and discharging.

The low level maintaining module 5 is coupled between the signal output terminal and the low level terminal. The low level maintaining module 5 responds to the first clock signal V_AHigh level signal or third clock signal V_CThe high level signal couples the signal output end to the low level end, and maintains the low level potential of the signal output end.

Generally, in order to suppress the feedthrough effect, in an embodiment, the low-level maintaining module 5 may further include a low-level maintaining enabling unit 4, the low-level maintaining enabling unit 4 is coupled to the first clock signal input terminal and the low-level terminal, and the low-level maintaining enabling unit 4 is further coupled to the signal output terminal. The low-level sustain enable unit 4 responds to the pulse driving signal V at the stage that the gate driving circuit unit of the present stage is gated_OCoupling a low level maintaining enable end P to a low level end and outputting a low level signal; in the low level dimensionIn the hold phase, the low-level hold enable unit 4 asserts the first clock signal V_AAnd controlling the low-level maintaining enable end P to output a high-level signal. At this time, the low level maintaining module 5 responds to the high level signal or the third clock signal V output by the low level maintaining enable terminal P_CThe high level signal couples the signal output end to the low level end, and maintains the low level potential of the signal output end.

The first input module 1 comprises a cascade of at least one first switching transistor T11, the cascade of at least one first switching transistor T11 being coupled between the first signal input terminal and the driving control terminal Q, a first pole (e.g. drain) of the first switching transistor T11 being used for inputting the fourth clock signal V_DA second pole (e.g., source) of the tail stage first switching transistor T11 is coupled to the driving control terminal Q; a control electrode (e.g., a gate electrode) of each first switching transistor T11 is coupled to the first signal input terminal for inputting the first pulse signal V_I1. In the forward direction scanning mode, the first input module 1 responds to the first pulse signal V_I1And a fourth clock signal V_DThe high level overlap period signal charges the driving control end Q; in the reverse scan mode, the first pulse signal V_I1And a fourth clock signal V_DWhen the voltage is respectively at a high level and a low level, the first input module 1 discharges to the driving control end Q;

the second input module 2 comprises at least one second switching transistor T14 cascaded, the at least one second switching transistor T14 cascaded is coupled between the second signal input terminal and the driving control terminal Q, a first pole (e.g., drain) of the first-stage second switching transistor T14 is used for inputting the second clock signal V_BA second pole (e.g. source) of the second switching transistor T14 of the tail stage is coupled to the driving control terminal Q, and a control pole (e.g. gate) of each second switching transistor T14 is coupled to the second signal input terminal for inputting the second pulse signal V_I2. In the reverse scan mode, the second input block 2 responds to the second pulse signal V_I2And a second clock signal V_BThe high level overlap period signal charges the driving control end Q; in forward scan mode, the second pulse signalNumber V_I2And a second clock signal V_BWhen the voltage is high and low, the second input module 2 discharges the driving control terminal Q.

In the first gate driving circuit unit circuit structure, the first input module 1 further includes a fifteenth transistor T15. A control electrode (e.g., a gate electrode) of the fifteenth transistor T15 is used for inputting the control signal V_CTRA first pole (e.g., drain) is coupled to a second pole (e.g., source) of the first-stage switching transistor T11, and the second pole (e.g., source) is coupled to the low-level terminal. The fifteenth transistor T15 is in the control signal V_CTRThe second pole (e.g., source) of the first-stage switching transistor T11 is coupled to the low-level terminal under the control of the high-level signal_CTRThe fifteenth transistor T15 is turned off under the control of the low level signal.

In the second gate driving circuit unit circuit structure, the second input block 2 further includes a sixteenth transistor T16. A control electrode (e.g., a gate electrode) of the sixteenth transistor T16 is used for inputting the control signal V_CTRA first pole (e.g., drain) is coupled to a second pole (e.g., source) of the first-stage switch four-transistor T14, and the second pole (e.g., source) is coupled to the low-level terminal. The sixteenth transistor T16 is at the control signal V_CTRThe second pole (e.g., source) of the first-stage second switching transistor T14 is coupled to the low-level terminal under the control of the high-level signal_CTRThe sixteenth transistor T16 is turned off under the control of the low level signal.

Or, further, in the third gate driving circuit unit structure, the two gate driving circuit unit structures may also be simultaneously constructed, that is, the first input module 1 further includes a fifteenth transistor T15, and the second input module 2 further includes a sixteenth transistor T16. At this time, the control electrodes (e.g., gates) of the fifteenth transistor T15 and the sixteenth transistor T16 may also share the control signal V_CTR。

Wherein the first clock signal V_AAnd a third clock signal V_CAnd (4) complementation.

Further, in the present embodiment, the following relationship should be satisfied between the clock signals/pulse signals:

first pulse signal V_I1And a second pulse signal V_I2Spaced by one clock signal period;

second clock signal V_BAnd a fourth clock signal V_DComplementation;

in the forward scanning mode, the fourth clock signal V_DLags behind the first pulse signal V_I1A phase, a first clock signal V_ALags the fourth clock signal V_DA phase;

in the reverse scan mode, the second clock signal V_BLags behind the second pulse signal V_I2One phase, the fourth clock signal V_DLags behind the first clock signal V_AOne phase.

One of the phases is T/4, and T is the period of the clock signal.

The above modules will be explained by the following specific embodiments.

The first embodiment is as follows:

referring to fig. 1, in one embodiment:

the driving module 3 includes a second transistor T2 and a first capacitor C1. A control electrode of the second transistor T2 is coupled to the driving control terminal Q, a first electrode is coupled to the first clock signal input terminal, and a second electrode is coupled to the signal output terminal; the first capacitor C1 has one end coupled to the driving control terminal Q and the other end coupled to the signal output terminal.

The low level maintaining module 5 includes a low level maintaining enable unit 4 and a first low level maintaining unit 51. The low level sustain enable unit 4 includes a sixth transistor T6 and a second capacitor C2. A control electrode of the sixth transistor T6 is coupled to the signal output terminal, a first electrode is coupled to the low level sustain enable terminal P, and a second electrode is coupled to the low level terminal; the second capacitor C2 has one terminal coupled to the first clock signal input terminal and the other terminal coupled to the low-level sustain enable terminal P.

The first low level holding unit 51 includes: a fourth transistor T4 and a seventh transistor T7. A control electrode of the fourth transistor T4 is used for inputting the third clock signal V_CA first pole coupled to the signal output terminal and a second pole coupled to the low level terminal; the seventh transistor T7 has a control electrode coupled to the low-level sustain enable terminal P, a first electrode coupled to the signal output terminal, and a second electrode coupled to the low-level terminal.

Further, in another embodiment, the low level maintaining module 5 may further include a second low level maintaining unit 52, and the second low level maintaining unit 52 includes a fifth transistor T5. The fifth transistor T5 has a control electrode coupled to the low-level sustain enable terminal P, a first electrode coupled to the driving control terminal Q, and a second electrode coupled to the low-level terminal.

In other embodiments, the modules/units may adopt other existing schemes.

In one embodiment, the first input module 1 and the second input module 2 are combined when the control signal V is applied_CTRAt a low level, the fifteenth transistor T15 and the sixteenth transistor T16 are turned off, and the gate driving circuit unit has a normal forward/reverse scan mode function. Since the control electrode (e.g., gate) of the first switching transistor T11 is shorted, the first switching transistor T11 may be equivalent to a switching transistor and is driven by the first pulse signal V_I1Controlling the on/off thereof; similarly, the second switching transistor T14 in cascade can be equivalent to a switching transistor and is driven by the second pulse signal V_I2Controlling its on/off.

When the control signal V_CTRWhen the voltage is high, the fifteenth transistor T15/the sixteenth transistor T16 are turned on, and the node where the first switching transistor T11 and the fifteenth transistor T15 in the cascade are connected is clamped at the low level end and keeps the low level; in the same way as above, the first and second,the node interconnecting the second switching transistor T14 and the sixteenth transistor T16 of the cascade is also clamped at the low terminal, keeping the low potential. Therefore, the potential of the drive control terminal Q cannot rise to a higher potential in either the forward or reverse scan mode. The gate driving circuit units all output zero level to stop the scanning function.

The operation of the present invention will be described with reference to fig. 1 by taking a third gate driving circuit unit as an example. For the working processes of the first and second gate driving circuit units, those skilled in the art can easily analyze the disclosure according to the embodiment, and therefore, the description is omitted. Fig. 2 is a timing diagram of the forward scan mode of the shift register unit in the present embodiment, and the principle is the same for the reverse scan mode, and no additional timing diagram is shown here. The working process of the shift register unit can be divided into five stages: (1) the method comprises the following steps of (1) a pre-charging stage, (2) a pull-up stage, (3) a pull-down stage, (4) a discharging stage and (5) a low-level maintaining stage. The operation of these five stages will be described in detail below.

(1) Precharge phase t1

In the pre-charging phase, the first input module 1 or the second input module 2 charges the driving control terminal Q to provide a high level voltage, and the driving module 3 is turned on in advance before the bootstrap action is triggered. At this stage, a sufficiently high turn-on voltage must be provided to the driving module 3 to avoid a serious tailing phenomenon in the subsequent pull-up/pull-down process due to insufficient driving capability of the driving module 3.

At this stage, the control signal V_CTRAt a low level, the fifteenth transistor T15 and the sixteenth transistor T16 are turned off. In the case of the forward scanning mode, the first pulse signal V_I1And a fourth clock signal V_DAt high level, the first switching transistor T11 in cascade is turned on, and the driving control terminal Q is charged to high level; in the case of the reverse scan mode, the second pulse signal V_I2And a second clock signal V_BIs high, and then the fourteenth transistor T is cascaded14 are turned on and the drive control terminal Q is charged to a high state.

In summary, in the precharge phase T1, the driving control terminal Q is charged to a high state and the second transistor T2 is fully turned on regardless of the forward or reverse direction scan. This provides for the next pull-up stage. The more the second transistor T2 is turned on, the stronger the driving capability of the second transistor T2 in the following pull-up/pull-down phase.

(2) Pull-up stage t2

The precharge phase t1 is followed by a pull-up phase t 2. At pull-up stage t2, the first clock signal V_AAt a high level, at a first clock signal V_AUnder the action of (3), the driving module 3 pulls up the signal output end to a high level with a strong driving capability through a bootstrap principle. During the scanning process, the degree of opening of the switching devices in the flat panel display array is closely related to the amplitude of the scan pulse and the effective scan pulse time. The response speed of the drive module 3 must be sufficiently fast during the pull-up phase.

In the pull-up stage t2, the first pulse signal V_I1And a second pulse signal V_I2Are low, and thus, the first switching transistors T11 and T14 connected to the driving control terminal Q are in an off state. In other words, during the pull-up period t2, the driving control terminal Q is in a floating state.

In addition, since the second transistor T2 has been turned on in the precharge phase T1 to be in a closed conductive state and the driving control terminal Q is almost floated, the second transistor T2 is maintained in a conductive state in the pull-up phase. Since the second transistor T2 has been turned on to be in a closed state in the precharge phase T1, C of the second transistor T2_GD2(capacitance between first and control electrodes, e.g. gate-drain capacitance) is equal to C_GS2(capacitance between the control electrode and the second electrode, e.g., gate-source capacitance) and are each half the capacitance of the gate dielectric layer. And a first pole (e.g., drain) of the second transistor T2_ABecomes highLevel, this case brings the following two changes: (1) c of the second transistor T2_GD2A first clock signal V_AIs coupled to the drive control terminal Q, the potential on the drive control terminal Q rises rapidly due to the coupling. Accordingly, a gate-to-second pole (e.g., gate-source) voltage difference of the second transistor T2 increases, and the pull-up driving capability of the second transistor T2 increases. (2) Strong current from the first clock signal V in high level state_AThrough the second transistor T2, which is kept closed, to the signal output terminal of the gate drive circuit unit. A load capacitor C coupled to the signal output terminal_LBecause of the accumulation of positive charge, the level on it is raised. And the potential on the driving control end Q is also along with the output pulse driving signal V_ORises up. Finally, a pulse drive signal V is output_OIs pulled up to the first high level voltage V without voltage loss_H. The above process is referred to as voltage bootstrap effect.

(3) Pull-down phase t3

Following the pull-up phase t2 is a pull-down phase t 3. In the pull-down period t3, the signal output terminal is pulled down to the low level V_L. At the end of the pull-down phase, the signal output terminal should also maintain the low level voltage V_LAnd is not changed.

At the beginning of the pull-down phase t3, the first clock signal V_AAnd goes low. First pulse signal V_I1And a second pulse signal V_I2Still remains at the low level, and thus the first switching transistors T11 and T14 still remain in an off state. Thus, the driving control terminal Q is still maintained in a floating state during the pull-down period, so that the second transistor T2 is still maintained to be turned on during the half period of the pull-down period T3. While the first clock signal V_AHas become low level V_LSo that the signal output terminal of the gate driving circuit unit is pulled down to the low level voltage V_L。

(4) Discharge phase t4

Following the pull-down phase t3 is a discharge phase t 4. In the discharging period t4, the driving control terminal Q is discharged and pulled down to a low level state.

During the discharging period t4, the first clock signal V_AIs kept at a low level, and therefore, the signal output terminal is also kept at a low level voltage V_LAnd is not changed. In the case of the forward direction scan mode, the second pulse signal V_I2Goes high to turn on the second switching transistor T14 and the second clock signal V_BGoes low, and thus the control terminal Q is driven by the second clock signal V_BDischarge pull-down to a low state through the turned-on second switching transistor T14; in the case of the reverse scan mode, the first pulse signal V_I1Goes high to turn on the first switching transistor T11 and the fourth clock signal V_DGoes low, and thus the driving control terminal Q is driven by the fourth clock signal V_DThe pull-down to the low state is discharged through the turned-on first switching transistor T11.

In summary, in the discharging phase T4, the driving control terminal Q is discharged to pull down to a low state and the second transistor T2 is turned off, regardless of the forward or reverse direction scan mode.

(5) Low-level maintaining period t5

Following the discharge phase t4, the gate driving circuit unit enters the low level sustain phase t 5. During the low-level maintaining period t5, the signal output terminal should be kept at the low-level voltage V_L. Only when the signal output terminal of the gate driving circuit unit is maintained at the low level voltage V_LOnly can guarantee that: (1) the switching thin film transistor in the pixel on the gate scan line coupled to the signal output terminal of the gate driving circuit unit is maintained in an off state, and the pixel charge programmed in the corresponding pixel is not seriously leaked. (2) The gate drive circuit units of the front and rear stages connected with the gate drive circuit unit of the current stage are not affected, and the drive control terminal Q of the adjacent stage is not affected by the gate scanning signal of the current stage to cause wrong charging or discharging action.

Therefore, two complementary clock signals are used in this embodiment: first clock signalNumber V_AAnd a third clock signal V_CTo alternately discharge the signal output terminal, ensuring that the signal output terminal is always kept at a low level potential.

During the low-level sustain period t5, regardless of the forward or reverse scan mode, when the third clock signal V is asserted_CAt the high level, the fourth transistor T4 is turned on, the signal output terminal is coupled to the low level terminal through the fourth transistor T4, and the potential thereof is pulled down to the low level voltage V_L(ii) a At a first clock signal V_AAt the high level, the low sustain enable terminal P is coupled to the high level voltage through the second capacitor C2, and the fifth transistor T5 is turned on to couple the signal output terminal to the low level terminal, the potential of which is pulled down to the low level voltage V_L。

In another embodiment, at the first clock signal V_AWhen the voltage level is high, after the low-level sustain enable terminal P obtains the high-level voltage level, the fifth transistor T5 is also turned on to couple the driving control terminal Q to the low-level terminal, so that the voltage level of the driving control terminal Q can be better maintained at the low-level voltage V5 during the low-level sustain period T5_LThe low level potential of the driving control terminal Q is effectively maintained.

In this embodiment, the sixth transistor T6 is used to pull down the low-level sustain enable terminal P to a low level when the signal output terminal is at a high level. Can effectively prevent the output of the pulse driving signal V at the signal output end_OIn the process, the low-level maintaining enable terminal P is not expected to pull up the boost voltage, so that the low-level maintaining module 5 starts to work.

It should be noted that, in a specific embodiment, the first switching transistor T11 in the cascade may be 1, 2 or more:

referring to fig. 3(a), it is a structural diagram of the first input module 1 when there is only one cascaded first switching transistor T11. The structure is a voltage division structure, and the first pulse signal V is_I1And a control signal V_CTRWhile being high, the first switching transistor T11 and the fifteenth transistorT15 are both in a conducting state, and the potential of the driving control terminal Q is determined by the divided voltages of the first switching transistor T11 and the fifteenth transistor T15. In the control signal V_CTRWhen the voltage level is high, the driving control terminal Q is desirably in a low level state, so that the driving module 3 is in a non-enabled state, and the output signal terminal is kept at a low level. Therefore, in order to make the voltage divided by the fifteenth transistor T15 small enough, the turn-on capability of the fifteenth transistor T15 must be much larger than that of the first switch transistor T11, in other words, the size of the fifteenth transistor T15 should be large enough. This aspect increases the area occupied by the fifteenth transistor T15, and increases the control signal V_CTRThe amount of load of (a); on the other hand, the leakage current of the fifteenth transistor T15 will increase due to the increase in size of the fifteenth transistor T15. Accordingly, the fifteenth transistor T15 having an excessively large size may decrease the voltage amplitude of the driving control terminal Q, thereby affecting the normal operation of the scan mode.

Referring to fig. 3(b), it is a structural diagram of the first input module 1 when there are two cascaded first switching transistors T11. The structure is a shunting structure, and the control signal V_CTRAt the high level, the fifteenth transistor T15 is in a conducting state, and thus the first pulse signal V_I1At the high level, the input current of the first switching transistor T11 of the first stage is bypassed through the fifteenth transistor T15. Even though the tail stage first switching transistor T11 is turned on, the voltage of the first pole (e.g., drain) is low due to the shunt, so almost no charging current flows through the tail stage first switching transistor T11 to charge the driving control terminal Q. The driving control terminal Q is then maintained at a low level because of insufficient charging current. In this shunting structure, the size of the fifteenth transistor T15 does not need to be large in order to respond effectively to the control signal V_CTRThe driving control terminal Q is maintained at a low level.

In summary, the shunt structure illustrated in fig. 3(b) may have the following advantages compared to the voltage division structure of fig. 3 (a): (1) more efficient response to control signal V_CTRThe drive control terminal Q is stabilized at a lower potential to play a roleThe effect of the scan is stopped. (2) The side effect on the normal scan function due to leakage of the fifteenth transistor T15 or the like is reduced. (3) The progressive transmission and accumulation of noise voltages between stages of the gate driving circuit unit, which may be caused by leakage current, are reduced.

In other embodiments, the first switching transistor T11 in cascade may be multiple, but the number of transistors in series on the input path is larger. This may bring disadvantages that the series resistance on the input path is too large, which may affect the charging effect of the driving control terminal Q, resulting in a failure of the normal scanning function of the gate driving circuit unit. In addition, actually, the structure of fig. 3(b) has been able to suppress the leakage current through the first switching transistor T11 to a smaller value in the bootstrap phase or the low level sustain phase, so adding more transistors on the input path would increase the complexity of the circuit in the contrary, and affect the normal scan function.

Therefore, in this embodiment, the number of the first switching transistors T11 in cascade connection is 2. Likewise, 2 switching transistors T14 are also preferred for the cascade.

Example two:

referring to fig. 4, the present embodiment discloses a gate driving circuit, including: and N cascaded gate drive circuit units, wherein N is an integer greater than 1. The gate driving circuit units are disposed at both sides A-A and B-B of the display panel. In other embodiments, the gate driving circuit unit may also be disposed at one side of the display panel. Arrange the gate drive circuit unit in display panel's both sides, can make the display effect difference that signal delay brought between the near-end of column line direction and the distal end reduce, in addition, because there is the coupling of signal between the column line of neighbour, consequently can more conveniently lay wire after separately to reduce the territory area, also can make display panel both sides distribute evenly, bring certain pleasing to the eye effect. Therefore, the present embodiment preferably arranges the gate driving circuit units on both sides of the display panel, and a preferable manner is: the odd-numbered stage gate driving circuit units are disposed at one side of the display panel, and the even-numbered stage gate driving circuit units are disposed at the other side of the display panel.

Four clock signal lines (CLK 1, CLK2, CLK3, CLK 4) for transmitting clock signals (V) to the gate driving circuit units, respectively_A、V_B、V_CAnd V_D) In the forward direction scan mode, clocks of the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, and the fourth clock signal line CLK4 are sequentially delayed by one phase; in the reverse scan mode, the clocks of the first, second, third, and fourth clock signal lines CLK1, CLK2, CLK3, and CLK4 are sequentially earlier by one phase, where one phase is T/4, and T is the period of the clock signal. First clock signal V of 4k +1 th stage gate driving circuit unit_AA second clock signal V_BA third clock signal V_CAnd a fourth clock signal V_DSupplied by a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3, and a fourth clock signal line CLK4, respectively; first clock signal V of 4k +2 stage gate driving circuit unit_AA second clock signal V_BA third clock signal V_CAnd a fourth clock signal V_DSupplied by the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, and the first clock signal line CLK1, respectively; first clock signal V of 4k +3 th stage gate driving circuit unit_AA second clock signal V_BA third clock signal V_CAnd a fourth clock signal V_DSupplied by a third clock signal line CLK3, a fourth clock signal line CLK4, a first clock signal line CLK1, and a second clock signal line CLK2, respectively; first clock signal V of 4 k-th stage gate driving circuit unit_AA second clock signal V_BA third clock signal V_CAnd a fourth clock signal V_DAre respectively provided by a fourth clock signal line CLK4, a first clock signal line CLK1, a second clock signal line CLK2, and a third clock signal line CLK3, where k is a natural number.

First signal startAn STV1 and a second signal start line STV2, the first signal start line STV1 is coupled to the first signal input terminal of the first stage gate drive circuit unit for providing the first pulse signal V to the first stage gate drive circuit unit_I1(ii) a A second signal start line STV2 is coupled to the first signal input terminal of the second stage gate drive circuit unit for providing a first pulse signal V to the second stage gate drive circuit unit_I1(ii) a The signal output end of the ith-level gate driving circuit unit is respectively coupled to the second signal input end of the (i-2) th-level gate driving circuit unit and the first signal input end of the (i + 2) th-level gate driving circuit unit, and i is an integer greater than or equal to 3; the signal output end of the first-stage grid electrode driving circuit unit is coupled to the first signal input end of the third-stage grid electrode driving circuit unit; the signal output end of the second stage grid driving circuit unit is coupled to the first signal input end of the fourth stage grid driving circuit unit. The signal output end of each stage of grid drive circuit unit is also used for providing a grid scanning signal V_G ⁿWherein V is_G ⁿIs a gate scan signal of the nth stage gate driving circuit unit.

Low level line l-V_LLow level line l-V_LA low level terminal coupled to each stage of gate drive circuit unit for providing low level signal V to each stage of gate drive circuit unit_L。

Control signal line l-V_CTRControl signal line l-V_CTRFor transmitting control signal V to gate drive circuit_CTR。

Referring to fig. 5, a diagram of gate scan signals output by the 1 st-4 th stage gate driving circuit unit of the gate driving circuit of the present embodiment in the forward scan mode is shown. Corresponding to the clock signals overlapped in pairs, the output signals of the adjacent gate driving circuits are overlapped in pairs. In the forward scanning mode, the phase sequence of the output signals is as follows: v_G ¹、V_G ²、V_G ³、V_G ⁴(ii) a Correspondingly, in the reverse scanning mode, the phase sequence of the output signals is as follows: v_G ⁴、V_G ³、V_G ²、V_G ¹. Odd-numbered line signals V on one side of the panel regardless of the forward or reverse scan mode_G ¹、V_G ³Are non-overlapping; even row signal V on the other side of the panel_G ²、V_G ⁴Nor overlapping. The gate scanning signals output by the other gate driving circuit units can also be analyzed and obtained by a similar method.

Fig. 6 is a diagram of gate scan signals output by the 1 st to 4 th stage gate driving circuit units in the scanning stage and the non-scanning stage of the gate driving circuit of the embodiment under the reverse scan mode. In the control signal V_CTRWhen the voltage is low, the grid drive circuit is in a scanning stage, and grid scanning signals are sequentially output to be V in a reverse scanning mode_G ⁴、V_G ³、V_G ²、V_G ¹(ii) a Accordingly, in the forward direction scan mode, the gate scan signals are sequentially outputted as V_G ¹、V_G ²、V_G ³、V_G ⁴. In the control signal V_CTRWhen the voltage is high level, the grid drive circuit is in a non-scanning stage, and output signals of the grid drive circuit units at all levels are all low level.

Example three:

the difference between the gate driving circuit disclosed in this embodiment and the second embodiment is that the gate driving circuit unit of the intermediate stage has a simplified circuit structure.

Referring to fig. 7, fig. 7 is a circuit diagram of an nth stage gate driving circuit unit, where N is an integer and 2< N-1. A particularly simplified structure consists in a first input module 1 and a second input module 2, wherein:

the first input module 1 comprises a first switching transistor T11, a control electrode (e.g. gate) of a first switching transistor T11Coupled to the first signal input terminal for inputting the first pulse signal V_I1(ii) a A first pole (e.g. drain) for inputting the fourth clock signal V_D(ii) a The second pole is coupled to the driving control terminal Q.

The second input module 2 comprises a second switch transistor T14, a control electrode (e.g. gate) of the second switch transistor T14 is coupled to the first signal input terminal for inputting the second pulse signal V_I2(ii) a A first pole (e.g. drain) for inputting a second clock signal V_B(ii) a The second pole is coupled to the driving control terminal Q.

Compared with the second embodiment, the nth gate driving circuit unit of the present embodiment reduces the number of cascaded switching transistors (T11, T14), and also reduces the fifteenth transistor T15 and the sixteenth transistor T16, and in the present embodiment, the nth gate driving circuit unit does not need to input the control signal V any more_CTR. It will be understood by those skilled in the art that the first and second signal input terminals and other signals (terminals) of the nth stage gate driving circuit unit are connected in the same manner as the embodiment.

The simplified circuit structure is based on the following physical facts that whether each stage of gate driving circuit unit works in a forward scanning mode or a reverse scanning mode depends on the signal output of the adjacent stage of gate driving circuit unit according to the characteristics of the gate driving circuit for scanning stage by stage. Whether the gate driving circuit starts to work or not is determined by the first-stage gate driving circuit unit or the last-stage gate driving circuit unit. Therefore, the control signal V does not need to be additionally added to the nth stage gate drive circuit unit_CTRThe nth stage gate driving circuit unit can start the corresponding scanning mode only by waiting for the excitation of the adjacent stage gate driving circuit unit.

Example four:

according to the physical fact stated in the third embodiment, the forward/reverse scan mode of the gate driving circuit is determined to be the first stage/last stage gate driving circuit unit. The present embodiment discloses another simplified gate driving circuit.

The gate driving circuit disclosed in this embodiment is different from the above embodiments in that the first-stage (1 st stage and 2 nd stage) gate driving circuit unit adopts a simplified circuit structure, specifically, adopts a first gate driving circuit unit structure.

Referring to fig. 8, fig. 8 is a circuit structure diagram of the gate driving circuit units of the 1 st and 2 nd stages, which is specifically simplified in that the second input module 2 includes a second switching transistor T14, and a control electrode (e.g., a gate electrode) of the second switching transistor T14 is coupled to the second signal input terminal for inputting the second pulse signal V_I2(ii) a A first pole (e.g. drain) for inputting a second clock signal V_B(ii) a The second pole is coupled to the driving control terminal Q. Compared with the above embodiments, the 1 st and 2 nd gate driving circuit units of this embodiment have the advantages of reducing the number of the cascaded second switching transistors T14 and the sixteenth switching transistor T16, and in this embodiment, the second input module 2 of the 1 st and 2 nd gate driving circuit units does not need to input the control signal V any more_CTR. It will be understood by those skilled in the art that the first and second signal input terminals and other signals (terminals) of the stage 1 and stage 2 gate driving circuit units are connected in the same manner as the other embodiments.

In another embodiment, the difference from the above embodiments is that the gate driving circuit units of the last stages (the N-1 th stage and the N-th stage) adopt a simplified circuit structure, specifically, adopt a second gate driving circuit unit structure.

Referring to fig. 9, fig. 9 is a circuit structure diagram of the nth-1 and nth gate driving circuit units, and the simplified structure is that the first input module 1 includes a first switching transistor T11, and a control electrode (e.g., a gate electrode) of the first switching transistor T11 is coupled to the first signal input terminal for inputting the first pulse signal V_I1(ii) a A first pole (E.g., drain) for inputting the fourth clock signal V_D(ii) a The second pole is coupled to the driving control terminal Q. Compared with the above embodiments, the N-1 th and nth gate driving circuit units of this embodiment reduce the number of the cascaded first switching transistors T11 and the fifteenth transistor T15, and in this embodiment, the first input module 2 of the N-1 th and nth gate driving circuit units does not need to input the control signal V any more_CTR. It will be understood by those skilled in the art that the first and second signal input terminals and other signals (terminals) of the gate driving circuit units of the nth-1 st and nth stages are connected in the same manner as those of the other embodiments.

The two simplified modes disclosed in the embodiment are based on the following basis:

in the forward scanning mode, the first input module 1 of the first stage gate drive circuit unit plays a role in exciting the gate drive circuit to start working, and each stage only needs to respond to the output pulse drive signal V of the previous stage_OThe work of the current-stage grid drive circuit unit can be started; the second input module 2 of the tail gate drive circuit unit is used for finishing the work of the gate drive circuit, and the second pulse signal V is carried out along with the second pulse signal V of the tail gate drive circuit unit_I2Marks the end of the forward scan mode of the gate driver circuit.

In the reverse scanning mode, the second input module 2 of the tail stage grid drive circuit unit plays a role in exciting the grid drive circuit to start working, and each stage only needs to respond to the output pulse drive signal V of the next stage_OThe work of the current-stage grid drive circuit unit can be started; the first input module 1 of the first gate drive circuit unit is used for finishing the work of the gate drive circuit, and the first input module follows the first pulse signal V of the first gate drive circuit unit_I1Marks the end of the reverse scan mode of the gate driver circuit.

Therefore, no matter in the forward scanning mode or the reverse scanning mode, in the practical application process, only the first input module 1 and the last stage gate driving circuit of the first stage gate driving circuit unit are neededThe unit second input module 2 inputs a control signal V_CTRAnd (5) controlling.

Example five:

fig. 10 is a structural diagram of a display according to the present embodiment.

The display panel 100, the display panel 100 includes a two-dimensional pixel array composed of a plurality of two-dimensional pixels, and a plurality of gate scan lines in a first direction (e.g., a transverse direction) and a plurality of data lines in a second direction (e.g., a longitudinal direction) connected to each pixel. The pixels in the same row of the pixel array are connected to the same grid scanning line, and the pixels in the same column of the pixel array are connected to the same data line. The display panel 100 may be a liquid crystal display panel, an organic light emitting display panel, an electronic paper display panel, or the like, and the corresponding display device may be a liquid crystal display, an organic light emitting display, an electronic paper display, or the like.

The gate driving circuit 200, wherein the signal output terminal of the gate driving circuit unit in the gate driving circuit 200 is coupled to the corresponding gate scanning line in the display panel 100 for scanning the pixel array line by line, and the gate driving circuit 200 may be connected to the display panel 100 by soldering or integrated in the display panel 100. The gate driving circuit 200 adopts the gate driving circuit provided by the above-mentioned embodiment.

The timing generation circuit 300 is used for generating various control signals required by the gate driving circuit 200.

And a data driving circuit 400 for generating an image data signal and outputting the image data signal to a corresponding data line in the display panel 100, and transmitting the image data signal to a corresponding pixel unit through the data line to realize image gray scale.

Example six:

in the above embodiment, the first input module 1 and/or the second input module 2 are improvements of the present application, and the key point is that a logic control terminal is additionally introduced on the basis of an existing input module, so as to form a logic transmission circuit. In this embodiment, the logic transmission circuit is described separately, please refer to fig. 11, and the structure of the logic transmission circuit includes:

a first logic signal input terminal for inputting a first logic control signal V₁。

A second logic signal input terminal for inputting a second logic control signal V₂。

A transmission signal input terminal for inputting a transmission signal V_in。

And a signal following end.

At least one switching transistor T01 in cascade, at least one switching transistor T01 in cascade coupled between the first logic signal input terminal and the signal follower terminal, a first pole (e.g., drain) of the first switching transistor T01 for inputting the transmission signal, a second pole (e.g., source) of the last switching transistor T01 coupled to the signal follower terminal, and a control pole (e.g., gate) of each switching transistor T01 coupled to the first logic signal input terminal for inputting the first logic control signal V₁. In a specific embodiment, the number of the cascaded at least one switching transistor T01 may be 2.

A first control transistor T21, a control electrode (e.g., gate) of the first control transistor T21 coupled to the second logic signal input terminal for inputting a second logic control signal V₂A first pole (e.g. drain) coupled to a second pole (e.g. source) of the first-stage switching transistor T01, and a second pole (e.g. source) of the first control transistor for coupling to the low-level terminal for inputting the low-level voltage V_L。

The first control transistor T21 is responsive to the second logic control signal V₂When the circuit is disconnected: when the first logic control signal V₁When active, the cascaded switching transistor T01 is turned on to transmit the signal V_inApplied to signal followerPotential V of terminal, i.e. signal follower terminal_QFollowing the changes in the transmitted signal. The first control transistor T21 is responsive to the second logic control signal V₂When turned on, the second pole (e.g., source) of the first stage switching transistor T01 is coupled to the low level terminal.

In one embodiment, when the first control transistor T21 is an N-channel type transistor, the second logic control signal V is applied₂When high, the first control transistor T21 is turned on; when the second logic control signal V₂When low, the first control transistor T21 is turned off. In other embodiments, the first control transistor T21 can also be other types of transistors, and the second logic control signal V can be corresponding₂The logical control relationship of (c) will also change as the response occurs. Further, in another embodiment, a logical not gate may be added to the control electrode (e.g., the gate) of the first control transistor T21, so as to implement a logical not operation.

In one embodiment, when the cascaded switching transistor T01 is an N-channel type transistor, the first logic control signal V₁Is high, and similarly, in other embodiments, the cascaded switching transistor T01 may also be another type of transistor, and the corresponding first logic control signal V₁Will also change as the response occurs.

The logic transmission circuit of the embodiment can realize logic operation such as multi-input logical AND, multi-input logical OR, logical NOT gate and the like, has small dependence on the channel width-length ratio of the transistor, has small amplitude loss of output high level or low level, and has simple circuit structure.

The logic transmission circuit of this embodiment can be applied to other circuits besides the gate driving circuit, and as shown in fig. 12 and 13, other applications of the logic transmission circuit of this embodiment are also possible.

Referring to fig. 12, the logic transmission circuit further includes a second control transistor T22, specifically: second control transistorA first pole (e.g., drain) of the T22 is coupled to the signal follower terminal, a second pole (e.g., source) is coupled to the low level terminal, and a control pole (e.g., gate) is used for inputting a non-signal of the first logic control signal

In this embodiment, when the first logic control signal V₁Is high level; the first control transistor T21 is an N-channel transistor, and the second logic control signal V₂Is high, at a second logic control signal V₂Before being input to the control electrode (e.g., gate) of the first control transistor T21, the operation is not performed. In other embodiments, the first control transistor T21 may be a P-channel transistor, and the second logic control signal V may be a P-channel transistor₂The input to the control electrode (e.g., gate) of the first control transistor T21 need not be negated.

When the first logic control signal V₁And a second logic control signal V₂At the same time, when the active level is reached, the cascaded switch transistor T01 is turned on, the first control transistor T21 and the second control transistor T22 are turned off, and the transmission signal V is transmitted_inPotential V applied to signal follower, i.e. signal follower_QFollowing the transmission signal V_inIs changed, e.g. when V is changed_inAt high level, V_QIs high level, otherwise, V_QIs low.

When the first logic control signal V₁When the voltage level is inactive, the second control transistor T22 is turned on to couple the signal follower terminal to the low level terminal, and the voltage V of the signal follower terminal is set_QKept at a low level V_L。

When the second logic control signal V₂At the inactive level, the first control transistor T21 is turned on to couple the second pole (e.g., source) of the first switch transistor T01 to the low terminal.

Circuit structure adopting the embodimentThe first logic control signal V can be realized₁And a second logic control signal V₂Only when the first logic control signal V is asserted₁And a second logic control signal V₂While being active, will transmit signal V_inApplied to the signal follower terminal.

Referring to fig. 13, a circuit for implementing the logical exclusive-or operation using the circuit of fig. 11 is disclosed, which includes a first sub-module 81 and a second sub-module 82, both of which use the logic transmission circuit shown in fig. 13.

Wherein the transmission signal input ends of the two sub-modules are connected in parallel and used for inputting a transmission signal V_in(ii) a The signal following ends of the two sub-modules are connected in parallel and used for following transmission signals; the logic control signals input to the first logic signal input terminals of the first submodule 81 and the second submodule 82 are opposite, for example, the logic control signals input to the first logic signal input terminal of the first submodule 81The first logic signal input of the second submodule 82 is input V₁(ii) a The logic control signals input to the second logic signal input terminals of the first submodule 81 and the second submodule 82 are opposite, for example, the logic control signals input to the second logic signal input terminal of the first submodule 81A second logic signal input terminal of the second submodule 82 inputs V₂。

Through this circuit, realized logic transmission circuit of logic exclusive OR operation:

wherein,is an exclusive OR operation, i.e.

The above formula shows that when V₁And V₂When the level of (A) is the same, e.g. high or low, V_QIs low level;

when V is₁And V₂When the levels of (A) are different, V_QFollowing V_inMay vary.

In the embodiment, the simple shunting voltage-controlled circuit structure is adopted to realize the exclusive-or logic, so that the defects of the logic based on the inverter are overcome: such as a large dependence on the channel width-to-length ratio of the transistor, a large amplitude loss at a high level or a low level of output, and the like.

The foregoing is a more detailed description of the present invention that is presented in conjunction with specific embodiments, and the practice of the invention is not to be considered limited to those descriptions. It will be apparent to those skilled in the art that a number of simple derivations or substitutions can be made without departing from the inventive concept.

Claims

1. A gate drive circuit unit, comprising:

a first signal input terminal for inputting a first pulse signal (V)_I1)；

A second signal input terminal for inputting a second pulse signal (V)_I2)；

A first clock signal input terminal for inputting a first clock signal (V)_A)；

A signal output terminal for outputting a pulse drive signal (V)_O)；

A drive module (3) which drivesA movable module (3) coupled between the first clock signal input and the signal output for applying a first clock signal (V) after a drive voltage is obtained at a drive control terminal (Q) thereof_A) To a signal output when said first clock signal (V)_A) When the voltage is at a high level, the driving module (3) pulls up and charges the signal output end; when the first clock signal (V)_A) When the voltage is low, the driving module (3) is used for outputting a signal (V)_O) Pulling down for discharging;

a low level maintaining module (5), wherein the low level maintaining module (5) is coupled between the signal output end and the low level end; the low level maintaining module (5) is responsive to a first clock signal (V)_A) High level signal or third clock signal (V)_C) The high level signal couples the signal output end to the low level end and maintains the low level potential of the signal output end;

a second input module (2), the second input module (2) comprising a cascade of at least one second switching transistor (T14), the cascade of at least one second switching transistor (T14) being coupled between the second signal input terminal and the drive control terminal (Q), a first pole of a first stage second switching transistor (T14) being for inputting a second clock signal (Vclock)_B) A second pole of the second switching transistor (T14) of the tail stage is coupled to the driving control terminal (Q), and a control pole of each second switching transistor (T14) is coupled to the second signal input terminal for inputting the second pulse signal (V)_I2) (ii) a In the reverse scan mode, the second input module (2) is responsive to a second pulse signal (V)_I2) And a second clock signal (V)_B) Charging the drive control terminal (Q) with the high level overlap period signal; in the forward direction scanning mode, the second pulse signal (V)_I2) And a second clock signal (V)_B) When the voltage is respectively at a high level and a low level, the second input module (2) discharges the drive control end (Q);

a first input module (1), the first input module (1) comprising a cascade of at least one first switching transistor (T11), the cascade of at least one first switching transistor (T11) being coupled between the first signal input terminal and the drive control terminal (Q), a first pole of a first switching transistor (T11) of a first stage being for inputting a fourth switching transistor (T11)Clock signal (V)_D) A second pole of the first switching transistor (T11) of the tail stage is coupled to the driving control terminal (Q), and a control pole of each first switching transistor (T11) is coupled to the first signal input terminal for inputting the first pulse signal (V)_I1) (ii) a In the forward direction scanning mode, the first input module (1) is responsive to a first pulse signal (V)_I1) And a fourth clock signal (V)_D) Charging the drive control terminal (Q) with the high level overlap period signal; in the reverse scan mode, a first pulse signal (V)_I1) And a fourth clock signal (V)_D) When the voltage is respectively high level and low level, the first input module (1) discharges the drive control end (Q);

the first input module (1) further comprises a fifteenth transistor (T15), a control electrode of the fifteenth transistor (T15) is used for inputting a control signal (V)_CTR) A first pole coupled to a second pole of a first switching transistor (T11) of a first stage, the second pole coupled to the low terminal; the fifteenth transistor (T15) is in the control signal (V)_CTR) Coupling the second pole of the first switching transistor (T11) of the first stage to the low terminal under the control of the high signal_CTR) The fifteenth transistor (T15) is switched off under the control of a low-level signal;

a first clock signal (V)_A) And a third clock signal (V)_C) Complementation;

wherein the number of first switching transistors (T11) of the first input module (1) cascade is at least 2, and/or the number of second switching transistors (T14) of the second input module (2) cascade is at least 2.

2. A gate drive circuit unit, comprising:

a first signal input terminal for inputting a first pulse signal (V)_I1)；

A second signal input terminal for inputting a second pulse signal (V)_I2)；

A signal output terminal for outputting a pulse drive signal (V)_O)；

A driving module (3), said driving module (3) being coupled between said first clock signal input and said signal output, for applying a first clock signal (V) after a driving voltage is obtained at a driving control terminal (Q) thereof_A) To a signal output when said first clock signal (V)_A) When the voltage is at a high level, the driving module (3) pulls up and charges the signal output end; when the first clock signal (V)_A) When the voltage is low, the driving module (3) is used for outputting a signal (V)_O) Pulling down for discharging;

a first input module (1), the first input module (1) comprising a cascade of at least one first switching transistor (T11), the cascade of at least one first switching transistor (T11) being coupled between the first signal input terminal and the drive control terminal (Q), a first pole of a first switching transistor (T11) for inputting a fourth clock signal (Vv)_D) A second pole of the first switching transistor (T11) of the tail stage is coupled to the driving control terminal (Q), and a control pole of each first switching transistor (T11) is coupled to the first signal input terminal for inputting the first pulse signal (V)_I1) (ii) a In the forward direction scanning mode, the first input module (1) is responsive to a first pulse signal (V)_I1) And a fourth clock signal (V)_D) Charging the drive control terminal (Q) with the high level overlap period signal; in the reverse scan mode, a first pulse signal (V)_I1) And a fourth clock signal (V)_D) When the voltage is respectively high level and low level, the first input module (1) discharges the drive control end (Q);

a second input module (2), the second input module (2) comprising a cascade of at least one second switching transistor (T14), the cascade of at least one second switching transistor (T14) being coupled between the second signal input terminal and the drive control terminal (Q) firstA first pole of a second switch transistor (T14) is used for inputting a second clock signal (V)_B) A second pole of the second switching transistor (T14) of the last stage is coupled to the drive control terminal (Q) and a control pole of each second switching transistor (T14) is coupled to the second signal input terminal for inputting a second pulse signal (V)_I2) (ii) a In the reverse scan mode, the second input module (2) is responsive to a second pulse signal (V)_I2) And a second clock signal (V)_B) Charging the drive control terminal (Q) with the high level overlap period signal; in the forward direction scanning mode, the second pulse signal (V)_I2) And a second clock signal (V)_B) When the voltage is respectively at a high level and a low level, the second input module (2) discharges the drive control end (Q);

the second input module (2) further comprises a sixteenth transistor (T16), a control electrode of the sixteenth transistor (T16) being used for inputting a control signal (V)_CTR) A first pole coupled to a second pole of a first-stage second switching transistor (T14), the second pole coupled to the low-level terminal; the sixteenth transistor (T16) is in the control signal (V)_CTR) Coupling the second pole of the first stage second switching transistor (T14) to the low terminal under the control of the high signal_CTR) The sixteenth transistor (T16) is switched off under the control of the low-level signal;

a first clock signal (V)_A) And a third clock signal (V)_C) Complementation;

3. A gate drive circuit unit as claimed in claim 1, characterized in that the second input block (2) further comprises a sixteenth transistor (T16), the control electrode of the sixteenth transistor (T16) being for inputting a control signal (V)_CTR) A first pole coupled to a second pole of a first-stage second switching transistor (T14), the second pole coupled to the low-level terminal; the sixteenth transistor (T16) is in the control signal (V)_CTR) Under the control of high level signal, the first stage isThe second pole of the two switching transistors (T14) is coupled to the low level terminal at the control signal (V)_CTR) The sixteenth transistor (T16) is turned off under the control of the low level signal.

4. A gate drive circuit unit as claimed in any one of claims 1 to 3, characterized in that the number of first switching transistors (T11) cascaded by the first input module (1) is 2.

5. A gate drive circuit unit as claimed in any one of claims 1 to 3, characterized in that the number of second switching transistors (T14) cascaded by the second input block (2) is 2.

6. A gate drive circuit unit as claimed in any one of claims 1 to 3, characterized in that the first pulse signal (V)_I1) And said second pulse signal (V)_I2) Spaced by one clock signal period; second clock signal (V)_B) And a fourth clock signal (V)_D) Complementation;

in the forward direction scan mode, the fourth clock signal (V)_D) Lags behind the first pulse signal (V)_I1) One phase, the first clock signal (V)_A) Lags the fourth clock signal (V)_D) A phase;

in the reverse scan mode, the second clock signal (V)_B) Lags behind the second pulse signal (V)_I2) One phase, the fourth clock signal (V)_D) Lags behind the first clock signal (V)_A) A phase;

the one phase is T/4, and T is the period of the clock signal.

7. A gate drive circuit comprising: n cascaded gate drive circuit units, wherein N is an integer greater than 1; the gate driving circuit unit according to claim 1 or 3 is adopted in the first stage; the tail stage employs the gate driving circuit unit as claimed in claim 2.

8. A display, comprising:

the display device comprises a display panel (100), wherein a gate line in a first direction and a data line in a second direction are manufactured on the display panel;

the gate driver circuit (200) of claim 7, wherein the signal output of a gate driver cell in the gate driver circuit (200) is coupled to its corresponding gate line;

a timing generation circuit (300) for generating various control signals required by the gate driving circuit (200);

and the data driving circuit (400) is used for generating an image data signal and outputting the image data signal to a corresponding data line in the display panel (100).

9. A logic transmission circuit, comprising:

a first logic signal input terminal for inputting a first logic control signal;

a second logic signal input terminal for inputting a second logic control signal;

a transmission signal input terminal for inputting a transmission signal;

a signal following end;

a second control transistor;

at least one cascaded switching transistor, the cascaded switching transistor being coupled between the first logic signal input terminal and the signal follower terminal, a first pole of the first switching transistor being used for inputting a transmission signal, a second pole of the last switching transistor being coupled to the signal follower terminal, and a control pole of each switching transistor being coupled to the first logic signal input terminal for inputting a first logic control signal;

a first control transistor, a control electrode of which is coupled to the second logic signal input terminal for inputting a second logic control signal, a first electrode of which is coupled to the second electrode of the first stage switching transistor, and a second electrode of which is coupled to the low level terminal, wherein when the first control transistor is turned off in response to the second logic control signal and the cascaded switching transistors are turned on in response to the first logic control signal, a transmission signal is applied to the signal follower terminal, and when the first control transistor is turned on in response to the second logic control signal, the second electrode of the first stage switching transistor is coupled to the low level terminal;

the first pole of the second control transistor is coupled to the signal following end, the second pole of the second control transistor is used for being coupled to the low-level end, and the control pole of the second control transistor is used for inputting a non-signal of the first logic control signal;

when the first logic control signal and the second logic control signal are at effective levels at the same time, the cascaded switch transistors are switched on, the first control transistor and the second control transistor are switched off, and a transmission signal is applied to the signal following end;

when the first logic control signal is at an invalid level, the second control transistor is conducted to couple the signal following end to the low level end;

when the second logic control signal is at an inactive level, the first control transistor is turned on to couple the second pole of the first switch transistor to the low-level terminal.