CN103825488A - Dual-output single-phase six-switch block MMC inverter and control method thereof - Google Patents
Dual-output single-phase six-switch block MMC inverter and control method thereof Download PDFInfo
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- CN103825488A CN103825488A CN201410042070.3A CN201410042070A CN103825488A CN 103825488 A CN103825488 A CN 103825488A CN 201410042070 A CN201410042070 A CN 201410042070A CN 103825488 A CN103825488 A CN 103825488A
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Abstract
本发明公开了双输出单相六开关组MMC逆变器及其控制方法。本发明的逆变器包括直流电源、第一桥臂、第二桥臂、第一负载和第二负载；所述第一桥臂和第二桥臂均由上开关组、中开关组、下开关组和耦合电感串联而成；第一负载的两端分别接到第一桥臂的中开关组和第二桥臂的中开关组的上端，第二负载的两端分别接到第一桥臂的中开关组和第二桥臂的中开关组的下端。该逆变器采用载波移相PWM控制，具有两路2N+1电平的交流输出，功率开关单元中每个开关管承受的电压应力仅为直流电源电压的1/N，适合于高压、大功率、双负载的场合。第一桥臂的耦合电感原副边和第二桥臂的耦合电感的原、副边均可由第一电感和第二电感两个独立电感替代。
The invention discloses a dual-output single-phase six-switch group MMC inverter and a control method thereof. The inverter of the present invention includes a DC power supply, a first bridge arm, a second bridge arm, a first load and a second load; the first bridge arm and the second bridge arm are composed of an upper switch group, a middle switch group, a lower The switch group and the coupled inductor are connected in series; the two ends of the first load are respectively connected to the upper ends of the middle switch group of the first bridge arm and the middle switch group of the second bridge arm, and the two ends of the second load are respectively connected to the first bridge The middle switch group of the arm and the lower end of the middle switch group of the second bridge arm. The inverter adopts carrier phase-shift PWM control, has two 2N+1 level AC outputs, and the voltage stress of each switch tube in the power switch unit is only 1/N of the DC power supply voltage, suitable for high voltage, large power, double load occasions. The primary and secondary sides of the coupled inductor of the first bridge arm and the primary and secondary sides of the coupled inductor of the second bridge arm can be replaced by two independent inductors, the first inductor and the second inductor.
Description
Technical field
The present invention relates to module and combine many level (MMC) converter field, be specifically related to single-phase six switches set MMC inverter and the control methods thereof of a kind of dual output.
Background technology
, under this trend, there is the direction of two kinds of improvement converters: reduce passive device or improve converter topology structure to reduce active device as the new development that reduces active device direction at present power inverter forward miniaturization, high reliability and low-loss future development.Single-phase six switch converters have reduced a switch and corresponding drive circuit with respect to eight traditional switch converters, in the application of considering cost and volume, occupy certain advantage.But the single-phase output of two-way of six switch converters is two level, output AC waveform is poor.In addition, the half that the voltage stress that in six switches, each switch bears is DC bus-bar voltage, and the voltage-sharing of six switches of existence, this has limited the application of single-phase six switch converters in high pressure and large-power occasions greatly.
In recent years, multilevel technology is constantly promoted, and successful Application is at the industrial circle such as such as high voltage direct current transmission, Electric Drive, active power filtering, static synchroballistic, common voltage-type multi-level converter topology is broadly divided into case bit-type and the large class of unit cascaded type two at present.Module combination multi-level converter (Modular Multilevel Converter, MMC) as a kind of novel many level topology, except having advantages of traditional multi-level converter, module combination multi-level converter adopts Modular Structure Design, is convenient to System Expansion and redundancy of effort; Have unbalanced operation ability, fault traversing and recovery capability, system reliability is high; Owing to having common DC bus, module combination multi-level converter is particularly useful for HVDC (High Voltage Direct Current) transmission system application.But, in the time of the alternating current circuit of two different frequencies connected, needing 2 MMC converters, this has increased engineering cost greatly.
Summary of the invention
The object of the invention is to overcome above-mentioned the deficiencies in the prior art, propose single-phase six switches set MMC inverter and the control methods thereof of a kind of dual output.
The technical solution used in the present invention is as follows.
The single-phase six switches set MMC inverters of dual output comprise DC power supply, the first brachium pontis, the second brachium pontis, the first load and the second load; Described the first brachium pontis and the second brachium pontis are in series by upper switches set, middle switches set, lower switches set and coupling inductance; The upper switches set of the first brachium pontis is in series by N power switch unit, the middle switches set of the first brachium pontis is in series by N power switch unit, the lower switches set of the first brachium pontis is in series by N power switch unit, the upper switches set of the second brachium pontis is in series by N power switch unit, the middle switches set of the second brachium pontis is in series by N power switch unit, and the lower switches set of the second brachium pontis is in series by N power switch unit; The upper end of the middle switches set of the first brachium pontis and the middle switches set of the second brachium pontis is received respectively at the two ends of the first load, and the lower end of the middle switches set of the first brachium pontis and the middle switches set of the second brachium pontis is received respectively at the two ends of the second load; Export as the first via at the two ends of the first load, and export as the second tunnel at the two ends of the second load.The former and deputy limit of the former secondary of coupling inductance of the first brachium pontis and the coupling inductance of the second brachium pontis all can be substituted by the first inductance and two separate inductors of the second inductance.
Further, in the single-phase six switches set MMC inverters of described dual output, the upper end of the upper end of the positive pole of DC power supply and the upper switches set of the first brachium pontis, the upper switches set of the second brachium pontis is connected, and the lower end of the lower end of the negative pole of DC power supply and the lower switches set of the first brachium pontis, the lower switches set of the second brachium pontis is connected; The lower end of the upper switches set of the first brachium pontis is connected with the Same Name of Ends on the former limit of the coupling inductance of the first brachium pontis, the non-same polarity on the former limit of the coupling inductance of the first brachium pontis is connected with the upper end of the middle switches set of the first brachium pontis, the lower end of the middle switches set of the first brachium pontis is connected with the Same Name of Ends of the coupling inductance secondary of the first brachium pontis, and the non-same polarity of the coupling inductance secondary of the first brachium pontis is connected with the upper end of the switches set of the first brachium pontis; The structure of the structure of the second brachium pontis and the first brachium pontis is in full accord; The lower end of the lower end of the negative pole of DC power supply and the lower switches set of the first brachium pontis, the lower switches set of the second brachium pontis, hold and be connected; One end of the first load is connected with the upper end of the middle switches set of the first brachium pontis, the other end of the first load is connected with the upper end of the middle switches set of the second brachium pontis, one end of the second load is connected with the lower end of the middle switches set of the first brachium pontis, and the other end of the second load is connected with the lower end of the middle switches set of the second brachium pontis.
Further, power switch unit comprises the first switching tube, second switch pipe, the first diode, the second diode and electric capacity.Wherein, the positive pole of electric capacity is connected with the collector electrode of the first switching tube, the negative electrode of the first diode, the emitter of the first switching tube is connected with the anode of the first diode, the collector electrode of second switch pipe, the negative electrode of the second diode, and the emitter of second switch pipe is connected with the anode of the second diode, the negative pole of electric capacity; The collector electrode of second switch pipe is as the first output, and the emitter of second switch pipe is as the second output.
The second output of i power switch unit of each switches set is connected with the first output of i+1 power switch unit, and wherein the value of i is 1～N-1.
The control method of above-mentioned inverter comprises: adopt phase-shifting carrier wave PWM to control the opening and turn-offing of switching tube of each switches set; I power switch unit of i power switch unit of i power switch unit of i power switch unit of the upper switches set of the first brachium pontis, the lower switches set of the first brachium pontis, the upper switches set of the second brachium pontis and the lower switches set of the second brachium pontis adopts identical triangular wave as i carrier wave C
i, wherein the value of i is 1～N; N carrier wave 360 °/N of lagging phase angle successively; The upper switches set of the first brachium pontis adopts primary sinusoid R
a1the first direct current biasing R superposes
doaas the first modulating wave R of the first brachium pontis
a1+ R
doa, the lower switches set of the first brachium pontis adopts the second sinusoidal wave R
b1the second direct current biasing R superposes
dobas the second modulating wave R of the first brachium pontis
b1+ R
dob, the upper switches set of the second brachium pontis adopts the 3rd sinusoidal wave R
a2the first direct current biasing R superposes
doaas the first modulating wave R of the second brachium pontis
a2+ R
doa, the lower switches set of the second brachium pontis adopts the 4th sinusoidal wave R
b2the second direct current biasing R superposes
dobas the second modulating wave R of the second brachium pontis
b2+ R
dob; Primary sinusoid R
a1with the 3rd sinusoidal wave R
a2the identical and phase difference of frequency be 180 °, the second sinusoidal wave R
b1with the 4th sinusoidal wave R
b2the identical and phase difference of frequency be 180 °.
In above-mentioned control method, the first modulating wave R of the first brachium pontis
a1+ R
doawith i carrier wave C
iobtain the control level of the second switch pipe gate pole of i power switch unit of the upper switches set of the first brachium pontis by the first comparator, as the first modulating wave modulating wave R of the first brachium pontis
a1+ R
doabe greater than i carrier wave C
itime, the first comparator output high level, as the first modulating wave modulating wave R of the first brachium pontis
a1+ R
doabe less than i carrier wave C
itime, the first comparator output low level, wherein the value of i is 1～N; The second modulating wave R of the first brachium pontis
b1+ R
dobwith i carrier wave C
iobtain the control level of the second switch pipe gate pole of i power switch unit of the lower switches set of the first brachium pontis by the second comparator, as the second modulating wave R of the first brachium pontis
b1+ R
dobbe less than i carrier wave C
itime, the second comparator output high level, as the second modulating wave R of the first brachium pontis
b1+ R
dobbe greater than i carrier wave C
itime, the second comparator output low level; The control level of the second switch pipe gate pole of the control level of second switch pipe gate pole of i power switch unit of the upper switches set of the first brachium pontis and i power switch unit of the lower switches set of the first brachium pontis obtains the control level of second switch pipe gate pole in i the power switch unit of middle switches set of the first brachium pontis by the first XOR gate; The first modulating wave R of the second brachium pontis
a2+ R
doawith i carrier wave C
iobtain the control level of second switch pipe gate pole in i the power switch unit of upper switches set of the second brachium pontis by the 3rd comparator, as the first modulating wave R of the second brachium pontis
a2+ R
doabe greater than i carrier wave C
itime, the 3rd comparator output high level, as the first modulating wave R of the second brachium pontis
a2+ R
doabe less than i carrier wave C
itime, the 3rd comparator output low level; The second modulating wave R of the second brachium pontis
b2+ R
dobwith i carrier wave C
iobtain the control level of the second switch pipe gate pole of i power switch unit of switches set under the second brachium pontis by the 4th comparator, as the second modulating wave R of the second brachium pontis
b2+ R
dobbe less than i carrier wave C
itime, the 4th comparator output high level, as the second modulating wave R of the second brachium pontis
b2+ R
dobbe greater than i carrier wave C
itime, the 4th comparator output low level; In i power switch unit of the upper switches set of the second brachium pontis, under the control level of second switch pipe gate pole and the second brachium pontis, the control level of the second switch pipe gate pole of i power switch unit of switches set obtains the control level of the second switch pipe gate pole of i power switch unit of the middle switches set of the second brachium pontis by the second XOR gate; In each power switch unit of each switches set, the control level of second switch pipe gate pole obtains the control level of the first switching tube gate pole in this power switch unit after anti-phase.
The mode of operation of the single-phase six switches set MMC inverters of dual output comprises that, with frequency pattern (CF pattern) and alien frequencies pattern (DF pattern), in CF pattern, first via output is identical with the electric voltage frequency of the second tunnel output, and voltage magnitude is not identical; In DF pattern, first via output is all different from electric voltage frequency and the amplitude of the second tunnel output.
Compared with prior art, the advantage that the present invention has is: have two-way 2N+1 level and exchange output, output current wave is of high quality, the voltage stress that in power switch unit, each switching tube bears is only the 1/N of DC bus-bar voltage, can guarantee that the voltage that in the converter course of work, all switching tubes bear equates, has well solved the voltage-sharing of switching tube simultaneously.Compare with existing single-phase six switch converters, the two-way output of the single-phase six switches set MMC inverters of dual output provided by the present invention is 2N+1 level and exchanges output, and the quality of output AC waveform is greatly improved.In addition, the voltage stress bearing of each switching tube is only the 1/N of DC bus-bar voltage, and control method provided by the present invention equates the voltage that in the converter course of work, all switching tubes bear, well solved the voltage-sharing of switching tube, this will be very beneficial for the application of the single-phase six switches set MMC inverters of dual output in high pressure and large-power occasions.Compare with existing MMC converter, the single-phase six switches set MMC inverters of dual output provided by the present invention have two-way exchange output, can be directly used in two different frequencies alternating current circuit be connected, greatly reduce engineering cost.
Accompanying drawing explanation
Fig. 1 is the circuit structure diagram of the single-phase six switches set MMC inverters of dual output of the present invention;
Fig. 2 is the circuit structure diagram of the power switch unit of the single-phase six switches set MMC inverters of the dual output shown in Fig. 1;
Fig. 3 is the phase-shifting carrier wave PWM control structure figure of the single-phase six switches set MMC inverters of the dual output shown in Fig. 1;
Fig. 4 a, 4b are that the single-phase six switches set MMC inverters of the dual output shown in Fig. 1 work in respectively the modulating wave under CF pattern and DF pattern;
Fig. 5 a, 5b are the simulation waveform figure that the single-phase five level SS-MMC inverters of dual output work in CF pattern and DF pattern.
Embodiment
For further setting forth content of the present invention and feature, below in conjunction with accompanying drawing, enforcement of the present invention is specifically described, but enforcement of the present invention is not limited to this.
With reference to figure 1, the single-phase six switches set MMC inverters of dual output of the present invention, comprise DC power supply U
dc, the first brachium pontis, the second brachium pontis, the first load and the second load; Described the first brachium pontis and the second brachium pontis are by upper switches set (H
1, H
2), middle switches set (M
1, M
2), lower switches set (L
1, L
2) and coupling inductance (L
h1: L
l1, L
h2: L
l2) be in series; The upper switches set H of the first brachium pontis
1by N power switch unit (SM
h11, SM
h12..., SM
h1N) be in series, the middle switches set M of the first brachium pontis
1by N power switch unit (SM
m11, SM
m12..., SM
m1N) be in series, the lower switches set L of the first brachium pontis
1by N power switch unit (SM
l11, SM
l12..., SM
l1N) be in series, the upper switches set H of the second brachium pontis
2by N power switch unit (SM
h21, SM
h22..., SM
h2N) be in series, the middle switches set M of the second brachium pontis
2by N power switch unit (SM
m21, SM
m22..., SM
m2N) be in series, the lower switches set L of the second brachium pontis
2by N power switch unit (SM
l21, SM
l22..., SM
l2N) be in series; Middle switches set (the M of the first brachium pontis is received respectively at the two ends of the first load
1) and the middle switches set M of the second brachium pontis
2upper end o, the middle switches set M of the first brachium pontis is received respectively at the two ends of the second load
1middle switches set M with the second brachium pontis
2lower end p; Export as the first via at the two ends of the first load, and export as the second tunnel at the two ends of the second load.Wherein, DC power supply U
dcpositive pole and the upper switches set H of the first brachium pontis
1upper end o, the upper switches set H of the second brachium pontis
2upper end o connect, DC power supply U
dcnegative pole and the lower switches set L of the first brachium pontis
1lower end p, the lower switches set L of the second brachium pontis
2lower end p connect; The upper switches set H of the first brachium pontis
1lower end p and the coupling inductance (L of the first brachium pontis
h1: L
l1) former limit L
h1same Name of Ends w
1connect the coupling inductance (L of the first brachium pontis
h1: L
l1) former limit L
h1non-same polarity a
1middle switches set M with the first brachium pontis
1upper end o connect, the middle switches set M of the first brachium pontis
1lower end p and the coupling inductance (L of the first brachium pontis
h1: L
l1) secondary L
l1same Name of Ends b
1connect the coupling inductance (L of the first brachium pontis
h1: L
l1) secondary L
l1non-same polarity z
1switches set L with the first brachium pontis
1upper end o connect; The structure of the structure of the second brachium pontis and the first brachium pontis is in full accord; DC power supply U
dcnegative pole and the lower switches set L of the first brachium pontis
1lower end p, the lower switches set L of the second brachium pontis
2lower end p, hold n connect; The middle switches set M of one end of the first load and the first brachium pontis
1upper end o connect, the middle switches set M of the other end of the first load and the second brachium pontis
2upper end o connect, the middle switches set M of one end of the second load and the first brachium pontis
1lower end p connect, the middle switches set M of the other end of the second load and the second brachium pontis
2lower end p connect.
Fig. 2 illustrates the circuit structure of the power switch unit of the single-phase six switches set MMC inverters of the dual output shown in Fig. 1, comprises the first switching tube S
1, second switch pipe S
2, the first diode D
1, the second diode D
2and capacitor C
sM.Wherein, capacitor C
sMpositive pole and the first switching tube S
1collector electrode, the first diode D
1negative electrode connect, the first switching tube S
1emitter and the first diode D
1anode, second switch pipe S
2collector electrode, the second diode D
2negative electrode connect, second switch pipe S
2emitter and the second diode D
2anode, capacitor C
sMnegative pole connect; Second switch pipe S
2collector electrode as the first output, second switch pipe S
2emitter as the second output.
As shown in Figure 1, the second output of i power switch unit of each switches set is connected with the first output of i+1 power switch unit, and wherein the value of i is 1～N-1.
As shown in Figure 1, the voltage u at the first load two ends
avoltage u with the second load two ends
bfor
In formula, u
h1be the upper switches set H of the first brachium pontis
1output voltage, u
m1be the middle switches set M of the first brachium pontis
1output voltage, u
l1be the lower switches set L of the first brachium pontis
1output voltage, u
h2be the upper switches set H of the second brachium pontis
2output voltage, u
m2be the middle switches set M of the second brachium pontis
2output voltage, u
l2be the lower switches set L of the second brachium pontis
2output voltage.
The single-phase six switches set MMC inverters of dual output shown in Fig. 1 adopt phase-shifting carrier wave PWM to control, as shown in Figure 3.
The upper switches set H of the first brachium pontis
1i power switch unit SM
h1i, the first brachium pontis lower switches set L
1i power switch unit SM
l1i, the second brachium pontis upper switches set H
2i power switch unit SM
h2ilower switches set L with the second brachium pontis
2i power switch unit SM
l2iadopt identical triangular wave as i carrier wave C
i, wherein the value of i is 1～N; N carrier wave C
1, C
2..., C
n360 °/N of lagging phase angle successively; The upper switches set H of the first brachium pontis
1adopt primary sinusoid R
a1the first direct current biasing R superposes
doaas the first modulating wave R of the first brachium pontis
a1+ R
doa, the lower switches set L of the first brachium pontis
1adopt the second sinusoidal wave R
b1the second direct current biasing R superposes
dobas the second modulating wave R of the first brachium pontis
b1+ R
dob, the upper switches set H of the second brachium pontis
2adopt the 3rd sinusoidal wave R
a2the first direct current biasing R superposes
doaas the first modulating wave R of the second brachium pontis
a2+ R
doa, the lower switches set L of the second brachium pontis
2adopt the 4th sinusoidal wave R
b2the second direct current biasing R superposes
dobas the second modulating wave R of the second brachium pontis
b2+ R
dob; Primary sinusoid R
a1with the 3rd sinusoidal wave R
a2the identical and phase difference of frequency be 180 °, the second sinusoidal wave R
b1with the 4th sinusoidal wave R
b2the identical and phase difference of frequency be 180 °.
The first modulating wave R of the first brachium pontis
a1+ R
doawith i carrier wave C
iobtain the upper switches set H of the first brachium pontis by the first comparator
1i power switch unit SM
h1isecond switch pipe S
2the control level S of gate pole
h1i, as the first modulating wave modulating wave R of the first brachium pontis
a1+ R
doabe greater than i carrier wave C
itime, the first comparator output high level, as the first modulating wave modulating wave R of the first brachium pontis
a1+ R
doabe less than i carrier wave C
itime, the first comparator output low level, wherein the value of i is 1～N; The second modulating wave R of the first brachium pontis
b1+ R
dobwith i carrier wave C
iobtain the lower switches set L of the first brachium pontis by the second comparator
1i power switch unit SM
l1isecond switch pipe S
2the control level S of gate pole
l1i, as the second modulating wave R of the first brachium pontis
b1+ R
dobbe less than i carrier wave C
itime, the second comparator output high level, as the second modulating wave R of the first brachium pontis
b1+ R
dobbe greater than i carrier wave C
itime, the second comparator output low level; The upper switches set H of the first brachium pontis
1i power switch unit SM
h1isecond switch pipe S
2the control level S of gate pole
h1ilower switches set L with the first brachium pontis
1i power switch unit SM
l1isecond switch pipe S
2the control level S of gate pole
l1iobtain the middle switches set M of the first brachium pontis by the first XOR gate
1i power switch unit SM
m1imiddle second switch pipe S
2the control level S of gate pole
m1i; The first modulating wave R of the second brachium pontis
a2+ R
doawith i carrier wave C
iobtain the upper switches set H of the second brachium pontis by the 3rd comparator
2i power switch unit SM
h2imiddle second switch pipe S
2the control level S of gate pole
h2i, as the first modulating wave R of the second brachium pontis
a2+ R
doabe greater than i carrier wave C
itime, the 3rd comparator output high level, as the first modulating wave R of the second brachium pontis
a2+ R
doabe less than i carrier wave C
itime, the 3rd comparator output low level; The second modulating wave R of the second brachium pontis
b2+ R
dobwith i carrier wave C
iobtain switches set L under the second brachium pontis by the 4th comparator
2i power switch unit SM
l2isecond switch pipe S
2the control level S of gate pole
l2i, as the second modulating wave R of the second brachium pontis
b2+ R
dobbe less than i carrier wave C
itime, the 4th comparator output high level, as the second modulating wave R of the second brachium pontis
b2+ R
dobbe greater than i carrier wave C
itime, the 4th comparator output low level; The upper switches set H of the second brachium pontis
2i power switch unit SM
h2imiddle second switch pipe S
2the control level S of gate pole
h2iwith switches set L under the second brachium pontis
2i power switch unit SM
l2isecond switch pipe S
2the control level S of gate pole
l2iobtain the middle switches set M of the second brachium pontis by the second XOR gate
2i power switch unit SM
m2isecond switch pipe S
2the control level S of gate pole
m2i; Second switch pipe S in each power switch unit of each switches set
2after the control level of gate pole is anti-phase, obtain the first switching tube S in this power switch unit
1the control level of gate pole.
Described control method can guarantee the upper switches set H of the first brachium pontis of described inverter
1, the first brachium pontis middle switches set M
1lower switches set L with the first brachium pontis
1at the output voltage u of total N power switch unit of each moment
sM=E, the output voltage u of total 2N power switch unit
sM=0, meet u
h1+ u
m1+ u
l1=U
dc; Guarantee the upper switches set H of the second brachium pontis
2, the second brachium pontis middle switches set M
2lower switches set L with the second brachium pontis
2at the output voltage u of total N power switch unit of each moment
sM=E, the output voltage u of total 2N power switch unit
sM=0, meet u
h2+ u
m2+ u
l2=U
dc; The capacitor C of each power switch unit that wherein E is each switches set
sMvoltage, and E=U
dc/ N.
Fig. 4 a illustrates that the single-phase six switches set MMC inverters of dual output work in the first modulating wave R of the first brachium pontis under CF pattern
a1+ R
doa, the first brachium pontis the second modulating wave R
b1+ R
dobwith i carrier wave C
irelation.Can find out from Fig. 4 a, the primary sinusoid is identical with the electric voltage frequency of the second sine wave, and the voltage magnitude maximum of the primary sinusoid and the second sine wave is 1, and wherein the value of i is 1～N.Fig. 4 b illustrates that the single-phase six switches set MMC inverters of dual output work in the first modulating wave R of the first brachium pontis under DF pattern
a1+ R
doa, the first brachium pontis the second modulating wave R
b1+ R
dobwith i carrier wave C
irelation.Can find out from Fig. 4 b, the electric voltage frequency of the primary sinusoid and the second sine wave is not identical, and the voltage magnitude of the primary sinusoid and the second sine wave peaked and be 1/2.The first modulating wave R of the second brachium pontis
a2+ R
doathe first modulating wave R with the first brachium pontis
a1+ R
doawith i carrier wave C
irelation identical, the second modulating wave R of the second brachium pontis
b2+ R
dobthe second modulating wave R with the first brachium pontis
b1+ R
dobwith i carrier wave C
irelation identical.
Fig. 5 a is the simulation waveform figure that the single-phase five level six switches set MMC inverters of dual output work in CF pattern, the voltage of the first load, voltage, the electric current of the first load and the electric current of the second load of the second load successively, identical with the power frequency of the second load from visible the first load of Fig. 5 a, the current amplitude of the first load and the second load is not identical; Fig. 5 b is the simulation waveform figure that the single-phase five level six switches set MMC inverters of dual output work in DF pattern, be successively the voltage of the first load, voltage, the electric current of the first load and the electric current of the second load of the second load, all not identical from power frequency and the amplitude of visible the first load of Fig. 5 b and the second load.
Above-described embodiment is preferably execution mode of the present invention; but embodiments of the present invention are not limited by the examples; other any do not deviate from change, the modification done under Spirit Essence of the present invention and principle, substitutes, combination, simplify; all should be equivalent substitute mode, within being included in protection scope of the present invention.
Claims (8)
1. the single-phase six switches set MMC inverters of dual output, is characterized in that: comprise DC power supply (U
dc), the first brachium pontis, the second brachium pontis, the first load and the second load; Described the first brachium pontis and the second brachium pontis are by upper switches set (H
1, H
2), middle switches set (M
1, M
2), lower switches set (L
1, L
2) and coupling inductance (L
h1: L
l1, L
h2: L
l2) be in series; Upper switches set (the H of the first brachium pontis
1) by N power switch unit (SM
h11, SM
h12..., SM
h1N) be in series, the middle switches set (M of the first brachium pontis
1) by N power switch unit (SM
m11, SM
m12..., SM
m1N) be in series, the lower switches set (L of the first brachium pontis
1) by N power switch unit (SM
l11, SM
l12..., SM
l1N) be in series, the upper switches set (H of the second brachium pontis
2) by N power switch unit (SM
h21, SM
h22..., SM
h2N) be in series, the middle switches set (M of the second brachium pontis
2) by N power switch unit (SM
m21, SM
m22..., SM
m2N) be in series, the lower switches set (L of the second brachium pontis
2) by N power switch unit (SM
l21, SM
l22..., SM
l2N) be in series; Middle switches set (the M of the first brachium pontis is received respectively at the two ends of the first load
1) and the middle switches set (M of the second brachium pontis
2) upper end (o), the middle switches set (M of the first brachium pontis is received respectively at the two ends of the second load
1) and the middle switches set (M of the second brachium pontis
2) lower end (p); Export as the first via at the two ends of the first load, and export as the second tunnel at the two ends of the second load.
2. the single-phase six switches set MMC inverters of dual output according to claim 1, is characterized in that: the coupling inductance (L of the first brachium pontis
h1: L
l1) coupling inductance (L of former limit and secondary and the second brachium pontis
h2: L
l2) former limit and secondary by the first inductance (L
h1, L
h2) and the second inductance (L
l1, L
l2) two separate inductors substitute.
3. the single-phase six switches set MMC inverters of dual output according to claim 1, is characterized in that: DC power supply (U
dc) positive pole and the upper switches set (H of the first brachium pontis
1) upper end, the upper switches set (H of the second brachium pontis
2) upper end connect, DC power supply (U
dc) negative pole and the lower switches set (L of the first brachium pontis
1) lower end, the lower switches set (L of the second brachium pontis
2) lower end connect; Upper switches set (the H of the first brachium pontis
1) lower end and the coupling inductance (L of the first brachium pontis
h1: L
l1) former limit (L
h1) Same Name of Ends (w
1) connect the coupling inductance (L of the first brachium pontis
h1: L
l1) former limit (L
h1) non-same polarity (a
1) with the middle switches set (M of the first brachium pontis
1) upper end connect, the middle switches set (M of the first brachium pontis
1) lower end and the coupling inductance (L of the first brachium pontis
h1: L
l1) secondary (L
l1) Same Name of Ends (b
1) connect the coupling inductance (L of the first brachium pontis
h1: L
l1) secondary (L
l1) non-same polarity (z
1) with the switches set (L of the first brachium pontis
1) upper end connect; The structure of the structure of the second brachium pontis and the first brachium pontis is in full accord; DC power supply (U
dc) negative pole and the lower switches set (L of the first brachium pontis
1) lower end, the lower switches set (L of the second brachium pontis
2) lower end, hold (n) connect; Middle switches set (the M of one end of the first load and the first brachium pontis
1) upper end connect, the middle switches set (M of the other end of the first load and the second brachium pontis
2) upper end connect, the middle switches set (M of one end of the second load and the first brachium pontis
1) lower end connect, the middle switches set (M of the other end of the second load and the second brachium pontis
2) lower end connect.
4. the single-phase six switches set MMC inverters of dual output according to claim 1, is characterized in that: power switch unit comprises the first switching tube (S
1), second switch pipe (S
2), the first diode (D
1), the second diode (D
2) and electric capacity (C
sM); Wherein, electric capacity (C
sM) positive pole and the first switching tube (S
1) collector electrode, the first diode (D
1) negative electrode connect, the first switching tube (S
1) emitter and the first diode (D
1) anode, second switch pipe (S
2) collector electrode, the second diode (D
2) negative electrode connect, second switch pipe (S
2) emitter and the second diode (D
2) anode, electric capacity (C
sM) negative pole connect; Second switch pipe (S
2) collector electrode as the first output, second switch pipe (S
2) emitter as the second output.
5. the single-phase six switches set MMC inverters of dual output according to claim 4, it is characterized in that: the second output of i power switch unit of each switches set is connected with the first output of i+1 power switch unit, wherein the value of i is 1 ~ N-1.
6. the single-phase six switches set MMC inverters of dual output according to claim 1, is characterized in that: mode of operation comprises same pattern and alien frequencies pattern frequently, and in frequency pattern, the electric voltage frequency that first via output is exported with the second tunnel is identical, and voltage magnitude is not identical; In alien frequencies pattern, first via output is all different from electric voltage frequency and the amplitude of the second tunnel output.
7. for the control method of the single-phase six switches set MMC inverters of dual output claimed in claim 1, it is characterized in that: adopt phase-shifting carrier wave PWM to control the opening and turn-offing of switching tube of each switches set; Upper switches set (the H of the first brachium pontis
1) i power switch unit (SM
h1i), the lower switches set (L of the first brachium pontis
1) i power switch unit (SM
l1i), the upper switches set (H of the second brachium pontis
2) i power switch unit (SM
h2i) and the lower switches set (L of the second brachium pontis
2) i power switch unit (SM
l2i) adopt identical triangular wave as i carrier wave C
i, wherein the value of i is 1 ~ N; N carrier wave (C
1, C
2..., C
n) 360 °/N of lagging phase angle successively; Upper switches set (the H of the first brachium pontis
1) the employing primary sinusoid (R
a1) stack the first direct current biasing (R
doa) as the first modulating wave (R of the first brachium pontis
a1+ R
doa), the lower switches set (L of the first brachium pontis
1) employing the second sine wave (R
b1) stack the second direct current biasing (R
dob) as the second modulating wave (R of the first brachium pontis
b1+ R
dob), the upper switches set (H of the second brachium pontis
2) employing the 3rd sine wave (R
a2) stack the first direct current biasing (R
doa) as the first modulating wave (R of the second brachium pontis
a2+ R
doa), the lower switches set (L of the second brachium pontis
2) employing the 4th sine wave (R
b2) stack the second direct current biasing (R
dob) as the second modulating wave (R of the second brachium pontis
b2+ R
dob); The primary sinusoid (R
a1) and the 3rd sine wave (R
a2) the identical and phase difference of frequency be 180 °, the second sine wave (R
b1) and the 4th sine wave (R
b2) the identical and phase difference of frequency be 180 °.
8. control method according to claim 6, is characterized in that: the first modulating wave (R of the first brachium pontis
a1+ R
doa) and i carrier wave C
iobtain the upper switches set (H of the first brachium pontis by the first comparator
1) i power switch unit (SM
h1i) second switch pipe (S
2) control level (S of gate pole
h1i), as the first modulating wave modulating wave (R of the first brachium pontis
a1+ R
doa) be greater than i carrier wave C
itime, the first comparator output high level, as the first modulating wave modulating wave (R of the first brachium pontis
a1+ R
doa) be less than i carrier wave C
itime, the first comparator output low level, wherein the value of i is 1 ~ N; The second modulating wave (R of the first brachium pontis
b1+ R
dob) and i carrier wave C
iobtain the lower switches set (L of the first brachium pontis by the second comparator
1) i power switch unit (SM
l1i) second switch pipe (S
2) control level (S of gate pole
l1i), as the second modulating wave (R of the first brachium pontis
b1+ R
dob) be less than i carrier wave C
itime, the second comparator output high level, as the second modulating wave (R of the first brachium pontis
b1+ R
dob) be greater than i carrier wave C
itime, the second comparator output low level; Upper switches set (the H of the first brachium pontis
1) i power switch unit (SM
h1i) second switch pipe (S
2) control level (S of gate pole
h1i) and the lower switches set (L of the first brachium pontis
1) i power switch unit (SM
l1i) second switch pipe (S
2) control level (S of gate pole
l1i) obtain the middle switches set (M of the first brachium pontis by the first XOR gate
1) i power switch unit (SM
m1i) middle second switch pipe (S
2) control level (S of gate pole
m1i); The first modulating wave (R of the second brachium pontis
a2+ R
doa) and i carrier wave C
iobtain the upper switches set (H of the second brachium pontis by the 3rd comparator
2) i power switch unit (SM
h2i) middle second switch pipe (S
2) control level (S of gate pole
h2i), as the first modulating wave (R of the second brachium pontis
a2+ R
doa) be greater than i carrier wave C
itime, the 3rd comparator output high level, as the first modulating wave (R of the second brachium pontis
a2+ R
doa) be less than i carrier wave C
itime, the 3rd comparator output low level; The second modulating wave (R of the second brachium pontis
b2+ R
dob) and i carrier wave C
iobtain switches set (L under the second brachium pontis by the 4th comparator
2) i power switch unit (SM
l2i) second switch pipe (S
2) control level (S of gate pole
l2i), as the second modulating wave (R of the second brachium pontis
b2+ R
dob) be less than i carrier wave C
itime, the 4th comparator output high level, as the second modulating wave (R of the second brachium pontis
b2+ R
dob) be greater than i carrier wave C
itime, the 4th comparator output low level; Upper switches set (the H of the second brachium pontis
2) i power switch unit (SM
h2i) middle second switch pipe (S
2) control level (S of gate pole
h2i) and the second brachium pontis under switches set (L
2) i power switch unit (SM
l2i) second switch pipe (S
2) control level (S of gate pole
l2i) obtain the middle switches set (M of the second brachium pontis by the second XOR gate
2) i power switch unit (SM
m2i) second switch pipe (S
2) control level (S of gate pole
m2i); Second switch pipe (S in each power switch unit of each switches set
2) obtain the first switching tube (S in this power switch unit after the control level of gate pole is anti-phase
1) control level of gate pole.
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| PCT/CN2014/075997 WO2015113328A1 (en) | 2014-01-28 | 2014-04-22 | Multi-terminal high-voltage modular multilevel converter |
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|---|---|---|---|
| CN201410042070.3A CN103825488B (en) | 2014-01-28 | 2014-01-28 | Single-phase six switches set MMC inverter and the control methods thereof of dual output |
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