CN103813587B - A kind of LED drive circuit of numerical model analysis light modulation - Google Patents

Abstract

The invention discloses an LED drive circuit with digital-analog hybrid dimming function, which mainly solves the slow input response speed of the circuit structure of the existing voltage control mode, including a dimming control unit, a peak current detection sampling unit and a constant off-time control unit. The dimming control unit adjusts the size of the average current flowing through the LED through two dimming methods, analog and digital, to achieve brightness adjustment, and outputs the peak current detection threshold V _CST1 to the peak current detection sampling unit, and outputs two enable V _EN1 and V _EN2 are given to the constant off-time control unit; the peak current detection sampling unit inputs the comparison result to the constant off-time control unit; the constant off-time control unit generates a constant off-time when the peak current is detected . The invention improves the input response speed, can realize fast digital-analog hybrid dimming, and can be applied to LED driving circuits.

Description

A digital-analog hybrid dimming LED drive circuit

technical field

The invention belongs to the technical field of electronic circuits, and relates to an analog integrated circuit, in particular to a digital-analog hybrid dimming LED drive circuit.

Background technique

With the rapid development of semiconductor technology and the continuous expansion of application fields, LED lighting technology with the advantages of environmental protection, energy saving, high efficiency, and long life has been widely used in various fields such as automotive lighting and architectural lighting. However, to bring these advantages into play requires the cooperation of LED driver chips. Therefore, the further development of LED driver integrated circuits has become an urgent need of the society. Among several common LED drive circuits, the DC-DC converter has been widely used because of its high working efficiency and simple operation. The DC-DC converter is a circuit structure that converts a certain DC input voltage into another DC output voltage. Its principle is to adjust the duty cycle of the loop by controlling the turn-on and turn-off time of the power switch tube, so as to maintain the output voltage. constant. DC-DC conversion circuits mainly have four topologies: Buck (step-down), Boost (boost), Cuk (boost-boost) and buck-boost (Buck-Boost), generally composed of power switch tubes, energy storage element inductors , Freewheeling diodes, capacitors, comparators and error amplifiers. The turn-on and turn-off time of the power switch tube is controlled by a feedback loop composed of an error amplifier and a comparator, so as to maintain a constant output. The entire circuit uses the energy stored in the inductor to provide a continuous current to the load.

The system structure of a typical voltage control mode DC-DC converter is shown in Figure 1. The circuit includes a voltage negative feedback loop controlled by pulse width modulation (PWM). The specific working principle is: the output voltage V _OUT is divided by the sampling resistor R _SNS and compared with the reference voltage V _REF , the difference is amplified by the error amplifier to obtain V _COMP , which is used as the non-inverting input terminal of the PWM comparator, and compared with the PWM Compare the sawtooth wave signal V _RAMP at the inverting input terminal of the device, and use the compared signal to control the turn-on and turn _- off of the power switch tube Q1. When the output voltage V _OUT drops, the feedback voltage signal obtained by dividing the voltage by the sampling resistor R _SNS will drop, and the voltage V _COMP amplified by the error amplifier will increase, so that the conduction time of the power switch tube Q ₁ increases, and the output voltage rises . The voltage control mode keeps the output constant through this kind of negative feedback. However, this voltage-controlled mode DC-DC converter requires an external compensation network, making the input response slow and the control loop vulnerable to current disturbances.

Contents of the invention

The object of the present invention is to propose a digital-analog hybrid dimming LED drive circuit for the slow input response speed of the DC-DC converter in the above-mentioned voltage control mode and the control loop is easily disturbed by the current. Constant off-time control mode with digital-analog hybrid dimming function. When the power switch tube Q1 is turned on, when the voltage across the _first resistor R1 reaches the set threshold voltage _of the comparator, the set peak current is detected, and _Q1 is turned off. In addition, the off-time of the system is constant. The whole circuit structure is simple, the control is convenient; the hysteresis control response speed is fast; the loop compensation is simple; the system stability is good.

In order to achieve the above object, the present invention adopts the following technical solutions to solve it:

A digital-analog hybrid dimming LED drive circuit, comprising the following units:

The dimming control unit includes an analog dimming circuit and a digital dimming circuit, wherein the analog dimming circuit is used to receive the driving voltage V _ADJ1 , and output the peak current detection threshold voltage V by adjusting the voltage value of the driving voltage V _{ADJ1 CST1} , and will be input to the peak current detection sampling unit; the digital dimming circuit is used to receive the enable signal V _EN , and under the control of the enable signal V _EN , to the peak current detection sampling unit and constant off-time control The unit outputs an enable signal V _EN1 , and at the same time outputs an enable signal V _EN2 to the constant off-time control unit;

The peak current detection sampling unit is used to receive the peak current detection threshold voltage V _CST1 sent by the receiving analog dimming circuit in the dimming control unit and the output enable signal V _EN1 sent by the digital dimming circuit; and the enable signal V _EN1 Under the control of the input voltage V _IN and the voltage V ₁ obtained by the input voltage V _IN through the voltage drop V _SNS is compared with the peak detection threshold voltage V _CST1 to realize the detection of the peak current, and the output signal V ₃ is input to a constant Off time control unit;

Constant off-time control unit: used to receive the enable signal V _EN1 and enable signal V _EN2 sent by the digital dimming circuit in the dimming control unit, and at the same time receive the output signal V ₃ sent by the peak current detection sampling unit; Under the control of the enable signal V _EN1 and the enable signal V _EN2 , when the peak current is detected, the input voltage V _ADJ2 is adjusted to obtain an output voltage V ₂ , and the output voltage V ₂ is sent to the power switch tube Q ₁ ;

Power switch tube Q ₁ : used to receive the output voltage V ₂ sent by the constant off-time control unit, and generate a constant off-time T _OFF according to the output voltage V ₂ ;

The input DC power supply is connected in parallel with the first capacitor C ₁ to obtain the input voltage V _IN , the input voltage V _IN and the voltage V ₁ at both ends of the first resistor R ₁ are connected to the peak current detection unit; the output voltage V output by the constant off-time control unit ₂ is connected to a driver, which is used to control the turn-on and turn _- off _of the power switch tube Q1 _; the power switch tube Q1 is connected in parallel with the Schottky diode D1 and the _second capacitor C2, and is connected in series with the _first inductor L1 .

Further, the dimming control unit includes an analog dimming circuit and a digital dimming circuit.

Further, the analog dimming circuit includes an amplifier, an NMOS transistor M ₁₀₁ , a second resistor R ₂ , a third resistor R ₃ and a current source _IS1 ; the digital dimming circuit 12 includes a first Schmitt trigger and A second Schmitt trigger, an inverter, a PMOS transistor M ₁₀₂ , a PMOS transistor M ₁₀₄ , an NMOS transistor M ₁₀₃ , an NMOS transistor M ₁₀₅ and a third capacitor C ₃ ; where:

In the amplifier, its non-inverting input terminal is connected to the driving voltage V _ADJ1 and grounded through the third resistor _R3 ; its inverting terminal is grounded through the _second resistor R2; its output terminal is connected to the gate of the NMOS transistor _M101 ; the NMOS The drain of the tube M ₁₀₁ is connected to the input threshold voltage V _CST1 of the peak current detection sampling unit, and its source is grounded through the second resistor R ₂ ; the input terminal of the current source _IS1 is connected to the internal power supply V _DD , and its output terminal is connected through the third Resistor R ₃ is connected to ground and connected to V _ADJ1 ;

The first Schmitt trigger, its input terminal is connected to the drain of the NMOS transistor _M103 , and is connected to the positive pole of the _third capacitor C3 at the same time, and its output terminal is connected to the input terminal of the inverter. Enable signal V _EN1 ; its power supply terminals are respectively connected to internal power supply V _DD and ground;

In the second Schmitt trigger, its input terminal is connected to the output terminal of the inverter, and the drains of the PMOS transistor M ₁₀₄ and the NMOS transistor M ₁₀₅ are connected at the same time; its output terminal is connected to the constant off-time control unit The enable signal V _EN2 of one input terminal of the NAND gate; its power supply terminal is respectively connected to the internal power supply V _DD and ground;

The input of the inverter is connected to the output of the Schmitt trigger, and its output is connected to the gate of the PMOS transistor M ₁₀₄ ; the source of the PMOS transistor M ₁₀₂ is connected to the internal power supply V _DD , and its output is connected to the gate of the PMOS transistor M 104 . The gate is directly connected to the ground; the source of the PMOS transistor M ₁₀₄ is connected to the internal power supply V _DD ; the gate of the NMOS transistor M ₁₀₃ is connected to the enable input signal V _EN , and its source is grounded; the source of the NMOS transistor M ₁₀₅ is connected to the internal power supply V DD . It is grounded, and its gate is connected to the enable input signal V _EN ; the third capacitor C ₃ , its negative pole is grounded.

Further, the peak current detection sampling unit includes an inverter, a current source I _S2 , a fourth resistor R ₄ , a fifth resistor R ₅ , a sixth resistor R ₆ , a seventh resistor R ₇ , and a high-voltage PMOS transistor M ₂₀₃ , High-voltage PMOS tube M ₂₀₅ , High-voltage NMOS tube M ₂₀₄ , High-voltage NMOS tube M ₂₀₆ , NMOS tube M ₂₀₁ , NMOS tube M ₂₀₂ , NMOS tube M ₂₀₇ , NMOS tube M ₂₀₈ , NMOS tube M ₂₀₉ , NMOS tube M ₂₁₀ , NMOS tube Tube M ₂₁₁ , NMOS tube M ₂₁₂ , NMOS tube M ₂₁₅ , NMOS tube M ₂₂₀ , NMOS tube M ₂₂₁ , NMOS tube M ₂₂₃ , NMOS tube M ₂₂₄ , NMOS tube M ₂₂₆ , PMOS tube M ₂₁₃ , PMOS tube M ₂₁₄ , PMOS tube Tube M ₂₁₆ , PMOS tube M ₂₁₇ , PMOS tube M ₂₁₈ , PMOS tube M ₂₁₉ , PMOS tube M ₂₂₂ and PMOS tube M ₂₂₅ ; wherein:

The input of the inverter is connected to the enable input signal V _EN1 , and its output is connected to the NMOS transistor M ₂₀₇ ;

The input terminal of the current source _IS2 is connected to the internal power supply V _DD , and its output terminal is connected to the drains of the NMOS transistors M ₂₀₇ and M ₂₀₈ , and connected to the gates of the NMOS transistors M ₂₀₈ and M ₂₀₉ ; NMOS transistors M ₂₀₈ , M ₂₀₉ , M ₂₁₀ , M ₂₁₁ , and M ₂₁₂ form a row of current mirrors, and the gates of NMOS transistors M ₂₀₈ , M ₂₀₉ , M ₂₁₀ , M ₂₁₁ , and M ₂₁₂ are all connected to the gate of NMOS transistor M ₂₀₈ Both poles and sources are grounded;

The drain of the NMOS transistor M ₂₀₉ is connected to the sources of the NMOS transistors M ₂₀₁ and M ₂₀₂ forming a differential pair; the drain of the NMOS transistor M ₂₁₀ is connected to the source of the high-voltage NMOS transistor M ₂₀₄ ; the NMOS transistor M The drain of ₂₁₁ is connected to the source of the high-voltage NMOS transistor M ₂₀₆ , and the drain of the NMOS transistor M ₂₁₂ is connected to the drain of the PMOS transistor M ₂₁₃ ;

The NMOS transistors _M201 and _M202 form a differential pair, their drains are respectively connected to the input voltage V _IN through the _sixth resistor R6 and the seventh resistor _R7 , and their gates are respectively connected through the fourth resistor R ₄ and the fifth resistor R ₅ are connected to the input voltage V ₁ and V _IN ;

The high-voltage PMOS transistors M ₂₀₃ and M ₂₀₅ and the NMOS transistors M ₂₀₄ and M ₂₀₆ are high-voltage drain transistors, wherein the sources of the high-voltage PMOS transistors M ₂₀₃ and M ₂₀₅ are connected to the differential pair of NMOS transistors M ₂₀₁ and M ₂₀₂ respectively. On the drains, their drains are respectively connected to the drains of the NMOS transistors M ₂₀₄ and M ₂₀₆ , and their gates are connected to the input voltage V _B1 ; the gates of the high-voltage NMOS transistors M ₂₀₄ and M ₂₀₆ are connected to the input voltage V _B2 , their sources are respectively connected to the gates of NMOS transistors M ₂₁₉ and M ₂₁₈ forming a differential pair;

The PMOS transistors M ₂₁₃ and M ₂₁₆ constitute a current mirror, their sources are connected to the internal power supply V _DD , and the drain of the PMOS transistor M ₂₁₆ is connected to the sources of the PMOS transistors M ₂₁₈ and M ₂₁₉ that form a differential pair; The source of the tube M ₂₁₇ is connected to the internal power supply V _DD , the gate is connected to the enable signal V _EN1 , and the drain is connected to the drain of the PMOS tube M ₂₁₃ ;

The PMOS transistors M ₂₁₄ and M ₂₂₂ form a current mirror, and their sources are connected to the internal power supply V _DD , wherein the drain of the PMOS transistor M ₂₁₄ is connected to the drain of the NMOS transistor M ₂₁₅ , and the drain of the PMOS transistor M ₂₂₂ is connected to the NMOS transistor The drain of M ₂₂₃ ; the NMOS transistors M ₂₁₅ and M ₂₂₀ also constitute a current mirror, and their sources are all grounded, wherein the drain of the NMOS transistor M ₂₂₀ is connected to the drain of the PMOS transistor M ₂₁₈ forming a differential pair; The above-mentioned NMOS transistors M ₂₂₁ and M ₂₂₃ also constitute a current mirror, their sources are all grounded, and the drain of the NMOS transistor M ₂₂₁ is connected to the drain of the PMOS transistor M ₂₁₉ that forms a differential pair;

The gate of the NMOS transistor M ₂₂₄ is connected to the enable signal V _EN1 for controlling its switching state, its drain is connected to the drain of the NMOS transistor M ₂₂₃ , and its source is grounded; the PMOS transistor M ₂₂₅ and the NMOS The tube M ₂₂₆ constitutes an inverter, the input terminal of the inverter is connected to the drain of the NMOS tube M ₂₂₃ , and the output terminal is connected to the output signal V ₃ , wherein the source of the PMOS tube M ₂₂₅ is connected to the internal power supply V _DD , and the NMOS tube M 225 is connected to the internal power supply V DD . The source of tube M ₂₂₆ is grounded.

Further, the constant off-time control unit includes an amplifier, a comparator, an RS flip-flop, an inverter, an inverter, a NAND gate, a fourth capacitor C ₄ , an eighth resistor R ₈ , and a PMOS transistor M ₃₀₁ , PMOS transistor M ₃₀₂ , PMOS transistor M ₃₀₃ and PMOS transistor M ₃₀₄ , NMOS transistor M ₃₀₅ and NMOS transistor M ₃₀₆ ; wherein:

In the amplifier, its non-inverting input terminal is connected to the input voltage V _ADJ2 , the inverting input terminal is grounded through the eighth resistor _R8 , and its output terminal is connected to the gate of the NMOS transistor M ₃₀₅ ; the non-inverting input terminal of the comparator is connected to the reference voltage V _REF , its inverting terminal is connected to the drain of the PMOS transistor M ₃₀₃ , and its output terminal is connected to the reset terminal R of the RS flip-flop; the RS flip-flop is composed of two NAND gates, and its setting terminal S is connected to the inverting On the output terminal of the inverter, its output terminal is connected to the input terminal of the inverter; the input terminal of the inverter is connected to the output signal V ₃ of the peak current detection sampling unit, and the output terminal of the inverter is connected to One input of the NAND gate; the other input terminal of the NAND gate is connected to the enable signal V _EN2 , and its output terminal is connected to the output voltage V ₂ ;

The PMOS transistors M ₃₀₁ , M ₃₀₂ , M ₃₀₃ and M ₃₀₄ form a current mirror, wherein the sources of the PMOS transistors M ₃₀₁ and M ₃₀₂ are connected to the internal power supply V _DD , and the drains are respectively connected to the PMOS transistors M ₃₀₄ and On the source of M ₃₀₃ ; by taking the same tube size, the current relationship is: I _D6= I _D7= I _D8= I _D9 ;

The drain of the PMOS transistor _M304 is connected to the drain of the NMOS transistor _M305 , the drain of the PMOS transistor _M303 is grounded through the fourth capacitor _C4 ; the source of the NMOS transistor _M305 is grounded through the eighth resistor _R8 , The gate of the NMOS transistor _M306 is connected to the output signal V ₃ of the peak current detection sampling unit, its drain is connected to the inverting input terminal of the comparator, and its source is grounded.

Further, the peak current detection sampling unit includes an inverter, a fourth resistor R ₄ , a fifth resistor R ₅ , a PMOS transistor M ₂₀₁ , a PMOS transistor M ₂₀₂ , a PMOS transistor M ₂₀₅ , a PMOS transistor M ₂₀₆ , and a PMOS transistor M ₂₀₉ , PMOS tube M ₂₁₂ , PMOS tube M ₂₁₃ , NMOS tube M ₂₀₃ , NMOS tube M ₂₀₄ , NMOS tube M ₂₀₇ , NMOS tube M ₂₀₈ , NMOS tube M ₂₁₀ , NMOS tube M ₂₁₁ , NMOS tube M ₂₁₄ , and NMOS tube M ₂₁₅ ; of which:

In the inverter, its input end is connected to the drain of the PMOS transistor M ₂₁₃ , and its output end is connected to the grid of the NMOS transistor M ₃₀₆ in the constant off-time control unit for controlling its switch; the PMOS transistors M ₂₁₂ and M ₂₁₃ constitutes a current mirror, their sources are connected to the internal power supply V _DD , the drain of the PMOS transistor M ₂₁₂ is connected to the drain of the NMOS transistor M ₂₁₄ , and the drain of the PMOS transistor M ₂₁₃ is connected to the drain of the NMOS transistor M ₂₁₅ ;

The gate of the NMOS transistor _M215 is connected to the source of the high-voltage NMOS transistor _M210 , and its source is grounded; the gates of the NMOS transistors _M214 , _M211 , and _M208 are all connected to the gate of the NMOS transistor _M207 , Their sources are all grounded, wherein the drain of NMOS transistor _M211 is connected to the source of high-voltage NMOS transistor _M210 , the drain of NMOS transistor _M208 is connected to the source of high-voltage NMOS transistor _M206 , and the drain of NMOS transistor _M207 is connected to The source of the high-voltage NMOS transistor M ₂₀₅ ; the gate of the high-voltage NMOS transistor M ₂₁₀ is connected to the internal power supply V _DD , and its drain is connected to the drain of the high-voltage PMOS transistor M ₂₀₉ ; the source of the PMOS transistor M ₂₀₉ is connected to the input voltage V _IN , the gate of which is connected to the drain of the PMOS transistor _M202 and the high-voltage NMOS transistor _M204 ;

The PMOS transistors M ₂₀₁ and M ₂₀₂ constitute a current mirror, and their sources are connected to the input voltage V _IN , wherein the drains of the PMOS transistors M ₂₀₁ and M ₂₀₂ are respectively connected to the drains of the NMOS transistors M ₂₀₃ and M ₂₀₄ ; the high voltage The NMOS transistor M ₂₀₄ , its gate is connected to the output threshold voltage V _CST of the analog dimming circuit in the dimming control unit, and is connected to the input voltage V _IN through the fifth resistor R ₅ , and its source is connected to the source of the NMOS transistor M ₂₀₃ connected to the drain of the high-voltage NMOS transistor _M206 ; the gate of the NMOS transistor _M203 is connected to the input voltage V1 through the _fourth resistor R4; the high _- voltage NMOS transistors _M205 and _M206 form a current mirror, wherein the NMOS The drain of the tube M ₂₀₅ is connected to the current source I _S2 .

Further, the constant off-time control unit includes a comparator, an RS flip-flop, an inverter and an inverter, a NAND gate, a fourth capacitor C ₄ , an eighth resistor R ₈ and an NMOS transistor M ₃₀₁ ; wherein:

In the comparator, its non-inverting input terminal is connected to the reference voltage V _REF , its inverting input terminal is connected to the drain of the NMOS transistor _M301 , and is connected to the output voltage V _ADJ2 through the eighth resistor _R8 or through the fourth capacitor _C4 It is grounded, and its output terminal is connected to the reset terminal R of the RS flip-flop; the RS flip-flop is composed of two NAND gates, and its setting terminal S is connected to the output terminal of the inverter, and its output terminal is connected to the inverter on the input terminal of the inverter; the input terminal of the inverter is connected to the output signal V ₃ of the peak current detection sampling unit; the output terminal of the inverter is connected to an input of the NAND gate; the input terminal of the NAND gate The other input terminal is connected to the enable signal V _EN2 , and its output terminal is connected to the output voltage V ₂ ; the gate of the NMOS transistor M ₃₀₁ is connected to the output signal V ₃ of the peak current detection sampling unit, and its source is grounded.

Compared with the prior art, the present invention has the following advantages:

1. The present invention triggers the shutdown of the power switch tube by comparing the voltage across the _first resistor R1 with the threshold voltage of the comparator, and does not require an error amplifier and a feedback network. Therefore, compared with the traditional voltage control mode, it has faster response speed.

2. The constant off-time control mode LED drive circuit of the present invention does not need an external compensation network, and the loop compensation is simple, easy to implement, and convenient to control; and the switching frequency only increases with the increase of V _IN , and the system has good stability and is effective It avoids the problem that the control loop in the traditional system is susceptible to current interference.

Description of drawings

Figure 1 is a system block diagram of a traditional LED drive circuit.

Fig. 2 is a structural block diagram of the digital-analog hybrid dimming LED driving circuit of the present invention.

Fig. 3 is a schematic diagram of the dimming control unit in Embodiment 1 of the present invention.

FIG. 4 is a schematic diagram of a peak current detection sampling unit circuit in Embodiment 1 of the present invention.

FIG. 5 is a schematic diagram of a constant off-time control unit circuit in Embodiment 1 of the present invention.

FIG. 6 is a schematic diagram of a peak current detection sampling unit circuit in Embodiment 2 of the present invention.

FIG. 7 is a schematic diagram of a constant off-time control unit circuit in Embodiment 3 of the present invention.

The present invention will be further described below in conjunction with accompanying drawings and embodiments thereof.

Detailed ways

Example 1:

Referring to FIG. 2 and FIG. 3 , the digital-analog hybrid dimming LED drive circuit of the present invention includes a dimming control unit 1 , a peak current detection sampling unit 2 and a constant off-time control unit 3 .

The dimming control unit 1 includes an analog dimming circuit 11 and a digital dimming circuit 12, and has two input terminals a, b and three output terminals c, d, e; wherein, the first input terminal a and the second The input end b is respectively connected to the input drive voltage V _ADJ1 of the analog dimming circuit 11 and the input enable control signal V _EN of the digital dimming circuit 12, and the dimming control unit 1 performs analog dimming and digital dimming by changing V _ADJ1 and V _EN respectively. Dimming: the first output terminal c is connected to the enable signal V _EN2 of the output terminal of the second Schmitt trigger in the digital dimming circuit 12; the second output terminal d is connected to the first Schmitt trigger in the digital dimming circuit 12 The enable signal V _EN1 at the output terminal; the third output terminal e is connected to the current peak detection threshold V _CST1 in the analog dimming circuit 11 , which is changed by changing V _ADJ1 .

The peak current detection sampling unit 2 is provided with four input terminals f, g, j, k and one output terminal h; wherein, the first input terminal f is connected to the output current of the analog dimming circuit 11 in the dimming control unit 1 The peak threshold voltage V _CST1 is connected; the second input terminal g is connected with the enable signal V _EN1 of the digital dimming circuit 12 in the dimming control unit 1, and is used to realize the control of the working state of the internal device; the third input terminal j and the fourth The input terminal k is respectively connected to the output terminal V ₁ of the first resistor R ₁ and the input terminal V _IN of the circuit, and is used to compare the voltage drop V _SNS on the first resistor R ₁ with the peak current detection threshold V _CST to realize the peak current detection; the output terminal h is connected to the input terminal in the constant off-time control unit 3 .

The constant off-time control unit 3 is provided with four input terminals m, n, o, p and an output terminal q; wherein, the first input terminal m is connected to the output signal _V3 in the peak current detection sampling unit 2 ; The second input terminal n and the third input terminal o are respectively connected to the enable signals V _EN1 and V _EN2 of the output terminals of the digital dimming circuit in the dimming control unit 1, and are used to control the on and off of internal devices; the fourth The input terminal p is connected to the driving voltage V _ADJ2 of the amplifier, and is used to adjust the charging and discharging of the fourth capacitor _C4 , so as to realize the control _of the off time of the PMOS transistor Q1 _; the output terminal q is connected to the output voltage V2.

The input DC power supply is connected in parallel with the first capacitor C ₁ to obtain the input voltage V _IN , the input voltage V _IN and the voltage V ₁ at both ends of the first resistor R ₁ are connected to the peak current detection unit 2; the output of the constant off-time control unit 3 The voltage V ₂ is connected to a driver Driver, which is used to control the turn-on and turn _- off of the power switch tube Q1 _; the power switch tube Q1 is connected in parallel with the Schottky diode D1 and the _second capacitor C2, and is connected with the _first inductor L ₁ in series.

When the power switch tube Q1 is turned _on , the Schottky diode D1 is in reverse bias, the DC power supply charges the _first inductor L1, and the inductor current increases linearly until _a certain level, the current on the LED is only provided by the DC power supply , at this time the DC power supply starts to charge the _second capacitor C2, and when the peak current is detected, the power switch tube Q1 is turned off; then because the current in the _first inductor L1 will not change abruptly, it will produce _a change with the inductor current The opposite induced electromotive force prevents the reduction of the inductor current, and makes the diode D1 turn _on for freewheeling. This is the application of the circuit topology principle of the BUCK type DC-DC converter, which finally makes the output voltage V _OUT stable, so that the current flowing through the LED is stable.

The high-voltage PMOS and high-voltage NMOS transistors described below generally have a withstand voltage drop between 5V and 80V.

Referring to FIG. 3 , the dimming control unit 1 includes an analog dimming circuit 11 and a digital dimming circuit 12 . Among them, the analog dimming circuit 11 includes an amplifier 101, an NMOS transistor M ₁₀₁ , a second resistor R ₂ , a third resistor R ₃ and a current source _IS1 ; the digital dimming circuit 12 includes a first Schmitt trigger 102 and a second A Schmitt trigger 104 , an inverter 103 , a PMOS transistor M ₁₀₂ , a PMOS transistor M ₁₀₄ , an NMOS transistor M ₁₀₃ , an NMOS transistor M ₁₀₅ and a third capacitor C ₃ . in:

In the amplifier ₁₀₁ , its non-inverting input terminal is connected to the drive voltage V _ADJ1 and grounded through the third resistor _R3 ; its inverting terminal is grounded through the _second resistor R2; its output terminal is connected to the gate of the NMOS transistor M101; The drain of the NMOS transistor M ₁₀₁ is connected to the input threshold voltage V _CST1 of the peak current detection sampling unit 2, and its source is connected to the ground through the second resistor R ₂ ; the input terminal of the current source I _S1 is connected to the internal power supply V _DD , and its output terminal is connected to the internal power supply V DD through The third resistor R ₃ is connected to ground and connected to V _ADJ1 ; since R ₂ =5R ₅ , therefore,

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; CST</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 5</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; ADJ</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; ADJ</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

Wherein, V _IN -V _CST =V _CST1 ; V _CST is the voltage drop across the fifth resistor R ₅ ; V _CST1 is the peak current detection threshold.

The first Schmitt trigger 102, its input terminal is connected to the drain of the NMOS transistor M ₁₀₃ , and is connected to the positive pole of the _third capacitor C3, and its output terminal is connected to the input terminal of the inverter 103, and simultaneously connected to the positive pole of the third capacitor C3. Input enable signal V _EN1 ; its power supply terminals are respectively connected to internal power supply V _DD and ground.

Described second Schmitt trigger 104, its input end is connected on the output end of inverter 103, connects the drain electrode of PMOS transistor M ₁₀₄ and NMOS transistor M ₁₀₅ at the same time; Its output end is connected in constant off-time control The enable signal V _EN2 of an input terminal of the NAND gate 306 in unit 3 is connected to the internal power supply V _DD and the ground respectively.

In the inverter 103, its input terminal is connected to the output terminal of the Schmitt trigger 102, and its output terminal is connected to the gate of the PMOS transistor M ₁₀₄ ; the source of the PMOS transistor M ₁₀₂ is connected to the internal power supply V _DD , whose gate is directly connected to the ground; PMOS transistor M ₁₀₄ , whose source is connected to the internal power supply V _DD ; NMOS transistor M ₁₀₃ , whose gate is connected to the enable input signal V _EN , and whose source is grounded; NMOS transistor M ₁₀₅ , whose The source is grounded, and its gate is connected to the enable input signal V _EN ; the negative electrode of the third capacitor C ₃ is grounded.

Referring to FIG. 4 , the peak current detection sampling unit 2 of this embodiment includes an inverter 201, a current source I _S2 , a fourth resistor R ₄ , a fifth resistor R ₅ , a sixth resistor R ₆ , a seventh resistor R ₇ , High-voltage PMOS tube M ₂₀₃ , high-voltage PMOS tube M ₂₀₅ , high-voltage NMOS tube M ₂₀₄ , high-voltage NMOS tube M ₂₀₆ , NMOS tube M ₂₀₁ , NMOS tube M ₂₀₂ , NMOS tube M ₂₀₇ , NMOS tube M ₂₀₈ , NMOS tube M ₂₀₉ , NMOS Tube M ₂₁₀ , NMOS tube M ₂₁₁ , NMOS tube M ₂₁₂ , NMOS tube M ₂₁₅ , NMOS tube M ₂₂₀ , NMOS tube M ₂₂₁ , NMOS tube M ₂₂₃ , NMOS tube M ₂₂₄ , NMOS tube M ₂₂₆ , PMOS tube M ₂₁₃ , PMOS tube The transistor M ₂₁₄ , the PMOS transistor M ₂₁₆ , the PMOS transistor M ₂₁₇ , the PMOS transistor M ₂₁₈ , the PMOS transistor M ₂₁₉ , the PMOS transistor M ₂₂₂ and the PMOS transistor M ₂₂₅ . in:

In the inverter 201, its input end is connected to the enable input signal V _EN1 , and its output end is connected to the NMOS transistor M ₂₀₇ ;

The input terminal of the current source _IS2 is connected to the internal power supply V _DD , and its output terminal is connected to the drains of the NMOS transistors M ₂₀₇ and M ₂₀₈ , and connected to the gates of the NMOS transistors M ₂₀₈ and M ₂₀₉ ; NMOS transistors M ₂₀₈ , M ₂₀₉ , M ₂₁₀ , M ₂₁₁ , and M ₂₁₂ form a row of current mirrors, and the gates of NMOS transistors M ₂₀₈ , M ₂₀₉ , M ₂₁₀ , M ₂₁₁ , and M ₂₁₂ are all connected to the gate of NMOS transistor M ₂₀₈ Both the pole and the source are grounded; the magnitude of the current flowing on the NMOS tubes M ₂₀₈ , M ₂₀₉ , M ₂₁₀ , M ₂₁₁ , and M ₂₁₂ is calculated according to the size of each NMOS tube:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; \&times;</span>\frac{{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 209</span>}}}{{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 208</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; \&times;</span>\frac{{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 210</span>}}}{{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 208</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; \&times;</span>\frac{{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 211</span>}}}{{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 208</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; \&times;</span>\frac{{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 212</span>}}}{{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 208</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span>$

The drain of the NMOS transistor M ₂₀₉ is connected to the sources of the NMOS transistors M ₂₀₁ and M ₂₀₂ forming a differential pair; the drain of the NMOS transistor M ₂₁₀ is connected to the source of the high-voltage NMOS transistor M ₂₀₄ ; the NMOS transistor M The drain of ₂₁₁ is connected to the source of the high-voltage NMOS transistor _M206 , and the drain of the NMOS transistor _M212 is connected to the drain of the PMOS transistor _M213 .

The NMOS transistors _M201 and _M202 form a differential pair, their drains are respectively connected to the input voltage V _IN through the _sixth resistor R6 and the seventh resistor _R7 , and their gates are respectively connected through the fourth resistor R ₄ and the _fifth resistor R5 are connected to the input voltages _V1 and V _IN .

The high-voltage PMOS transistors M ₂₀₃ and M ₂₀₅ and the NMOS transistors M ₂₀₄ and M ₂₀₆ are high-voltage drain transistors, wherein the sources of the high-voltage PMOS transistors M ₂₀₃ and M ₂₀₅ are connected to the differential pair of NMOS transistors M ₂₀₁ and M ₂₀₂ respectively. On the drains, their drains are respectively connected to the drains of the NMOS transistors M ₂₀₄ and M ₂₀₆ , and their gates are connected to the input voltage V _B1 ; the gates of the high-voltage NMOS transistors M ₂₀₄ and M ₂₀₆ are connected to the input voltage V _B2 , their sources are respectively connected to the gates of the NMOS transistors M ₂₁₉ and M ₂₁₈ forming the differential pair, serving as the input of the differential pair.

The PMOS transistors M ₂₁₃ and M ₂₁₆ constitute a current mirror, their sources are connected to the internal power supply V _DD , and the drain of the PMOS transistor M ₂₁₆ is connected to the sources of the PMOS transistors M ₂₁₈ and M ₂₁₉ that form a differential pair; The source of the transistor M ₂₁₇ is connected to the internal power supply V _DD , the gate is connected to the enable signal V _EN1 , and the drain is connected to the drain of the PMOS transistor M ₂₁₃ .

The PMOS transistors M ₂₁₄ and M ₂₂₂ form a current mirror, and their sources are connected to the internal power supply V _DD , wherein the drain of the PMOS transistor M ₂₁₄ is connected to the drain of the NMOS transistor M ₂₁₅ , and the drain of the PMOS transistor M ₂₂₂ is connected to the NMOS transistor The drain of M ₂₂₃ ; the NMOS transistors M ₂₁₅ and M ₂₂₀ also constitute a current mirror, and their sources are all grounded, wherein the drain of the NMOS transistor M ₂₂₀ is connected to the drain of the PMOS transistor M ₂₁₈ forming a differential pair; The above-mentioned NMOS transistors _M221 and _M223 also constitute a current mirror, and their sources are grounded, and the drain of the NMOS transistor _M221 is connected to the drain of the PMOS transistor _M219 forming a differential pair.

The gate of the NMOS transistor M ₂₂₄ is connected to the enable signal V _EN1 for controlling its switching state, its drain is connected to the drain of the NMOS transistor M ₂₂₃ , and its source is grounded; the PMOS transistor M ₂₂₅ and the NMOS The tube M ₂₂₆ constitutes an inverter, the input terminal of the inverter is connected to the drain of the NMOS tube M ₂₂₃ , and the output terminal is connected to the output signal V ₃ , wherein the source of the PMOS tube M ₂₂₅ is connected to the internal power supply V _DD , and the NMOS tube M 225 is connected to the internal power supply V DD . The source of tube M ₂₂₆ is grounded.

Referring to FIG. 5, the constant off-time control unit 3 of this embodiment includes an amplifier 301, a comparator 302, an RS flip-flop 303, an inverter 304, an inverter 305, a NAND gate 306, a fourth capacitor C ₄ , Eighth resistor R ₈ , PMOS transistor M ₃₀₁ , PMOS transistor M ₃₀₂ , PMOS transistor M ₃₀₃ and PMOS transistor M ₃₀₄ , NMOS transistor M ₃₀₅ and NMOS transistor M ₃₀₆ . in:

In the amplifier 301, its non-inverting input terminal is connected to the input voltage V _ADJ2 , its inverting input terminal is connected to the ground through the eighth resistor R ₈ , and its output terminal is connected to the gate of the NMOS transistor M ₃₀₅ ; the non-inverting input terminal of the comparator 302 is connected to The reference voltage V _REF , its inverting terminal is connected to the drain of the PMOS transistor M ₃₀₃ , and its output terminal is connected to the reset terminal R of the RS flip-flop; the RS flip-flop is composed of two NAND gates, and its setting terminal S is connected to The output terminal of the inverter 304 is connected to the input terminal of the inverter 305; the input terminal of the inverter 304 is connected to the output signal V ₃ of the peak current detection sampling unit 2, and the inverter The output terminal of the NAND gate 305 is connected to one input of the NAND gate 306; the other input terminal of the NAND gate 306 is connected to the enable signal V _EN2 , and the output terminal of the NAND gate 306 is connected to the output voltage V ₂ .

The PMOS transistors M ₃₀₁ , M ₃₀₂ , M ₃₀₃ and M ₃₀₄ form a current mirror, wherein the sources of the PMOS transistors M ₃₀₁ and M ₃₀₂ are connected to the internal power supply V _DD , and the drains are respectively connected to the PMOS transistors M ₃₀₄ and On the source of M ₃₀₃ ; by taking the same tube size, the current relationship is: I _{D6 =} I _{D7 =} I _{D8 =} I _D9 .

The drain of the PMOS transistor _M304 is connected to the drain of the NMOS transistor _M305 , the drain of the PMOS transistor _M303 is grounded through the fourth capacitor _C4 ; the source of the NMOS transistor _M305 is grounded through the eighth resistor _R8 , The gate of the NMOS transistor M ₃₀₆ is connected to the output signal V ₃ of the peak current detection sampling unit 2 , its drain is connected to the inverting input terminal of the comparator 302 , and its source is grounded.

In the LED driving circuit of this embodiment, the turn-off time T _OFF is constant, which is mainly adjusted in advance by the eighth resistor R ₈ , the fourth capacitor C ₄ , and a constant output voltage V _ADJ2 . At the initial moment of T _OFF , the voltage on the fourth capacitor _C4 is zero, and then the current mirror will provide charge to the capacitor, and the capacitor starts to charge, and the charging time constant is determined by _R8 and _C4 . When the voltage (V _COFF ) across the fourth capacitor C ₄ is charged to be equal to the reference voltage V _REF , the off-time ends and the capacitor discharges to zero. The formula for calculating the turn _- off time T _OFF of the power switch tube Q1 is:

${\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; OFF</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; REF</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 8</span>}}}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; ADJ</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; )</span>$

In addition, this circuit is controlled by the peak current detection sampling unit 2. When the _first resistor R1 detects the peak current, the system on-time T _ON ends and the off-time T _OFF begins. Through the analysis, it can be known that once the peak current is detected, the output signal V ₃ is at a high level, and this output signal V ₃ is connected to the gate of the NMOS transistor M ₃₀₆ in the off-time control circuit to ensure that at the initial stage of the T _OFF time period At this moment, the charge on the fourth capacitor _C4 is zero.

Example 2:

The dimming control unit 1 and the constant off-time control unit 3 of this embodiment are the same as those in the first embodiment.

Referring to FIG. 6 , the peak current detection sampling unit 2 of this embodiment includes an inverter 201, a fourth resistor R ₄ , a fifth resistor R ₅ , a PMOS transistor M ₂₀₁ , a PMOS transistor M ₂₀₂ , a PMOS transistor M ₂₀₅ , and a PMOS transistor M ₂₀₆ , PMOS tube M ₂₀₉ , PMOS tube M ₂₁₂ , PMOS tube M ₂₁₃ , NMOS tube M ₂₀₃ , NMOS tube M ₂₀₄ , NMOS tube M ₂₀₇ , NMOS tube M ₂₀₈ , NMOS tube M ₂₁₀ , NMOS tube M ₂₁₁ , NMOS tube M ₂₁₄ and NMOS tube M ₂₁₅ . in:

The input end of the inverter 201 is connected to the drain of the PMOS transistor _M213 , and the output end is connected to the gate of the NMOS transistor _M306 in the constant off-time control unit 3 for controlling its switch. The PMOS transistors M ₂₁₂ and M ₂₁₃ form a current mirror, their sources are connected to the internal power supply V _DD , the drain of the PMOS transistor M ₂₁₂ is connected to the drain of the NMOS transistor M ₂₁₄ , and the drain of the PMOS transistor M ₂₁₃ is connected to the NMOS transistor Drain of M ₂₁₅ .

The gate of the NMOS transistor _M215 is connected to the source of the high-voltage NMOS transistor _M210 , and its source is grounded; the gates of the NMOS transistors _M214 , _M211 , and _M208 are all connected to the gate of the NMOS transistor _M207 , Their sources are all grounded, wherein the drain of NMOS transistor _M211 is connected to the source of high-voltage NMOS transistor _M210 , the drain of NMOS transistor _M208 is connected to the source of high-voltage NMOS transistor _M206 , and the drain of NMOS transistor _M207 is connected to The source of the high-voltage NMOS transistor M ₂₀₅ ; the gate of the high-voltage NMOS transistor M ₂₁₀ is connected to the internal power supply V _DD , and its drain is connected to the drain of the high-voltage PMOS transistor M ₂₀₉ ; the source of the PMOS transistor M ₂₀₉ is connected to the input voltage V _IN , the gate of which is connected to the drains of the PMOS transistor _M202 and the high voltage NMOS transistor _M204 .

The PMOS transistors M ₂₀₁ and M ₂₀₂ constitute a current mirror, and their sources are connected to the input voltage V _IN , wherein the drains of the PMOS transistors M ₂₀₁ and M ₂₀₂ are respectively connected to the drains of the NMOS transistors M ₂₀₃ and M ₂₀₄ ; the high voltage The gate of the NMOS transistor _M204 is connected to the output threshold voltage V _CST of the analog dimming circuit in the dimming control unit 1, and is connected to the input voltage V _IN through the _fifth resistor R5, and its source is connected to the source of the NMOS transistor _M203 Both are connected to the drain of the high-voltage NMOS transistor _M206 ; the gate of the NMOS transistor _M203 is connected to the input voltage V1 through the _fourth resistor R4; the high _- voltage NMOS transistors _M205 and _M206 form a current mirror, wherein the NMOS The drain of the tube M ₂₀₅ is connected to the current source I _S2 .

Its current relationship is: $I_{\mathrm{D.}10}=I_{S2}\&times;\frac{{\left(\frac{W}{L}\right)}_{m206}}{{\left(\frac{W}{L}\right)}_{m205}}---\left(7\right)$

Wherein, I _S2 is the current source current, I _D10 is the drain current of the high-voltage NMOS transistor M ₂₀₆ , and W/L is the width-to-length ratio of the MOS transistor.

In this embodiment, the detection is performed by using the differential voltage signal generated on the _first resistor R1. Detection of the peak current is achieved by comparing the voltage drop V _SNS across the first resistor R ₁ with the current peak detection threshold voltage V _CST . The voltage input to the positive terminal of the comparator is V _IN -V _CST , and the voltage input to the negative terminal is V _IN -V _SNS . Once the peak current is detected, that is, V _SNS is greater than V _CST , Q ₁ is turned off and the on-time is over, and the comparator outputs a high level at this time.

The value of V _CST is determined by the input voltage V _ADJ1 of the non-inverting terminal of the amplifier in the dimming control unit 1. The amplifier adopts a negative feedback connection mode. Since R ₂ =5R ₅ , the current flowing through the switch NMOS transistor M ₁₀₁ It can be expressed as:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; ADJ</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; 5</span>}\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 5</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; )</span>$

Therefore, the peak current detection threshold V _CST is expressed as:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; CST</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; ADJ</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 9</span>}<span\; class="notranslate">\; )</span>$

In addition, the circuit also provides two methods for adjusting the detection threshold voltage V _CST , both of which are realized by changing the voltage value of V _ADJ1 .

1. V _ADJ1 is disconnected, and the reference voltage V _REF is directly provided as a driving voltage.

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; CST</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; ADJ</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; 5</span>}\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; ADJ</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1.20</span>}\mathrm{<span\; class="notranslate">\; V</span>}}{\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 240</span>}\mathrm{<span\; class="notranslate">\; mV</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 10</span>}<span\; class="notranslate">\; )</span>$

It is realized by directly providing V _ADJ1 voltage of 0-1.20V. In this way, the set value of V _CST varies between 0-240mV.

2. Connect the resistor R ₂ between the same direction terminal of the op amp and the ground to realize it. The current I _S1 will flow through the resistor R ₂ to generate the V _ADJ1 voltage. At this time, the V _CST voltage can be expressed as:

${{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; CST</span>}}}^{<span\; class="notranslate">\; \text{'}</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; ADJ</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 11</span>}<span\; class="notranslate">\; )</span>$

It can be seen from the peak current detection sampling unit 2 of the LED drive circuit of the above two embodiments that the core design of this unit is a comparator, and the switching speed of the comparator directly affects the accuracy of the system turn-on time and turn-off time. Will affect the operating point of the system, so the designed comparator should have as fast a switching speed as possible. Here, a two-stage comparator circuit is used to realize it, and the specific circuit structure is shown in Fig. 6 .

At the same time, the DC-DC converter adopted in this embodiment triggers the shutdown _of the main switching tube Q1 by comparing the voltage drop V _SNS on the _first resistor R1 with the peak current detection threshold voltage V _CST of the comparator circuit, without Requires an error amplifier and feedback network, resulting in faster response than traditional voltage control modes.

Example 3:

The dimming control unit 1 and the peak current detection sampling unit 2 of this embodiment are the same as those of the first embodiment.

7, the constant off-time control unit 3 of this embodiment includes a comparator 301, an RS flip-flop 302, an inverter 303 and an inverter 304, a NAND gate 305, a fourth capacitor C ₄ , an eighth resistor R ₈ and NMOS tube M ₃₀₁ . in:

In the comparator 301, its non-inverting input terminal is connected to the reference voltage V _REF , its inverting input terminal is connected to the drain of the NMOS transistor M ₃₀₁ , and is connected to the output voltage V _ADJ2 through the eighth resistor _R8 or through the fourth capacitor C ₄ is grounded, and its output terminal is connected to the reset terminal R of the RS flip-flop; On the input terminal of phase device 304; Said inverter 303, its input terminal connects the output signal V ₃ of peak current detection sampling unit 2; Described inverter 304, its output terminal connects on an input of NAND gate 305 The other input terminal of the NAND gate 305 is connected to the enable signal V _EN2 , and its output terminal is connected to the output voltage V ₂ ; the gate of the NMOS transistor M ₃₀₁ is connected to the output signal V ₃ of the peak current detection sampling unit 2 , whose source is grounded.

In the LED driving circuit of this embodiment, the turn-off time T _OFF is constant, which is mainly adjusted in advance by the eighth resistor R ₈ , the fourth capacitor C ₄ , and the output voltage V _ADJ2 . Since the circuit adopts a constant current driving method, I _LED will be well controlled, so the output voltage V _ADJ2 will be a constant value, which will not change with the input voltage and temperature.

At the initial moment of T _OFF , the voltage on the fourth capacitor _C4 is zero, and then the output voltage V _ADJ2 will provide charge to the capacitor, and the capacitor starts to charge, and the charging time constant is determined by _R8 and _C4 . When the voltage across the capacitor (V _COFF ) charges to equal the reference voltage V _REF , the off-time ends and the capacitor discharges to zero. The calculation formula of T _OFF is:

${{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; OFF</span>}}}^{<span\; class="notranslate">\; \text{'}</span>}<span\; class="notranslate">\; =</span>{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 8</span>}}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; \&times;</span>\mathrm{<span\; class="notranslate">\; ln</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; REF</span>}}}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; ADJ</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 12</span>}<span\; class="notranslate">\; )</span>$

It can be seen from the off-time T _OFF and T _OFF ' in the above-mentioned embodiment 1 and embodiment 3: it is determined by the eighth resistor R ₈ , the fourth capacitor C ₄ and a constant voltage V _ADJ2 , so once After determining their parameter values, the off time of the circuit is constant. At the same time, the constant off-time control mode LED drive circuit proposed in the present invention does not need an external compensation network, the loop compensation is simple, easy to implement, and convenient to control; and the switching frequency only increases with the increase of V _IN , and the system stability is good .

The above are only three best examples of the present invention, and do not constitute any limitation to the present invention. Obviously, under the conception of the present invention, various changes and improvements can be made to the circuit, but these are all included in the protection of the present invention.

Claims (5)

1. A digital-analog hybrid dimming LED drive circuit, characterized in that it comprises the following units: A dimming control unit (1), comprising an analog dimming circuit (11) and a digital dimming circuit (12), wherein the analog dimming circuit (11) is used to receive a driving voltage V _ADJ1 , and adjust the driving voltage V _ADJ1 voltage value to output the peak current detection threshold voltage V _CST1 , and input it to the peak current detection sampling unit (2); the digital dimming circuit (12) is used to receive the enable signal V _EN , and when the Under the control of the signal V _EN , the enable signal V _EN1 is output to the peak current detection sampling unit (2) and the constant off-time control unit (3), and the enable signal V _EN2 is output to the constant off-time control unit (3) at the same time ; The peak current detection sampling unit (2), configured to receive the peak current detection threshold voltage V _CST1 sent by the analog dimming circuit (11) in the dimming control unit (1) and the output enable sent by the digital dimming circuit (12) signal V _EN1 ; and under the control of the enable signal V _EN1 , the input voltage V _IN and the voltage V ₁ obtained by the input voltage V _IN through the voltage drop V _SNS are compared with the peak detection threshold voltage V _CST1 to realize the peak current detection, and input the output signal V ₃ to the constant off-time control unit (3); Constant off-time control unit (3): used to receive the enable signal V _EN1 and enable signal V _EN2 sent by the digital dimming circuit (12) in the dimming control unit (1), and simultaneously receive the peak current detection sampling unit ( 2) The output signal V ₃ sent; and under the control of the enable signal V _EN1 and the enable signal V _EN2 , when the peak current is detected, the input voltage V _ADJ2 is adjusted to obtain an output voltage V ₂ , and the output voltage V ₂ delivered to the power switch tube Q1 _; Power switch tube Q ₁ : used to receive the output voltage V ₂ sent by the constant off-time control unit (3), and generate a constant off-time T _OFF according to the output voltage V ₂ ; The input DC power supply is connected in parallel with the first capacitor C ₁ to obtain the input voltage V _IN , the input voltage V _IN and the voltage V ₁ at both ends of the first resistor R ₁ are connected to the peak current detection unit (2); the constant off-time control unit (3 ) output voltage V ₂ is connected to a driver Driver for controlling the on and off of the power switch tube Q ₁ ; the power switch tube Q ₁ is connected in parallel with the Schottky diode D ₁ and the second capacitor C ₂ , and is connected with The _first inductor L1 is connected in series. 2. The digital-analog hybrid dimming LED drive circuit according to claim 1, characterized in that, the analog dimming circuit (11) comprises an amplifier (101), an NMOS transistor M ₁₀₁ , a second resistor R ₂ , a second Three resistors R ₃ and current source _IS1 ; the digital dimming circuit (12) includes a first Schmitt trigger (102) and a second Schmitt trigger (104), an inverter (103), a PMOS Tube M ₁₀₂ , PMOS tube M ₁₀₄ , NMOS tube M ₁₀₃ , NMOS tube M ₁₀₅ and the third capacitor C ₃ ; wherein: Said amplifier ( ₁₀₁ ), its non-inverting input terminal is connected to the driving voltage V _ADJ1 , and grounded through the third resistor _R3 ; its inverting terminal is grounded through the _second resistor R2; its output terminal is connected to the gate of the NMOS transistor M101 pole; the drain of the NMOS transistor M ₁₀₁ is connected to the input threshold voltage V _CST1 of the peak current detection sampling unit (2), and its source is grounded through the second resistor R ₂ ; the input end of the current source _IS1 is connected to the internal power supply V _DD , and its The output terminal is connected to the ground through the third resistor _R3 , and connected to V _ADJ1 ; The first Schmitt trigger (102), its input terminal is connected to the drain of the NMOS transistor M ₁₀₃ , while connected to the positive pole of the _third capacitor C3, its output terminal is connected to the input terminal of the inverter (103) , and at the same time access the enable signal V _EN1 ; its power supply terminals are respectively connected to the internal power supply V _DD and ground; Described second Schmitt trigger (104), its input end is connected on the output end of inverter (103), connects the drain electrode of PMOS transistor M ₁₀₄ and NMOS transistor M ₁₀₅ simultaneously; Its output end is connected in constant On the enabling signal V _EN2 of an input terminal of the NAND gate (306) in the off-time control unit (3); its power supply terminal is connected to the internal power supply V _DD and the ground respectively; Described inverter (103), its input end is connected on the output end of the first Schmitt trigger (102), and its output end is connected on the gate of PMOS transistor M ₁₀₄ ; PMOS transistor M ₁₀₂ , its source PMOS transistor M ₁₀₄ , whose source is connected to internal power supply V _DD ; NMOS _transistor M ₁₀₃ , whose gate is connected to enable input signal V _EN , and whose source is grounded; The source of the NMOS transistor M ₁₀₅ is grounded, and the gate is connected to the enable input signal V _EN ; the negative electrode of the third capacitor C ₃ is grounded. 3. the LED drive circuit of digital-analog hybrid dimming as claimed in claim 1, is characterized in that, described peak current detects sampling unit (2), comprises inverter (201), current source I _S2 , the 4th resistor R ₄ , fifth resistor R ₅ , sixth resistor R ₆ , seventh resistor R ₇ , high voltage PMOS transistor M ₂₀₃ , high voltage PMOS transistor M ₂₀₅ , high voltage NMOS transistor M ₂₀₄ , high voltage NMOS transistor M ₂₀₆ , NMOS transistor M ₂₀₁ , NMOS tube M ₂₀₂ , NMOS tube M ₂₀₇ , NMOS tube M ₂₀₈ , NMOS tube M ₂₀₉ , NMOS tube M ₂₁₀ , NMOS tube M ₂₁₁ , NMOS tube M ₂₁₂ , NMOS tube M ₂₁₅ , NMOS tube M ₂₂₀ , NMOS tube M ₂₂₁ , NMOS tube M ₂₂₃ , NMOS tube M ₂₂₄ , NMOS tube M ₂₂₆ , PMOS tube M ₂₁₃ , PMOS tube M ₂₁₄ , PMOS tube M ₂₁₆ , PMOS tube M ₂₁₇ , PMOS tube M ₂₁₈ , PMOS tube M ₂₁₉ , PMOS tube M ₂₂₂ and PMOS tube M ₂₂₅ ; wherein: The inverter (201), its input end is connected to enable input signal V _EN1 , and its output end is connected to NMOS transistor _M207 ; The input terminal of the current source _IS2 is connected to the internal power supply V _DD , and its output terminal is connected to the drains of the NMOS transistors M ₂₀₇ and M ₂₀₈ , and connected to the gates of the NMOS transistors M ₂₀₈ and M ₂₀₉ ; NMOS transistors M ₂₀₈ , M ₂₀₉ , M ₂₁₀ , M ₂₁₁ , and M ₂₁₂ form a row of current mirrors, and the gates of NMOS transistors M ₂₀₈ , M ₂₀₉ , M ₂₁₀ , M ₂₁₁ , and M ₂₁₂ are all connected to the gate of NMOS transistor M ₂₀₈ Both poles and sources are grounded; The drain of the NMOS transistor M ₂₀₉ is connected to the sources of the NMOS transistors M ₂₀₁ and M ₂₀₂ forming a differential pair; the drain of the NMOS transistor M ₂₁₀ is connected to the source of the high-voltage NMOS transistor M ₂₀₄ ; the NMOS transistor M The drain of ₂₁₁ is connected to the source of the high-voltage NMOS transistor M ₂₀₆ , and the drain of the NMOS transistor M ₂₁₂ is connected to the drain of the PMOS transistor M ₂₁₃ ; The NMOS transistors _M201 and _M202 form a differential pair, their drains are respectively connected to the input voltage V _IN through the _sixth resistor R6 and the seventh resistor _R7 , and their gates are respectively connected through the fourth resistor R ₄ and the fifth resistor R ₅ are connected to the input voltage V ₁ and V _IN ; The high-voltage PMOS transistors M ₂₀₃ and M ₂₀₅ and the NMOS transistors M ₂₀₄ and M ₂₀₆ are high-voltage drain transistors, wherein the sources of the high-voltage PMOS transistors M ₂₀₃ and M ₂₀₅ are connected to the differential pair of NMOS transistors M ₂₀₁ and M ₂₀₂ respectively. On the drain, the drains of the high-voltage PMOS transistors M ₂₀₃ and M ₂₀₅ are connected to the drains of the NMOS transistors M ₂₀₄ and M ₂₀₆ respectively, and the gates of the high-voltage PMOS transistors M ₂₀₃ and M ₂₀₅ are both connected to the input voltage V _B1 ; The gates of the transistors M ₂₀₄ and M ₂₀₆ are both connected to the input voltage V _B2 , and the sources of the high-voltage NMOS transistors M ₂₀₄ and M ₂₀₆ are respectively connected to the gates of the NMOS transistors M ₂₁₉ and M ₂₁₈ forming a differential pair; The PMOS transistors M ₂₁₃ and M ₂₁₆ constitute a current mirror, their sources are connected to the internal power supply V _DD , and the drain of the PMOS transistor M ₂₁₆ is connected to the sources of the PMOS transistors M ₂₁₈ and M ₂₁₉ that form a differential pair; The source of the tube M ₂₁₇ is connected to the internal power supply V _DD , the gate is connected to the enable signal V _EN1 , and the drain is connected to the drain of the PMOS tube M ₂₁₃ ; The PMOS transistors M ₂₁₄ and M ₂₂₂ form a current mirror, and their sources are connected to the internal power supply V _DD , wherein the drain of the PMOS transistor M ₂₁₄ is connected to the drain of the NMOS transistor M ₂₁₅ , and the drain of the PMOS transistor M ₂₂₂ is connected to the NMOS transistor The drain of M ₂₂₃ ; the NMOS transistors M ₂₁₅ and M ₂₂₀ also constitute a current mirror, and their sources are all grounded, wherein the drain of the NMOS transistor M ₂₂₀ is connected to the drain of the PMOS transistor M ₂₁₈ forming a differential pair; The above-mentioned NMOS transistors M ₂₂₁ and M ₂₂₃ also constitute a current mirror, their sources are all grounded, and the drain of the NMOS transistor M ₂₂₁ is connected to the drain of the PMOS transistor M ₂₁₉ that forms a differential pair; The gate of the NMOS transistor M ₂₂₄ is connected to the enable signal V _EN1 for controlling its switching state, its drain is connected to the drain of the NMOS transistor M ₂₂₃ , and its source is grounded; the PMOS transistor M ₂₂₅ and the NMOS The tube M ₂₂₆ constitutes an inverter, the input terminal of the inverter is connected to the drain of the NMOS tube M ₂₂₃ , and the output terminal is connected to the output signal V ₃ , wherein the source of the PMOS tube M ₂₂₅ is connected to the internal power supply V _DD , and the NMOS tube M 225 is connected to the internal power supply V DD . The source of tube M ₂₂₆ is grounded. 4. The LED driving circuit of digital-analog hybrid dimming as claimed in claim 1, wherein the constant off-time control unit (3) includes an amplifier (301), a comparator (302), an RS flip-flop (303), first inverter (304), second inverter (305), NAND gate (306), fourth capacitor C ₄ , eighth resistor R ₈ , PMOS transistor M ₃₀₁ , PMOS transistor M ₃₀₂ , PMOS transistor M ₃₀₃ and PMOS transistor M ₃₀₄ , NMOS transistor M ₃₀₅ and NMOS transistor M ₃₀₆ ; wherein: In the amplifier (301), its non-inverting input terminal is connected to the input voltage V _ADJ2 , its inverting input terminal is grounded through the eighth resistor _R8 , and its output terminal is connected to the gate of the NMOS transistor M ₃₀₅ ; the comparator (302), its The non-inverting input terminal is connected to the reference voltage V _REF , its inverting terminal is connected to the drain of the PMOS transistor _M303 , and its output terminal is connected to the reset terminal R of the RS flip-flop; the RS flip-flop is composed of two NAND gates, and its set The terminal S is connected to the output terminal of the first inverter (304), and its output terminal is connected to the input terminal of the second inverter (305); the input terminal of the first inverter (304) is connected to The output signal V ₃ of the peak current detection sampling unit (2), the second inverter (305), the output terminal of which is connected to one input of the NAND gate (306); the other of the NAND gate (306) One input terminal is connected to enable signal V _EN2 , and its output terminal is connected to output voltage V ₂ ; The PMOS transistors M ₃₀₁ , M ₃₀₂ , M ₃₀₃ and M ₃₀₄ form a current mirror, wherein the sources of the PMOS transistors M ₃₀₁ and M ₃₀₂ are connected to the internal power supply V _DD , and the drains are respectively connected to the PMOS transistors M ₃₀₄ and On the source of M ₃₀₃ ; by taking the same tube size, the current relation is: I _D6= I _D7= I _D8= I _D9 ; The drain of the PMOS transistor _M304 is connected to the drain of the NMOS transistor _M305 , the drain of the PMOS transistor _M303 is grounded through the fourth capacitor _C4 ; the source of the NMOS transistor _M305 is grounded through the eighth resistor _R8 , The gate of the NMOS transistor _M306 is connected to the output signal _V3 of the peak current detection sampling unit (2), its drain is connected to the inverting input terminal of the comparator (302), and its source is grounded. 5. The digital-analog hybrid dimming LED drive circuit according to claim 1, characterized in that, the peak current detection sampling unit (2) comprises an inverter (201), a fourth resistor R ₄ , a fifth resistor R ₅ , PMOS tube M ₂₀₁ , PMOS tube M ₂₀₂ , PMOS tube M ₂₀₅ , PMOS tube M ₂₀₆ , PMOS tube M ₂₀₉ , PMOS tube M ₂₁₂ , PMOS tube M ₂₁₃ , NMOS tube M ₂₀₃ , NMOS tube M ₂₀₄ , NMOS tube M ₂₀₇ , NMOS tube M ₂₀₈ , NMOS tube M ₂₁₀ , NMOS tube M ₂₁₁ , NMOS tube M ₂₁₄ and NMOS tube M ₂₁₅ ; where: The inverter (201), its input end is connected to the drain of the PMOS transistor M ₂₁₃ , and its output end is connected to the gate of the NMOS transistor M ₃₀₆ in the constant off-time control unit (3), for controlling its switch; The PMOS transistors M ₂₁₂ and M ₂₁₃ form a current mirror, their sources are connected to the internal power supply V _DD , the drain of the PMOS transistor M ₂₁₂ is connected to the drain of the NMOS transistor M ₂₁₄ , and the drain of the PMOS transistor M ₂₁₃ is connected to the NMOS transistor M ₂₁₅ the drain; The gate of the NMOS transistor M215 is connected to the source of the high-voltage NMOS transistor M210, and its source is grounded; the gates of the NMOS transistors M214, M211, and M208 are all connected to the gate of the NMOS transistor M207, and their sources are all grounded , wherein the drain of the NMOS transistor M211 is connected to the source of the high-voltage NMOS transistor M210, the drain of the NMOS transistor M208 is connected to the source of the high-voltage NMOS transistor M206, the drain of the NMOS transistor M207 is connected to the source of the high-voltage NMOS transistor M205; the high-voltage NMOS transistor The gate of M210 is connected to the internal power supply VDD, and its drain is connected to the drain of the high-voltage PMOS transistor M209; the source of the PMOS transistor M209 is connected to the input voltage VIN, and its gate is connected to the drains of the PMOS transistor M202 and the high-voltage NMOS transistor M204; The PMOS transistors M ₂₀₁ and M ₂₀₂ constitute a current mirror, and their sources are connected to the input voltage V _IN , wherein the drains of the PMOS transistors M ₂₀₁ and M ₂₀₂ are respectively connected to the drains of the NMOS transistors M ₂₀₃ and M ₂₀₄ ; the high voltage The gate of the NMOS transistor _M204 is connected to the output threshold voltage V _CST of the analog dimming circuit in the dimming control unit 1, and is connected to the input voltage V _IN through the _fifth resistor R5, and its source is connected to the source of the NMOS transistor _M203 Both are connected to the drain of the high-voltage NMOS transistor _M206 ; the gate of the NMOS transistor _M203 is connected to the input voltage V1 through the _fourth resistor R4; the high _- voltage NMOS transistors _M205 and _M206 form a current mirror, wherein, The drain of the NMOS transistor M ₂₀₅ is connected to the current source I _S2 .