CN103777922B - Count of predictions device - Google Patents
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Abstract
According to exemplary implementation scheme, such as digital signal processor（DSP）Processor possess the register as count of predictions device.The count of predictions device can include more than two useful values, and in addition to as the condition that executes instruction, can also track the nesting level in cycling or conditional branching.In some cases, the count of predictions device can be configured to single-instruction multiple-data（SIMD）SIMD in pattern or register（SWAR）Pattern is operated.
Description
The cross reference of related application
This application claims submission on October 23rd, 2012 and the U.S. Provisional Application No. of entitled " Predicate Counter "
The priority of 61/717, No. 541, the entire disclosure of which are incorporated by reference.It submits on December 19th, 2012 and entitled
" Memory Interconnect Network Architecture for Vector Processors' " is same in application
The full content of U. S. application the 13/720,624th (" 624 application ") be also incorporated herein by reference.
Technical field
The disclosure relates generally to parallel processing, and is more particularly related to a kind of Vector Processing using count of predictions device
Device.
Background technology
Parallel processing is typically the processor by being used to optimize processing application program（For example, for optimizing digital letter
Number processing application program digital signal processor（DSP））To implement.Processor can be used as single-instruction multiple-data（SIMD）Or number
According to parallel processor to realize parallel processing.In SIMD operation, one is instructed the multiple processing elements for being sent to processor,
Wherein each processing element independently can perform same operation to different data.Requirement to lasting high yield and increase performance
Constantly increase and have resulted in SIMD in register（SWAR）, wherein processing element may act on multigroup number in its related register
According to.For example, 32 bit registers can include four 8 data, eight 4 data or three 10 data, each of which can
By a processing element parallel work-flow.
Although implementing in the hardware of processor, SWAR is relatively cheap, and SWAR faces many from the viewpoint of programming
Challenge.For example, SWAR programs the typically required high-level language from the not part of ISO C or C++ standards（Such as C/C++）'s
Inherently, inline assembler and/or proprietary vector data types（Such as float2, int4, short4, etc.）.Because these are programmed
Option（Proprietary vector data types, intrinsic and/or inline assembler）It is peculiar for processor, so SWAR programmings are difficult to transplant original
There is code.In addition, because SWAR programming to vector processor addition additional level parallel processing, conventional processors due to
Ensure that processor identifies the parallel work-flow of two grades（Two-way simultaneous）And increase the burden of programmer：（Use SWAR's）Processing
The parallel processing of a grade in element and across processor vector location processing element another grade parallel processing.
Therefore, although being commonly available to it for performing the existing processor architecture of parallel processing and correlation technique and wishing purpose,
It is not entirely satisfactory in all respects.
Description of the drawings
Basis will be appreciated that the disclosure as detailed below after attached drawing is read.The disclosure is emphasized：It is put into practice according to industrywide standard,
Each feature is not necessarily to scale and is for illustration purposes only.In fact, in order to clearly discuss, can arbitrarily increased or decrease
The size of each feature.
Fig. 1 is the block diagram for the exemplary digital signal processor for including count of predictions device.
Fig. 2 is configured to perform the block diagram of the register in register in the digital signal processor of SIMD operation.
Specific embodiment
General introduction
On the one hand, the invention discloses a kind of processor, including：Processing element；Sequencer, be configured to by
The instruction that condition can perform is provided to processing element, and conditional is provided by the prediction encoded in count of predictions device；And prediction
Counter register is configured to receive more than two significant values and provides its value as count of predictions.
On the other hand, the invention discloses a kind of method performed by computer, including：It receives and count of predictions device quilt
It configures to receive more than two useful relevant instructions of value；If count of predictions device is the first value, then is executed instruction；If with
Count of predictions device is not the first value, then ignores instruction.
In another embodiment, the invention discloses a kind of visible computer readable medium, store thereon when implemented
Command processor carries out the software instruction of the following：Count of predictions device is read, there are two above useful values for count of predictions utensil；
Reading conditions instruct；If count of predictions device is the first value, then is executed instruction；If count of predictions device is not the first value, that
Ignore instruction and the value manipulation count of predictions device based on count of predictions device.
The disclosed exemplary embodiments
The many different embodiments or example of the following open different characteristic for providing to implement the disclosure.It is described below
Component and the particular instance of configuration are to simplify the disclosure.Certainly, these are only examples and are not intended to be limited.In addition, this public affairs
Opening can repeat reference numerals and/or letter in various embodiments.This repetition is in order at simplified and specific purpose, and itself
Relation between not indicating that each embodiment of discussion and/or configuring.Different embodiments can have the advantages that it is different, and
Any embodiment is without specific advantages.
Branch prediction is related to linearisation branch operation, this can substantially improve cache performance and instruction pipeline.
In traditional branch's topology, conditional order can be in the form of the following：
Because the branch to new position can destroy assembly line and memory cache, performed for dock cycles
CC condition code may be prohibitively expensive.Prediction alleviates branch by linearisation instruction as follows to be influenced：
{predicate:condition}branch-A;
{predicate:!condition}branch-B;
Therefore appearance is mutually inline for prediction instruction, but is only being attached to being performed when being predicted as true for each instruction.Therefore,
Prediction will control it is interdependent be transformed into data-dependent, this enables a processor to perform many operations parallel without jeopardizing assembly line and height
Speed caching.
According to the exemplary implementation scheme of the disclosure, integer counter may be used as branch prediction, so as to instruction encoding
Predicted state and nested condition.For example, such as particular value of " 0 " is used as allowing the prediction executed instruction, and any nonzero value is then
Instruction should not execute instruction.
For following discussion purpose, " count of predictions device " is used as the counter that PREDICTIVE CONTROL instruction performs, and is different from
Simple boolean's " mark " has more than two useful values.Count of predictions device therefore can be（Such as）Nested IF-ELSE-
ENDIF structures or nested Xun Huan interior coding predicted state and nested condition.Unique value can enable with the relevant instruction of counter, and
All other value so as to indicate some nesting level disable dependent instruction.If for example, counter is arranged to zero, then allow
Normal perform is instructed by counter controls, otherwise forbids executing instruction.In other exemplary embodiments, with nonrestrictive
Exemplified by example, unique value can be the maximum of 1, integer registers（MAXINT）, symbol integer registers negative peak（-
MAXINT）With it is infinite, negative infinite and can represent nonumeric by the special code in register.
Following article is described in more detail, and count of predictions device is useful for linearisation instruction and single instrction SWAR operations.
Description, Fig. 1 are the exemplary digital signal processors according to various aspects of the disclosure（DSP）100
Schematic block diagram.For clarity and the novel concept of the disclosure is more fully understood, Fig. 1 has been simplified.It can be in DSP100
Middle addition additional features, and some in replaceable in other embodiments of DSP100 or elimination features described below.
DSP100 can include control unit 110, memory 120 and computing array 130.In instances, control unit 110
DSP100 can be performed the core processor of calculating and data processing function by being formed with computing array 130.Some realities of DSP100
Applying scheme includes other components, such as performing the microcontroller of micro-controller instructions, direct memory access（DMA）Unit
With each interface to device outside chip.In addition, although memory 120 is shown here as a logical block, this field one
As technical staff will be recognized that：Memory 120 can include main system memory, the core on chip cache of different levels and/
Or other volatibility or nonvolatile memory technologies.
Control unit 110 promotes the program of DSP100 to perform.Control unit 110 can include arithmetic logic unit and data
Address generates（ALU-DAG）Unit 112, program sequencer 114 and program storage 116.Control unit 110 can also wrap
Include other components, such as instruction cache, timer and command register.ALU-DAG units 112 support general purpose integer to calculate
And to storage address supply address.For example, when in memory 120 and register（All computing arrays as described below 130
Register file）Between transmit data when, ALU-DAG112 provide storage address.ALU-DAG units 112 can give address provision
Data storage（For example, memory 120）And/or program storage 116.Program sequencer 114 provides IA
To program storage 116 to carry out instruction taking-up.Program storage 116 is by the program storage that DSP100 is implemented to program data
（The program data being such as stored in memory 120）And go back program storage data.Program includes referring to one or more
The instruction set of order, and DSP100 is by taking out instruction, solution code instruction and executing instruction come implementation procedure.In instances, program can
To include implementing different DSP algorithms（Algorithm including depending on count of predictions device）Instruction set.
Memory 120 stores the information/data handled by DSP100（Data storage）, implemented by DSP100 to handle letter
The program of breath/data（Program storage）Or its combination.In the embodiment described, memory 120 interlocks with multistage
Memory construction so that memory 120 include memory section M1, M2, M3 ..., Mn, wherein n be the memory of memory 120
The sum of section.In instances, memory 120 is random access storage device, such as static random-access memory（SRAM）, dynamic
RAM（DRAM）, quick flashing or other suitable memory technologies.In instances, one or more memory section M are individual RAM.
Alternatively, in each embodiment, memory 120 is the memory of another suitable type.
144 interconnection control unit 110 of interference networks 140, interference networks 142 and interference networks, memory 120 and calculating battle array
Row 130, so as to provide communication path between control unit 110, memory 120 and computing array 130.Interference networks 140, mutually
Networking network 142 and interference networks 144 can include a bus, more buses, traffic flow prediction, single stage network, multi-level networks
Network, other types of interference networks or its combination.Instruction and data address is dealt by control unit 110 via interference networks 142
Computing array 130.Therefore the address of instruction and data is transmitted to computing array 130 by interference networks 142 via interference networks 142
Each processing element PE.The transmission of interference networks 144 is from memory（Such as memory 120, program storage 116, Qi Tacun
Reservoir or its combination）Data and/or instruction so that the content of any register in DSP100 can be transmitted to any other post
Storage or any memory location, and memory 120 can be by data operand（Value）Computing array 130 is provided.
In certain embodiments, computing array 130 include multiple processing element PE1, PE2, PE3 ... PEN, wherein N
It is the sum of the processing element of computing array 130.In instances, computing array 110 can include four processing elements（PE1、
PE2, PE3 and PE4）.PE pairs of processing element（Such as）DSP algorithm performs numerical value processing.Processing element PE can be grasped independently, parallel
Make or be used as SIMD engines.In this example, each processing element PE can be vector processor.Alternatively, processing element PE can
To be the combination of scalar processor and vector processor.
Processing element PE each includes respective computing unit（CU）152.In the embodiment described, computing unit
152 can be identical, but the disclosure wishes the embodiment that wherein computing unit 152 is different.The disclosure also wants to one of them
Or multiple processing element PE do not include the configuration of computing unit 152.In this example, computing unit 152 is each patrolled including arithmetic
Collect unit（ALU）, multiplier accumulator（MAC）, shift unit, other computing units or its combination.ALU can perform arithmetic sum logic fortune
Calculate, such as addition, subtraction, negate, be incremented by, successively decreasing, absolute value, and（AND）Or（OR）, exclusive or（EXCLUSIVE OR）, it is non-
（NOT）, division primitive, other arithmetical operations, other logical operations or its combination.Exemplary MAC can perform multiplying and
Multiplying again and accumulating operation, such as single cycle multiplies, multiplies again again/addition, multiply/subtraction, other computings or its combination again.Shift unit can be held
Row logic and arithmetic shift, bit arithmetic, normalization, anti-normalization, index derivative operation, other computings or its combination.It can be right
Fixed point and floating-point format perform each arithmetical operation, logical operation and other computings.In each embodiment, ALU, MAC
And/or shift unit includes relative register.
Processing element PE can also each include respective register file 154.In the embodiment described, register
Heap 154 can be identical, but the disclosure wishes the embodiment that wherein register file 154 is different.The disclosure also wants to it
Middle one or more processing element PE does not include the configuration of register file 154.Register file 154 is included in processing element PE and number
According to interference networks（Such as interference networks 144）Between transmit the register of data and storage result.In this example, register file
154 may include respective general register group 155, be posted including the general of width with the design requirement depending on DSP100
Storage, such as 32 general registers, 40 general registers, 64 general registers, 128 general registers, Qi Takuan
The general register of degree or its combination.For the purpose of following discussion, general register 155 includes 32 general registers.
In this example, register file 154 each includes respective prediction register 158, can be configured to fixed count of predictions device.
Register file 154 may include the extra register for the design requirement for following DSP100.In addition, in each embodiment, prediction
Register 158 can be the general register 154 from general register group 155.In an exemplary embodiment, each
PE includes at least one special count of predictions device 158 up to 32 bit wides.In other embodiments, each PE can include multiple
Count of predictions device.
DSP100 can perform different parallel work-flows.For example, during one cycle, processing element PE can be with（Via interconnection
Network 142）Access instruction is simultaneously（Via interference networks 144）N number of data operand from memory is accessed to synchronize
Processing.In SIMD patterns, DSP100 can be with the multiple data flows of parallel processing.For example, when in SIMD patterns, DSP100 exists
One can be instructed via interference networks 142 each or multiple processing element being dispatched in processing element PE in one cycle
PE；Via the loading of interference networks 144 from memory（Memory 120, program storage 116, other memories or its combination）
N number of data set, each processing element PE loads a data set（In instances, each data set can include two data
Operand）；One instruction is synchronously performed in processing element PE；And it will be stored from the data result synchronously performed
In memory 120.
In certain embodiments, DSP100 can also carry out SIMD in register（SWAR）, any of which processing element
The register of PE（For example, general register）It can be divided into more than one processing channel so that any processing element PE can be individually
Parallel work-flow is performed to its respective processing channel.For example, in SWAR patterns, any processing element PE can hold n channel
Row parallel work-flow, each channel are k/n bit wides, and wherein k is the width in units of the position of register.
Fig. 2 schematically illustrates the processing element with that can implement the SWAR according to various aspects of the disclosure（Such as
The processing element PE of DSP100）Relevant exemplary register group.In fig. 2, one group of register includes register R1, register
R2 and register R3, wherein using register R1 and the element of register R2（Data operand）Perform the fortune of such as add operation
OP is calculated to generate result in register R3.Register R1, register R2 and register R3 may be such as from general deposit
The general register of device group 155.In this example, wherein general register is 32 bit wides（k=32）, it is any in SIMD patterns
Processing element PE can perform 32 bit units being stored in register R1 and R2 and operate and place the result in register R3.For
Promote this example, in SWAR patterns, register R can be divided into more than one processing channel to carry out parallel work-flow so that
Any processing element PE can be to being stored in two channels of 16 bit units in register R1 and R2（L1 and L2）Perform parallel behaviour
Make and place the result in register R3（Referred to as 2 × 16 SWAR processing）Or 8 bits to being stored in register R1 and R2
Four channels of part（L1 to L4）It performs parallel work-flow and places the result in register R3（Referred to as 4 × 8 SWAR processing）.
Wider data type is supported to digital signal processor（64 floating-points, 32 plural numbers etc.）It is high performance will
Seek the processing element for constantly increasing and causing to increase digital signal processor（The processing element PE of such as DSP100）Interior calculating power
And register width.These wider registers are increased by implementing SWAR compared with small data type（Such as 32 floating-points, 16 it is solid
Fixed point etc.）Digital signal processor performance variation.For example, DSP100 can be by implementing SWAR and not adding more processing
It is performed as soon as possible in the case of element twice to four operations.There are four processing elements with 32 bit wide registers wherein
In the example of PE1, PE2, PE3 and PE4, DSP100 can perform four parallel in same time amount with SIMD or non-SIMD patterns
32 bit arithmetics are performed eight parallel work-flows with 2 × 16 SWAR patterns or perform 16 parallel behaviour with 4 × 8 SWAR patterns
Make.Similarly, wherein processing element PE have 128 bit wide registers example in, DSP100 can in same time amount with
SIMD or non-SIMD patterns are performed four parallel 128 bit arithmetics, eight parallel 64 bit arithmetics are performed with 2 × 64 SWAR patterns,
16 parallel 32 bit arithmetics are performed with 4 × 32 SWAR patterns, perform 32 parallel 16 with 8 × 16 SWAR patterns
Computing performs 64 parallel 8 bit arithmetics with 16 × 8 SWAR patterns.
Although implementing within hardware, SWAR patterns are relatively cheap, and SWAR faces many choose from the viewpoint of programming
War.For example, SWAR programs the typically required high-level language from the not part of ISO C or C++ standards（Such as C/C++）Consolidate
Have, inline assembler and/or proprietary vector data types（Such as float2, int4, short4, etc.）.Because these programming choosings
（Proprietary vector data types, intrinsic and/or inline assembler）It is peculiar for processor, thus SWAR programming be difficult to transplant it is original
Code.In addition, because parallel processing of the SWAR programmings to vector processor addition additional level, at conventional digital signal
Device is managed as it ensure that DSP100 identifies the parallel work-flow of two grades（Two-way simultaneous）And increase the burden of programmer：（It uses
SWAR's）The parallel processing of a grade in processing element and across vector location processing element another grade parallel place
Reason.
Advantageously, as disclosed herein and as further described in ' 624 application, the disclosure is exemplary
DSP100 makes programmer（With the compiler for being accordingly used in DSP100）Parallel processing element can be regarded as to a vector channel,
In each handle channel（SWAR channels）It is counted as respective processing element.Each processing element PE can be divided into identical quantity wherein
Processing channel example in, the quantity that the effective quantity of processing element is considered as equal to actual treatment element by programmer is multiplied by often
The processing of a processing element（SWAR）The quantity of channel.Therefore, exist wherein and support four processing channels（For example, support 4 ×
The 32 bit wide registers of 8 SWAR）Four processing elements PE1, PE2, PE3 and PE4 example in, from the viewpoint of programmer
（With the viewpoint of therefore compiler）From the point of view of, the effective quantity of processing element is 16（Quantity × each PE of effective number=PE of PE
SWAR channels quantity=4 × 4=16）.There are eight processing elements and each processing element wherein to support two processing letters
Road（For example, two 32 floating-point operations）Another example in, from the viewpoint of programmer, the effective quantity of processing element is
16（Quantity=8 × 2=16 of the SWAR channels of the quantity of effective number=PE of PE × each PE）.In applying such as ' 624 in more detail
Description, DSP100 successfully carry out SWAR processing by implementing the following by programmer（Particularly, two-way simultaneous）：（1）
Based on processing channel（SWAR channels）Shielding,（2）Based on processing channel and use（Such as）The condition of count of predictions device performs,
（3）Across processing channel and/or across processing element execution reduction operations and/or（4）Address is had independently produced based on processing channel.
These mechanism greatly reduce the programming effort needed for DSP100.
The different embodiments of the count of predictions device in processor are described below.For clarity, some logic work is provided
For exemplary false code.In various embodiments, the mixed signal and DSP invented using such as Analog Devices companies design skill
Art（It is fully incorporated by reference hereby）Described in concept and processor carry out the embodiment.In each example
In, the following part for operating the machine instruction for being embodied as machine instruction or also handling other things.For example, counter is set to predict
It may have a negative impact to the arithmetic instruction of such as setting flag.
In each embodiment, one group of count of predictions device controls single-instruction multiple-data（SIMD）Instruction architecture, wherein often
A SIMD channels are controlled by different count of predictions devices.
IF-ELSE-ENDIF structures
In an exemplary architecture, count of predictions device control IF-ELSE-ENDIF structures.IF-ELSE-ENDIF structures
It is controlled by three discrete statements or primitive operation（primitive operation）：IF, ELSE and ENDIF.Because in some feelings
These are not necessarily the available discrete command of programmer under condition, so it is referred to as primitive operation or primitive.More precisely, its
It can be the inside operation of other user's accessible instructions.In other cases, it can be user's accessible instructions, but its
The specific name that need not have is defined herein.Three Operation Definitions are as follows：
IF：If depends on count of predictions device（" counter " in these examples）With the condition to be tested（" condition "）.Such as
Fruit counter be 0 and condition be true, then do not take any action, it is intended that counter remains 0, this allows to perform following finger
Order.Following any code will be called "true" until encountering false condition.For example, counter will be in nested " if " sound of following three
0 is remained in bright, it is assumed that A, B and C are entirely true：
Because counter remains 0 above in example, operation1 () is performed.
Continue to define IF, if counter is 0 and condition is vacation, then counter is incremented to 1, it is intended that will not perform down
Row instruct and enter "false" branch（For example, if A is false in previous case, then " if (B) " and " if (C) " belongs to vacation
Branch and any code should not be performed）.In said case, counter is used only saturation arithmetic and is incremented by（In other words, count
The high-end quilt of device " clamping down on " is in maximum, such as the max-int of count of predictions device or low side " being clamped down on " are 0）.IF can be as follows
It writes in pseudocode：
ELSE：Else acts only on counter.If counter is just 1, then is reached in prior instructions in false ramification
Final nesting level（If there is）, it is intended that " else " condition should be performed（Without performing " if " condition, because if performing " if "
Condition, then counter will be 0）.Therefore counter is arranged to 0, this allows to perform instructions（That is, " else " point
Branch）.If counter is 0, then performs " if " branch of this " else " branch（And any follow-up nesting of expansion）, but should not
Perform this branch.Therefore counter is arranged to 1, this will forbid performing instructions.If counter is any other
Value, then it is not taken any action and will not perform instructions.ELSE can be write in pseudocode as follows：
ENDIF：As ELSE, EDNIF acts only on counter.If counter non-zero, then this is false cycling
Nested branches, and counter successively decreases.Otherwise, any action is not taken.ENDIF instruction the result is that：It is stated when meeting ENDIF
The nesting level of Shi Yici " expansion " conditional logic.ENDIF can be write in pseudocode as follows：
IF, ELSE and ENDIF operation are appeared in the instruction stream with the arithmetic instruction by counter prediction.IF、ELSE
Control area nested with the telltale mark of ENDIF operations.
For example, simple nesting if-else Xun Huans can be unfolded under prediction.Traditional non-pre-
It surveys in language, cycling can write as follows：
Therefore, if A is true, then no matter how B only performs operation1 ().If A be false and B be it is true, that
Perform operation2 () and operation3 ().If A is that false and B is true, then only performs operation2 ().
Using the IF-ELSE structures of above-mentioned prediction, following table can be constructed.
In other exemplary embodiments, one group of count of predictions device can control SIMD instruction collection.In this case,
Count of predictions device can be operated by IF, ELSE and the ENDIF that can carry out SIMD and set.At this point, above-mentioned puppet is applied again
Code, wherein " counter " represents one group of counter and condition represents the vector of Boolean.
Step cycle
In another exemplary embodiment, count of predictions device can be used to implement SIMD step cycles（Such as June 29 in 2012
Day submission and the same U.S. Patent Application No. 13/537,731 in application of entitled " Staged Loop Instructions "
Disclosed in number, it is incorporated herein by reference）.In this case, to each stage of software flow wire type Xun Huan
Count of predictions device group is provided.Two primitive, i.e. LOOP and NEXT_STAGE are provided to SIMD step cycles embodiment.LOOP is grasped
Work is the preceding execution of the first instruction in the circulating cycle.NEXT_STAGE operation separation is unfolded the copy of cycle and is also to be held before cycling
Row.
LOOP：Following pseudocode provides the behavior of LOOP primitive.As previous primitive, LOOP can be that user may have access to finger
Order can be provided as other instruction institutes inherently.In following pseudocode, NUM_LANES indicates the quantity of processing element, and
COUNTER_GROUPS indicates the number in stage." Iters " represents the total degree of Xun Huan repeatedly.
Individual operations in SIMD step cycles are numbered with the stage.In this example, each stage numbers counts to prediction
Number device group indexes.For example, expansion dot product cycle may be as hereafter, wherein with { } given Stage Counting：
It is following illustrate provide example, wherein NUM_LANES=8, NUM_COUNTER_GROUPS=4, Iters=13 and
PredCounter [0] is entirely initially zero.Each stage is to be performed after its input is calculated in the relatively low number stage and each
Stage is initially in channel 0 to 7 and then performed in channel 0 to 4, repeatedly 13 times in total.
Another exemplary scheme for implementing prediction to SIMD or vector processor includes the use of mask register, wraps
Include prediction bits.The result of calculation of each position control element.This prediction scheme can be used for sub- word SIMD and/or buffer（SWAR）
Interior SIMD operation.Advantageously, the needs to independent prediction bits can be eliminated using count of predictions device.
It is nested
Some embodiments of this specification also realize the embedding of nested IF-ELSE-ENDIF and SIMD step cycles structure
Set.For this purpose, it can be combined and SIMD IF, ELSE, ENDIF and the relevant operation of step cycle primitive.
In an exemplary embodiment, SIMD step cycles nesting wherein the stage 0 counter be used as prediction
In IF-ELSE-ENDIF regions.When the original state into the counter group that the stage 0 is preserved when cycling, and then to every
The counter is set in a NEXT_STAGE operations and recovers the state when being exited from cycling.It is not opened during into Xun Huan
The channel will not be activated.
In other exemplary embodiments, IF-ELSE-ENDIF regions are nested in SIMD step cycles.In this feelings
Under condition, semanteme is suitable for being nested in IF-ELSE-ENDIF boxes non-deployed, in non-software pipeline system Xun Huan.When cycling is in
During software flow wire type, ENDIF operations can be in the stage of corresponding IF or ELSE be later than.In this case, this will be repaiied
Change different count of predictions device groups.ENDIF successively decreases the counter for therefore falsely causing its modification.And only beyond the stage 0
All count of predictions devices can be initialized as MAX.If MAX is likely larger than the maximum number in stage, then counter will not
It is decremented to zero.For example, it is contemplated that this non-software pipeline system cycles：
This Xun Huan can be into following software flow wire type：
In following exemplary embodiment, NUM_LANES=8, NUM_COUNTER_GROUPS=4, Iters=13 and
PredCounter [0] is entirely initially zero.If the value loaded in the stage 0 is less than zero, then just performs the storage in the stage 1.
SIMD in register
In an exemplary embodiment, count of predictions device is controlling SWAR to instruct.Exemplary SWAR machines can be supported
Regular length vector, wherein the length is element size * numbers of elements.When needing different elements size, count of predictions device
It is configured to handle the element of different number.
In the example machine including n PE, wherein each PE is able to carry out l channel of SWAR instructions, so in advance
Surveying counter group includes n × l counter.Therefore, the SWAR channels on one PE of the l counter controls each organized.Work as member
When part size is more than the channel of minimum channel width and each PE execution less than l, then a counter may be used as each letter
The prediction in road.
The IF operations of condition having less than n*l element can change all counters, therefore predictable with different numbers
The branch prediction of amount element.
The SWAR channels of the writable different different elements sizes and different number for cycling to calculate each PE.It props up wherein
It holds in an illustrative embodiments of SWAR, redefines LOOP primitive to regard l as parameters.
In this embodiment, the pseudocode of NEXT_STAGE primitive can retain as before.
It should be noted that the activity discussed above with reference to attached drawing can be applied to any integrated circuit for being related to signal processing（Especially
It is the integrated circuit of executable proprietary software program or algorithm）, some of which can be related to processing digitlization real time data.Certain
A little embodiments can relate to more DSP signal processings, floating-point processing, signal/control process, fixed function are handled, microcontroller is answered
With program etc..
In some contexts, feature discussed herein can be applied to medical system, scientific instrument, wireless and cable modem
Letter, radar, industrial procedure control, audio and video equipment, electric current sensing, instrument（There can be high accuracy）It is based on other
The system of digital processing.In addition, in the Digital Signal Processing for imaging of medical, patient monitoring, Medical Instruments and care and household
It could dictate that some embodiments discussed above in technology.This may include cardiacrespiration monitor, accelerometer, heart rate monitor, pace-making
Device etc..Other application can relate to security system（For example, stabilitrak, driver assistance system, brake system, appoint
The amusement of which kind of class and internal applications）Automatic technology.In addition, carrying out battery cell monitoring, control system, report control, dimension
During shield activity etc.,（For example, in mixing and electric car）The data conversion product of pinpoint accuracy can be used in powertrain system.
In other example scenario, the content of courses of the disclosure can be applied to include to help to improve productivity,
The industrial market of the program control system of energy efficiency and reliability.In consumer applies, signal processing electricity discussed above
The content of courses on road can be used for（For example, digital camera, video camera（Deng）'s）Image procossing, automatic focusing and image stabilization.
Other consumer's applications may include the Voice and Video processor of home theater system, DVD recorder and high-resolution TV.
Other consumer's application can relate to（For example, any kind of portable medical device）Advanced touch screen controller.
Therefore, these technologies can easily become smart mobile phone, tablet computer, security system, personal computer（PC）, game technology, void
Intend the part in real border, simulated training etc..
It can implement with reference to each illustrative components, blocks, module, core and the circuit that various aspects disclosed herein describe
In integrated circuit（IC）, in access terminal or access point or by integrated circuit（IC）, access terminal or access point perform.IC can be with
Including general processor, digital signal processor（DSP）, application-specific integrated circuit（ASIC）, field programmable gate array（FPGA）
Or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, electrical component, optical module, medical components
Or it is designed to perform any combinations of functions described in this article, and can perform and reside in IC, outside IC or secondly
The code of person or instruction.Logical block, module, core and circuit can include the day to communicate with the various components in network or device
Line and/or transceiver.General processor can be microprocessor, but in the alternative, processor can be any processing
Device, controller, microcontroller or state machine.Processor can also be implemented as the combination of computing device, such as DSP and microprocessor
Combination, multi-microprocessor, the one or more microprocessors for DSP core of arranging in pairs or groups or any other such configuration of device.Mould
The function of block or core can be in the way of such as imparting knowledge to students herein some other mode implement.In addition, work(described herein
Energy（For example, on one or more of attached drawing）It can in some aspects correspond in appended claims and to pass through similar specify
" instrument being used for ... " function.
The function of having described can be implemented in hardware, software, firmware, or any combination thereof.If implemented in software,
So described function can be used as one or more instructions or code to be stored in non-transitory computer-readable medium or pass through institute
State non-transitory computer-readable medium transmission.Computer-readable medium includes both computer storage media and communication medias,
Communication media includes any medium that computer program is promoted to be transmitted to another place at one.Storage medium can be can be by calculating
Any usable medium that machine accesses.Such as and unlimitedly, this computer-readable medium may include RAM, ROM, EEPROM, CD-
ROM or other optical disk storage apparatus, disk storage device or other magnetic storage devices can be used to carry or store in instruction
Or the form of data structure desired program code and can by computer access any other medium.Computer-readable medium
It can be in the form of non-transitory or temporary computer-readable medium.In addition, any connection can be properly called calculating
Machine readable medium.If for example, the software is to be transferred from website, server or using coaxial cable, optical cable, twisted-pair feeder, number
Word subscribers' line（DSL）Or other remote data sources of such as wireless technology of infrared ray, radio and microwave, then described same
Shaft cable, optical cable, twisted-pair feeder, digital subscriber line or such as wireless technology of infrared ray, radio and microwave are included in medium
Definition in.As used herein, CD and disk include CD (CD), laser disc, CD, digital versatile disc (DVD), floppy disk
Wherein CD usually magnetically replicate data and disk laser optics replicate data Blu-ray Disc.Said combination also should
It is included in the range of computer-readable medium.Generally speaking, machine readable media can be implemented on any appropriate computer
In program product.
Summarize the feature of multiple embodiments above so that the disclosure may be better understood in persons skilled in the art
Various aspects.Persons skilled in the art are it should be appreciated that they can be optionally using the disclosure as designing or repair
It uses instead in the identical purpose of implementation and/or realizes the other programs of same advantage of embodiment introduced herein or the base of structure
Plinth.Persons skilled in the art also should be appreciated that so equivalent construction does not run counter to spirit and scope of the present disclosure, and he
Can herein be variously modified, replace in the case where the construction of inequivalence does not run counter to spirit and scope of the present disclosure
Generation and change.
The particular embodiment of the disclosure can optionally include system on chip（SOC）, central processing unit（CPU）Envelope
Dress.The component of computer or other electronic systems is integrated into the integrated circuit in a chip by SOC expressions（IC）.It can be wrapped
Include number, simulation, mixed signal and radio-frequency enabled：Its whole may be provided on a chip substrate.Other embodiments
It can include multi-chip module（MCM）, plurality of chip is in an Electronic Packaging and is configured to pass through Electronic Packaging
Mutually close interaction.In each other embodiments, digital signal processing function can be implemented on application-specific integrated circuit
（ASIC）, field programmable gate array（FPGA）In the minds of one or more of other semiconductor chips silicon.
In the exemplary embodiment, at least some parts for the processing activity summarized herein can also be implemented on software
In.In certain embodiments, one or more of these features can be implemented on the element provided in published attached drawing
It can merge in external hardware or in any suitable manner to realize desirable function.Various components can include merging
To realize the software of operation as outlined herein（Or reciprocating software）.In other embodiments, these elements can
To include any appropriate algorithm, hardware, software, component, module, interface or the object for the operation for promoting it.
Furthermore, it is possible to it removes or merges in other ways and some in the relevant component of microprocessor that has described.One
As in meaning, the configuration described in attached drawing has more logicality in its expression, and physical structure can then include these elements
Various arrangements, combination and/or mixing.It has to be noticed that countless possible design configurations can be used to realize what is summarized herein
Operate target.Therefore, associated infrastructure has a large amount of alternative configurations, design alternative, device possibility, hardware configuration, soft
Part embodiment, device option etc..
Any processor module being properly configured can perform any kind of instruction associated with the data to realize herein
The operation of middle detailed description.Any processor disclosed herein can be by element or object（For example, data）From a state or situation
It is converted to another state or situation.In another example, some activities summarized herein can use fixed logic or can compile
Journey logic（For example, the software and/or computer instruction that are performed by processor）Implement, and the element assert herein may be certain
The programmable processor of type, programmable digital logic（For example, field programmable gate array（FPGA）, erasable programmable
Read-only memory（EPROM）, electric erasable programmable read-only memory（EEPROM））, including Digital Logic, software, code, electricity
Sub-instructions, flash memory, CD, CD-ROM, DVD ROM, magnetic or optical card, the other types of machine suitable for storing e-command
The ASIC of readable medium or its is any appropriately combined.In operation, processor can store information in any appropriate type
Non-transitory storage medium（For example, random access storage device（RAM）, read-only memory（ROM）, field programmable gate array
（FPGA）, erasable programmable read-only memory（EPROM）, electric erasable programmable ROM（EEPROM）Etc.）, software, hardware
Or it is stored in any other appropriate component, device or in the appropriate case and based on specific needs in object.In addition, it is just chased after
Track, transmission, the information of reception or storage in the processor can be based on specific needs and embodiment and be provided at any data
In storehouse, register, form, cache, queue, control inventory or storage organization, all it is subject to any appropriate time table
It quotes.Any memory item discussed herein should be interpreted as including in broader term " memory ".Similarly, herein
Described in any possible processing element, module and machine should be interpreted as including broader term " microprocessor " or " place
Manage device " in.
The all or part of computer program logics for implementing functions described in this article are in a variety of manners（Including（But
It is not limited to）Source code form, computer can perform form and various intermediate forms（For example, by assembler, compiler, link
The form that program or finder generate））Specific implementation.In instances, source code is included with various programming languages（Such as target
Code, assembler language or high-level language（OpenCL that various operating systems or the operating environment of such as arranging in pairs or groups use, formula translation journey
Formula language, C, C++, JAVA or HTML））The series of computation machine program instruction of implementation.Source code can define and using various
Data structure and communication information.Source code can be with（For example, via interpreter）Presentation computer can perform form or source code can
With（For example, via transfer interpreter, assembler or compiler）And it is converted to computer and can perform form.
In the discussion of embodiments hereinbefore, can arbitrarily replace, substitute or change in other ways capacitor, buffer,
Graphic elements, interconnection plate, clock, DDR, camera inductor, distributor, inductor, resistor, amplifier, switch, digital core
The heart, transistor and/or other components are to adapt to particular electrical circuit system needs.Moreover, it is noted that use complementary electronic device, hard
Part, non-transitory software etc. provide to implement the equally possible option of the content of courses of the disclosure.
In an exemplary embodiment, any amount of circuit of attached drawing may be implemented in the plug-in unit of related electronic device
On plate.The card may be various components for the internal electron system that can fix electronic device and also to other peripheral devices
The general-purpose circuit board of connector is provided.More specifically, the card, which can provide, can allow other components of system to carry out electric lead to
The electrical connection of letter.Any appropriate processor（Comprising digital signal processor, microprocessor, support chipset etc.）, storage
Device element etc. can be based on particular configuration needs, processing requirement, Computer Design etc. and be suitably connected to the card.
Such as other components of external memory, surplus induction device, the controller shown for audio/video and peripheral device can be with
The card is attached to as plug-in unit or be integrated into the card of its own via cable.In another exemplary embodiment party
In case, the circuit of attached drawing can be embodied as standalone module（For example, have the function of to be configured to carry out application-specific or correlation
The device of component and circuit system）Or it is implemented on as card module in the specialized hardware of electronic device.
It should be noted that in the multiple examples provided herein, can be retouched with regard to two, three, four, or more electrical component
State interaction.However, the purpose so done is merely to succinct and citing.It should be appreciated that the system can close in any appropriate manner
And.In attached drawing it is stated that any component, module and element various possible configurations can be combined into together with similar designs alternative,
It all clearly belongs in the broad scope of this part of specification.In some cases, the electricity member only referring to limited quantity is passed through
Part may more easily describe one or more of function of flow of given group.It should be appreciated that circuit and its religion of attached drawing
Learning content can arbitrarily extend and can accommodate a large amount of components and more complicated/fine configuration and construction.Therefore, the example having been provided
The scope of the circuit should not be limited when may be applied to a large amount of other frameworks or forbids the broad sense content of courses of the circuit.
Persons skilled in the art can confirm that it is a variety of it is other variation, substitute, change, change and modification, and it is desirable that this
It is open to include belonging to all these variations, replacement, variation, change and the modification in the range of appended claims.It is beautiful for auxiliary
Patent and trademark office of state（USPTO）And it aids in being attached to this Shen on any reader interpretation of any patent of the application issue in addition
Claim please, it is intended that it pays attention to：（a）Unless specifically used word " instrument being used for ... " in specific rights requirement
Or " the step of being used for ... ", any appended claims is otherwise not intended to call the 112nd chapters the 6th of 35U.S.C.（6）Section, because
The 112nd chapters the 6th of 35U.S.C.（6）The presence of section is on the submission date；With（b）It is not intended to through any sound in specification
It is bright by reflected not otherwise in appended claims it is any in a manner of limit the disclosure.
Claims (18)
1. a kind of processor, including：
Processing element；
Sequencer, the instruction for being configured to can perform condition provide the processing element；With
Count of predictions device register is configured to receive the useful value of more than two and provides its value as count of predictions device；
The predetermined value instruction of wherein described count of predictions device enables the execution of described instruction, and the count of predictions device is other
The execution of value instruction disabling described instruction simultaneously indicates the nesting level in Xun Huan or conditional branching.
2. processor according to claim 1, further includes：
Multiple processing elements, wherein each processing element includes count of predictions device register, and wherein described processor is configured
To be operated with simd mode.
3. processor according to claim 2, wherein：
Each processing element is divided into multiple l channels；
The processor is configured to be operated with simd mode in register；And
The processor further includes count of predictions device group, wherein the count of predictions device group includes at least n × l count of predictions
Device, wherein n are the quantity of processing element.
4. processor according to claim 1, wherein the processor is configured to single-instruction multiple-data in register
Pattern is operated.
5. processor according to claim 4, wherein the processor includes depending on the count of predictions for providing
The circuit system of the IF primitive relevant with the conditional branching of device, ELSE primitive and ENDIF primitive.
6. processor according to claim 5, wherein the IF primitive includes：
Condition of acceptance；
If the count of predictions device is not zero, the count of predictions device is incremented by；
If the count of predictions device be zero and the condition be false, the count of predictions device is arranged to 1.
7. processor according to claim 5, wherein the ELSE primitive includes：
If the count of predictions device is zero, the count of predictions device is arranged to 1；With
If the count of predictions device is 1, the count of predictions device is arranged to zero.
8. processor according to claim 5, wherein the ENDIF primitive includes：
If the count of predictions device is not zero, the count of predictions device successively decreases.
9. processor according to claim 1, wherein the processor includes being used to implement and the cycle is relevant
The circuit system of LOOP primitive and NEXT_STAGE primitive, wherein：
The LOOP primitive is configured to perform before the first instruction of stages of deployment Xun Huan；With
The NEXT_STAGE primitive is configured to perform between the stage of pipeline system step cycle.
10. processor according to claim 9, wherein the LOOP primitive is configured to single instruction multiple in register
It is operated according to pattern, and wherein described LOOP primitive is configured to receive single-instruction multiple-data channel conduct in multiple registers
Parameter.
11. a kind of method performed by computer, including：
Receive and be configured to receive the relevant instruction of count of predictions device of the useful value of more than two；
If the count of predictions device is the first value, described instruction is performed；With
If the count of predictions device is except the value of first value, ignore described instruction, wherein described except described
Nesting level in the value instruction Xun Huan of one value or conditional branching.
12. according to the method for claim 11, wherein first value is zero.
13. according to the method for claim 11, wherein first value be selected from by zero, 1, MAXINT ,-MAXINT, it is infinite,
The group of the nonumeric composition of negative infinite sum.
14. it according to the method for claim 11, further includes：
If the count of predictions device is not first value, additional act is taken.
15. it according to the method for claim 11, further includes：
Perform IF primitive relevant with the conditional branching, ELSE primitive and the ENDIF primitive depending on the count of predictions device.
16. the method according to claim 11, wherein：
The IF primitive includes：
Condition of acceptance；
If the count of predictions device is not zero, the count of predictions device is incremented by；
If the count of predictions device be zero and the condition be false, the count of predictions device is arranged to 1,
The ELSE primitive includes：
If the count of predictions device is zero, the count of predictions device is arranged to 1；With
If the count of predictions device is 1, the count of predictions device is arranged to zero；And
The ENDIF primitive includes：
If the count of predictions device is not zero, the count of predictions device successively decreases.
17. it according to the method for claim 11, further includes：
LOOP primitive relevant with the Xun Huan is performed before the first instruction and cycled in expansion in pipeline system step cycle
Stage between perform and held with the relevant NEXT_STAGE primitive of the cycle, the LOOP primitive and NEXT_STAGE primitive
Row each each depends on the count of predictions device.
18. a kind of computer, including the processor as described in claim 1-10 any one.
Applications Claiming Priority (6)
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| US201261717541P | 2012-10-23 | 2012-10-23 | |
| US61/717,541 | 2012-10-23 | ||
| US13/720,624 US9201828B2 (en) | 2012-10-23 | 2012-12-19 | Memory interconnect network architecture for vector processor |
| US13/720,624 | 2012-12-19 | ||
| US13/963,793 US9342306B2 (en) | 2012-10-23 | 2013-08-09 | Predicate counter |
| US13/963,793 | 2013-08-09 |
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| CN107659305A (en) * | 2017-10-19 | 2018-02-02 | 郑州云海信息技术有限公司 | A kind of clock count method, apparatus and medium based on CPLD |
| TWI783310B (en) * | 2020-11-26 | 2022-11-11 | 華邦電子股份有限公司 | Counting method and counting device |
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| US8078852B2 (en) * | 2009-05-28 | 2011-12-13 | International Business Machines Corporation | Predictors with adaptive prediction threshold |
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| US7127593B2 (en) | 2001-06-11 | 2006-10-24 | Broadcom Corporation | Conditional execution with multiple destination stores |
| US20080016320A1 (en) * | 2006-06-27 | 2008-01-17 | Amitabh Menon | Vector Predicates for Sub-Word Parallel Operations |
| US20090327674A1 (en) * | 2008-06-27 | 2009-12-31 | Qualcomm Incorporated | Loop Control System and Method |
| US8464031B2 (en) * | 2008-08-15 | 2013-06-11 | Apple Inc. | Running unary operation instructions for processing vectors |
| US9182959B2 (en) * | 2008-08-15 | 2015-11-10 | Apple Inc. | Predicate count and segment count instructions for processing vectors |
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