CN103731014B - A kind of TDC circuit for power tube drive part by part - Google Patents

Abstract

The present invention relates to integrated circuit technique, relate to a kind of time-to-digital conversion circuit for DC-DC converter DCM mode power pipe drive part by part specifically.A kind of TDC circuit for power tube drive part by part of the present invention, comprise time to digital converter unit and logic control element, described time to digital converter unit comprises Postponement module and latch module, and described logic control element comprises frequency division module, work schedule generation module, summation module and segmentation determination module; Wherein, Postponement module is connected with latch module, and summation module is connected with latch module, work schedule generation module and segmentation determination module respectively, and work schedule generation module is connected with frequency division module and segmentation determination module respectively.Beneficial effect of the present invention is, by the TDC circuit realiration current detecting of DC-DC converter under DCM of band logic control, and realizes the stable segmentation of power tube.The present invention is particularly useful for the power tube drive part by part under DC-DC converter DCM pattern.

Description

A kind of TDC circuit for segmental drive of power tube

technical field

The present invention relates to integrated circuit technology, in particular to a time-to-digital conversion (TimeDigitalConverter, TDC) circuit used for segmental driving of power tubes in DC-DC converter DCM mode.

Background technique

A DC-DC converter is a voltage converter that converts a non-fixed DC voltage into a fixed DC voltage, and is widely used in various electronic portable devices such as mobile phones and tablets. Common DC-DC converters are divided into three categories: Buck step-down converter, Boost step-up converter, and Buck-Boost step-down step-up converter. The conversion efficiency of the DC-DC converter affects some performances of electronic portable devices, such as battery life and so on. For this reason, the conversion efficiency is often used as one of the important indicators to measure the performance of the DC-DC converter.

Power tube segment drive technology is an important means to effectively improve the efficiency of DC-DC converters, especially the light-load efficiency. In this technology, how to detect the load current is a key issue. The commonly used SenseFET mirror tube current sampling method has good sampling accuracy under high load current, but the sampling accuracy will seriously drop under low load current, so it is not suitable for current detection under DCM. Therefore, how to conveniently and effectively detect the load current and complete the stable segmentation of the power tube under DCM has become a very meaningful problem.

Contents of the invention

What the present invention aims to solve is to propose a TDC circuit for power tube segmental drive aiming at the problems existing in the above-mentioned traditional power tube segmental drive technology.

The technical solution adopted by the present invention to solve the above-mentioned technical problems is: as shown in Figure 1, a TDC circuit for segmental driving of power tubes includes a time-to-digital conversion unit and a logic control unit, and the time-to-digital conversion unit includes a delay module and a latch module, the logic control unit includes a frequency division module, a working sequence generation module, a summation module and a segment judgment module; wherein, the delay module is connected to the latch module, and the summation module is connected to the latch module and the working sequence respectively. The timing generation module is connected to the segment determination module, and the working sequence generation module is respectively connected to the frequency division module and the segment determination module;

The delay module and the latch module are connected to the power tube control signal, and a plurality of detection points are arranged in the delay module as the output signal input of the delay module to the latch module. When the power tube control signal changes from high level to low level, through Reversely generates a rising edge and transmits backward. The detection point transmitted by the rising edge will change from low level to high level, and the node that has not been transmitted remains low. When the external control signal changes from low level to high level , the latch module latches the multi-bit signal input by the delay module under the control of the control signal, and generates an n-bit quantization code to output to the summation module, wherein the n-bit quantization code is the conduction time of the power tube control signal;

The summation module generates a corresponding m-bit control signal according to the n-bit quantization code input by the latch module and outputs it to the segmentation judgment module, and the segmentation judgment module generates an n-bit segmentation control code according to the m-bit control signal;

The working sequence generation module is used to provide an enabling control signal for the control summation module and the segmentation judgment module;

The frequency division module is used to divide the frequency of the external clock signal and provide it to the working sequence generation module.

In the general technical scheme of the present invention, the function of the time-to-digital conversion unit is to quantize the conduction time of the power tube once in each clock cycle to generate n-bit quantized codes, and the function of the serial control unit is to quantify the time-to-digital conversion unit. The code carries out the summation of several cycles, and determines which interval the final sum value is in, and then generates the final segment control code according to the relationship between the sum value interval and the number of power tube open segments. Here, the sum of several periodic quantization codes is used as the segmentation basis, which avoids the fluctuation of the segmentation control code and ensures the stability of the segmentation.

Specifically, the delay module is composed of a plurality of delay units cascaded, the latch module is composed of a plurality of D flip-flops triggered by falling edges, and the number of the D flip-flops is equal to that of the detection nodes in the delay module and sequentially corresponding connection.

The beneficial effect of the invention is that the current detection of the DC-DC converter under DCM is realized by using the TDC circuit with logic control, and the stable segmentation of the power tube is realized.

Description of drawings

Fig. 1 is the structural representation of the TDC circuit that is used for power tube section driving of the present invention;

Fig. 2 is a schematic structural diagram of a time-to-digital conversion unit;

Fig. 3 is a schematic diagram of the working cycle of the logic control unit;

Fig. 4 is a schematic structural diagram of a segment-driven Buck converter applying the present invention.

detailed description

Below in conjunction with accompanying drawing and embodiment, describe technical solution of the present invention in detail:

As shown in FIG. 1 , the TDC circuit with logic control proposed by the present invention generally includes two parts: a time-to-digital conversion unit and a logic control unit. The time-to-digital conversion unit includes: a delay module and a latch module; the logic control unit includes: a frequency division module, a working sequence generation module, a summation module and a segmentation judgment module.

The function of the time-to-digital conversion unit is to quantize the conduction time of the power transistor once in each clock cycle, and generate n-bit quantized codes. The role of the logic control unit is to sum the quantized codes generated by the time-to-digital conversion unit for several cycles, and determine which interval the final sum value is in. Then, according to the relationship between the sum value interval and the number of power tubes turned on, the final segmented control code is generated. Here, the sum of several periodic quantization codes is used as the segmentation basis, which avoids the fluctuation of the segmentation control code and ensures the stability of the segmentation.

The connection relationship between each module is described in detail as follows:

en is the overall enable signal, which is connected to the latch module and an input terminal of the NAND gate.

drivep is the driving signal of the power P tube (in the following description, it is assumed that the P tube is a power switch tube), and it is connected to the other input terminal of the above-mentioned NAND gate. The output of the NAND gate is respectively connected to the delay module and the latch module. The delay module sets n detection points in the internal delay chain as outputs: d1,...,dn, d1,...,dn are connected to the latch module. On the rising edge of drivep, that is, when the power P tube is turned on to off, the latch module latches the states of d1,...,dn, and generates n-bit quantization codes: a1,...,an. a1, . . . , an are the quantized codes of the turn-on time of the power transistor generated in each clock cycle, which are connected to the summation module in the logic processing unit.

clk is the converter switching frequency clock signal, respectively connected to the frequency division module, the summation module, and the segment determination module. The output of the frequency division module is connected to the working sequence generating module, and the working sequence generating module generates 3 signals: en1, rst1, en2. Among them, en1 and rst1 are connected to the summation module, which are the enable signal and reset signal respectively. en2 is connected to the segmentation judgment module, and it enables the signal. The summation module generates m bits (the value of m is determined according to the segment control code number n) output: q1,..., qm, q1,..., qm are connected to the segment determination module. The segment determination module generates n-digit codes: seg1,...,segn, seg1,...,segn as the final segment control code.

As shown in Figure 2, it is the specific structure of the time-to-digital conversion unit:

Among them, the delay module is formed by cascading a series of basic delay units. There are n detection nodes in the delay module. Their selection is based on the relationship between the load current and the conduction time of the power tube. The corresponding conduction time interval point is determined by the segmented current interval point, and then the corresponding delay time node is found on the delay chain, and it is set as the detection node. point. The delay module has such characteristics: assuming that the input of the delay module is at low level, each detection node is initially at low level. When the input jumps from low to high, a rising edge will be generated and transmitted backward in the delay chain. The node that the rising edge reaches will become high level, and the node that has not reached it will remain low level. If the state of each detection node is detected at a certain moment, each node presents a different state of high and low. If the detection time is different, different detection code combinations will be obtained.

The latch module consists of a series of D flip-flops triggered by falling edges. Starting from the power P tube drive signal changing from high to low, there will be a rising edge that will start to be transmitted backward in the delay chain, and the nodes that the rising edge reaches will change from low to high, and the nodes that have not been transmitted will remain low. When the drive signal of the power P tube changes from low to high, the falling edge generated by inversion will trigger the latch module, and the state of each detection node of the delay module will be saved at this moment. At this time, the time for the aforementioned rising edge to pass through the delay chain is exactly the low-level time of the driving signal of the power P tube, that is, the conduction time of the power P tube. So the conduction time of the power P tube is quantized into a set of digital codes.

It can be seen from the above that the time-to-digital conversion unit has already completed the quantization of the power tube conduction time to the digital code. However, this quantization code cannot be directly used as the final segment control code. The reason is that the quantization code above is generated once in each clock cycle. If the conduction time of the power P tube fluctuates in a certain clock cycle (or due to external influences, or because the load current is at a critical current), the quantization code will also fluctuate. , leading to segmental instability.

The role of the logic control unit is to avoid the above problems and ensure stable segmentation. In order to stabilize the segment, it updates the final segment control code once within N clock cycles (called the work cycle) through the logic processing of the quantization code. Among them, the working timing generation module generates 3 key timing signals, which divide the working cycle into 4 main stages: summation, judgment, reset, and hold.

In conjunction with FIG. 3 , the working states of the logic control unit at each stage will be described.

Summation phase: en1 is at high level and lasts for N ₁ (N ₁ <N) clock cycles. During this period, the summation module performs N ₁ sampling summation on the quantized value of the time-to-digital conversion unit. After en1 becomes low, the summation module stops summing and keeps the final summation value unchanged;

Judgment stage: en2 is at high level and lasts for N ₂ (N ₂ <N) clock cycles. During this period, the segment judgment module is enabled, and it makes a judgment on the interval of the summation value held by the summation module , generate the corresponding segment control code, and update the segment control code;

Reset phase: rst1 is at a high level and lasts for N ₃ (N ₃ <N) clock cycles. During this period, the summation module is reset by the clock signal (that is, the output of the summation module is set to 0) for the next working cycle prepare;

Hold phase: During the remaining clock cycles, the segment code remains unchanged. Until the arrival of the next working cycle, a new judgment is made.

Example:

This example mainly includes a segment-driven power tube, an LC filter circuit, a feedback control unit and the TDC circuit of the present invention. The feedback control unit is connected to the output of the Buck converter to generate a drive signal for the power tube and send it to the TDC module and the buffer circuit of the power tube. The TDC quantifies the conduction time of the power P tube, infers the current load current, and generates a segmented control code. The segment control code is connected to the buffer circuit to drive the power tube in segments.

In this example, the specific values of some parameters in the aforementioned technical solution are as follows:

n=5, m=9, N=32, N ₁ =10, N ₂ =2, N ₃ =2

That is, there are 5-digit segment control codes (the number of power pipe segments controlled under DCM is 5); the output of the summation module is represented by 9-digit binary numbers (the 10-period summation of 5-digit quantization codes can be represented by at least 9 binary digits); a working The period includes 32 clock cycles; the high level of the timing signal en1 lasts for 10 clock cycles, the high level of the timing signal rst1 lasts for 2 clock cycles, and the high level of the timing signal en2 lasts for 2 clock cycles.

In the summation stage, the summation module in the logic control unit performs 10 sampling sums on the quantization code of the on-time, and then the segment determination module determines which interval the sum value is in, and updates the segment code. Next, the summation block is reset (the output of the summation block is cleared). In the remaining time of the working cycle, the segmentation code remains unchanged until the arrival of the next working cycle, and then a new judgment is made.

In this example, the lookup table based on which the logic control unit performs segmentation judgment is shown in Table 1:

Table 1 The logical control unit performs a segmented judgment lookup table

Claims (2)

1. the TDC circuit for power tube drive part by part, described TDC circuit is time-to-digital conversion circuit, comprise time to digital converter unit and logic control element, described time to digital converter unit comprises Postponement module and latch module, and described logic control element comprises frequency division module, work schedule generation module, summation module and segmentation determination module; Wherein, Postponement module is connected with latch module, and summation module is connected with latch module, work schedule generation module and segmentation determination module respectively, and work schedule generation module is connected with frequency division module and segmentation determination module respectively;

Described Postponement module is connected power tube control signal with latch module, the output signal input and latch module of multiple test point as Postponement module is provided with in Postponement module, when power tube control signal is by high level step-down level, transmit backward through oppositely producing rising edge, the test point that rising edge passes to can uprise level by low level, the test point do not passed to still keeps low level, when external control signal uprises level by low level, the multibit signal that Postponement module inputs latches by latch module under control of the control signal, produce n position quantization code and output to summation module, wherein n position quantization code is the ON time of power tube control signal,

The n position quantization code that described summation module inputs according to latch module produces corresponding m position control signal and outputs to segmentation determination module, and segmentation determination module produces n position Discrete control code according to m position control signal;

Described work schedule generation module is used for for control summation module and segmentation determination module provide enable control signal;

Described frequency division module is used for carrying out frequency division to external timing signal and being supplied to work schedule generation module.

2. a kind of TDC circuit for power tube drive part by part according to claim 1, it is characterized in that, described Postponement module is made up of multiple delay cell cascade, the d type flip flop that described latch module is triggered by multiple trailing edge is formed, and described d type flip flop is equal with the quantity of test point in Postponement module and be corresponding in turn to connection.