CN103677040A - Drive circuit of reference voltage - Google Patents

Abstract

The invention discloses a driving circuit of a reference voltage, which can realize better PSRR, improve the establishment speed of the reference voltage, and reduce the power consumption of the circuit. The driving circuit of the reference voltage provided by the embodiment of the present invention includes a closed-loop negative feedback loop and an open-loop branch, and the open-loop branch includes an NMOS transistor (M31) and an NMOS transistor (M32); the drain connection of the NMOS transistor (M31) To the power supply VDD, the gate of the NMOS transistor (M31) is connected to the first bias voltage provided by the closed-loop negative feedback loop, and the source of the NMOS transistor (M31) outputs the reference voltage Vrp; the drain of the NMOS transistor (M32) is connected to the The source of the NMOS transistor (M31) is connected, the gate of the NMOS transistor (M32) is connected to the second bias voltage provided by the closed-loop negative feedback loop, the source of the NMOS transistor (M32) is grounded through an isolated electrical device, and the NMOS transistor (M32) The source of the tube (M32) outputs the reference voltage Vrn.

Description

A reference voltage driving circuit

technical field

The invention relates to the technical field of circuit development, in particular to a reference voltage driving circuit.

Background technique

ADC (Analog-to-Digital Converter, analog-to-digital conversion) technology converts analog signals into digital signals. Essentially, the function of the ADC is to output a digital code based on the comparison of the input analog signal and the input reference voltage. The error and noise of the reference voltage will be converted into the error of the output code, and the performance of the reference voltage directly affects the performance and accuracy of the ADC. For a 12-bit precision ADC device, the power supply voltage is 1.8V. If the reference voltage range is equal to the power supply voltage, the error and noise of the input reference voltage must be controlled within ±0.4mV.

In practical scenarios, there are many factors that affect the performance of a voltage reference. For example, in a stage circuit of a pipelined ADC, a switched-capacitor circuit draws current from a reference voltage drive circuit to charge and discharge the capacitor. On the one hand, the switched capacitor circuit needs a stable reference voltage to ensure its output accuracy. On the other hand, the high-speed switching of the switch will introduce a large transient load to the reference voltage circuit, causing the reference voltage to jitter. In high-speed ADCs, the jitter of the reference voltage must be stable within a short period of time. Therefore, there is a need for an implementation that provides a stable reference voltage for a high-speed ADC.

Existing implementation schemes of reference voltage driving circuits are mainly divided into two categories: high-impedance implementation technology and low-impedance implementation technology. High-impedance implementation technologies usually use larger on-chip or off-chip capacitors, and use large capacitors to absorb changes in charge to maintain voltage stability. Low-impedance implementation techniques rely on high-speed voltage buffers (buffers) to provide large transient currents. The low-impedance implementation technology is a more commonly used reference voltage drive implementation scheme for high-speed ADCs. Referring to Figure 1, it shows the reference voltage drive circuit for ADC under the existing low impedance implementation technology. This circuit is realized by driving an open-loop branch 2 by a closed-loop negative feedback loop 1, and the reference voltages Vrp and Vrn are driven by the open loop Branch 2 is output, and the open-loop drive branch 2 is driven by the closed-loop negative feedback loop 1. The input voltages Vrpin, Vrnin and Vcmoin are generated by the bandgap reference and reference voltage generation circuit 10, provide accurate voltage values through the unity gain negative feedback loop 4 and the loop 5, and then output through the open loop branch 2 and provide a larger drive current. The reference voltage Vrp is generated by PMOS (P-Channel Metal Oxide Semiconductor, P-channel Metal Oxide Semiconductor) transistors M11 and M12, and the reference voltage Vrn is generated by NMOS (N-Channel Mental Oxide Semiconductor, N-channel Metal Oxide Semiconductor) transistors M13 and M14 produced.

The existing reference voltage driving scheme has at least the following defects:

The existing high-impedance implementation technology needs to set a large-capacity off-chip capacitor. Therefore, the chip needs to add additional chip pads and package pins, and the parasitic inductance of the bonding wire and the off-chip capacitor will limit the speed of establishing the reference voltage.

In the existing low-impedance implementation technology, the driving branch is generally implemented by PMOS transistors and NMOS transistors. Since the carrier mobility of the NMOS tube is greater than that of the PMOS tube, the design size of the PMOS tubes M11 and M12 should be larger than the size of the NMOS tube (for example: in the SMIC13 process, the mobility of electrons is 3 times that of the hole mobility times, so the design size of the PMOS tubes M11 and M12 is three times the size of the NMOS tubes M13 and M14). A large-sized PMOS tube will bring a large parasitic capacitance. On the one hand, the decoupling capacitor 6 of the PMOS transistor M11 and the parasitic capacitance of M11 form a coupling path from the power line to the output terminal Vrp, which reduces the PSRR (Power Supply Rejection Ratio, power supply rejection ratio) and affects the circuit performance; on the other hand, The parasitic capacitances of the two PMOS transistors M11 and M12 connected to Vrp become the capacitive load of the output Vrp, resulting in a slow establishment of the reference voltage Vrp, and to ensure a certain reference voltage establishment speed will inevitably increase the power consumption of the circuit.

Contents of the invention

The present invention provides a reference voltage driving circuit to solve the problem that the existing solution adopts the off-chip capacitance method, which needs to add extra chip pads and packaging pins, introduces parasitic inductance to reduce the establishment speed, and when using large-size PMOS tubes The PSRR of the circuit is low, and the problem of excessive power consumption of the circuit will be caused when the speed of establishing the reference voltage is guaranteed.

In order to achieve the above object, the embodiment of the present invention adopts the following technical solutions:

A reference voltage driving circuit provided by an embodiment of the present invention, the driving circuit includes a closed-loop negative feedback loop and an open-loop branch, and the open-loop branch includes an NMOS transistor M31 and an NMOS transistor M32;

The drain of the NMOS transistor M31 is connected to the power supply VDD, the gate of the NMOS transistor M31 is connected to the first bias voltage provided by the closed-loop negative feedback loop, and the source of the NMOS transistor M31 outputs the reference voltage Vrp;

The drain of the NMOS transistor M32 is connected to the source of the NMOS transistor M31, the gate of the NMOS transistor M32 is connected to the second bias voltage provided by the closed-loop negative feedback loop, and the source of the NMOS transistor M32 is grounded through an isolation device. The source of the NMOS transistor M32 outputs the reference voltage Vrn.

From the above, the embodiment of the present invention is realized by the source follower formed by the NMOS transistor in the open-loop branch, which avoids the need for a large-sized PMOS transistor when the NMOS transistor and the PMOS transistor are used in the open-loop branch. The problem of slow reference voltage establishment speed and large circuit power consumption can quickly establish reference voltages Vrp and Vrn to reduce circuit power consumption; moreover, in this solution, the NMOS tube is connected with a source follower, and the gate is decoupled The capacitor is connected to the ground, which reduces the coupling effect from the power line to the output end, and can obtain better PSRR, thereby improving circuit performance.

Moreover, the reference voltage driving circuit of this solution has a simple circuit structure, does not require large-capacity capacitors outside the chip, does not need to add additional chip pads and packaging pins, reduces circuit power consumption, and optimizes circuit performance.

Description of drawings

FIG. 1 is a circuit diagram of a reference voltage driving scheme under the existing low impedance technology;

FIG. 2 is a circuit diagram of a reference voltage driving circuit provided by an embodiment of the present invention;

FIG. 3 is a circuit diagram of another reference voltage driving circuit according to an embodiment of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the implementation manner of the present invention will be further described in detail below in conjunction with the accompanying drawings.

The driving circuit of the reference voltage in this embodiment is realized by driving an open-loop branch with a closed-loop negative feedback loop. The closed-loop negative feedback loop provides an accurate initial reference voltage value, and the open-loop branch provides an output drive current to generate a reference voltage. Referring to FIG. 2 , it is a circuit diagram of a driving circuit of a reference voltage provided by an embodiment of the present invention, the driving circuit includes a closed-loop negative feedback loop and an open-loop branch, and the open-loop branch includes an NMOS transistor M31 and an NMOS transistor M32;

The drain of the NMOS transistor M31 is connected to the power supply VDD, the gate of the NMOS transistor M31 is connected to the first bias voltage provided by the closed-loop negative feedback loop, the source of the NMOS transistor M31 outputs the reference voltage Vrp, and the drain of the NMOS transistor M31 is connected to The connection mode to the power supply VDD has an isolation function, and the gate of the NMOS transistor M31 is decoupled to the ground through the decoupling capacitor 25, and this structure improves the PSRR of the circuit.

From the above, in this embodiment, the connection mode of the drain, source and gate of the NMOS transistor M31 and the decoupling structure of the gate to the ground through the decoupling capacitor 25 have a good isolation effect, reducing the power supply line to the output. The coupling effect of the terminal improves the PSRR of the circuit.

The drain of the NMOS transistor M32 is connected to the source of the NMOS transistor M31, the gate of the NMOS transistor M32 is connected to the second bias voltage provided by the closed-loop negative feedback loop, and the source of the NMOS transistor M32 is grounded through an isolation device. The source of the NMOS transistor M32 outputs the reference voltage Vrn.

The electrical isolation device mentioned above can be realized by an NMOS transistor or a resistor, and it is not recommended to use a PMOS transistor for the electrical isolation device.

From the above, the embodiment of the present invention is realized by the source follower formed by the NMOS transistor in the open-loop branch, which avoids the need for a large-sized PMOS transistor when the NMOS transistor and the PMOS transistor are used in the open-loop branch. The problem of slow reference voltage establishment speed and large circuit power consumption can quickly establish reference voltages Vrp and Vrn to reduce circuit power consumption; moreover, this scheme reduces the coupling effect from the power line to the output terminal, and can get better PSRR, thereby improving circuit performance.

Moreover, the driving circuit of the reference voltage in this solution has a simple circuit structure and does not require an off-chip large-capacity capacitor, which not only reduces circuit power consumption, optimizes circuit performance, but also improves the generality of the circuit, which is convenient for practical use.

Referring to FIG. 3 , a circuit diagram of another reference voltage driving circuit is provided for an embodiment of the present invention. In the scenario of FIG. 3 , the electrical isolation device is realized by the NMOS transistor M33 , that is, only the NMOS transistor is included in the open-loop branch. The gate of the NMOS transistor M33 is connected to the third bias voltage provided by the closed-loop negative feedback loop, and the source of the NMOS transistor M33 is grounded.

The closed-loop negative feedback loop includes a branch 21, which includes an NMOS transistor M34, an NMOS transistor M35, and an NMOS transistor M36, and the branch 21 is set as the ratio of the current on the branch 21 to the current on the open-loop branch The relation is 1:K, where,

The drain of the NMOS transistor M34 is connected to the power supply VDD, the gate of the NMOS transistor M34 is connected to the first bias voltage and connected to the gate of the NMOS transistor M31, and the source of the NMOS transistor M34 is connected to the drain of the NMOS transistor M35 ;

The gate of the NMOS transistor M35 is connected to the second bias voltage and connected to the gate of the NMOS transistor M32, and the source of the NMOS transistor M35 is connected to the drain of the NMOS transistor M36;

The gate of the NMOS transistor M36 is connected to the third bias voltage and connected to the gate of the NMOS transistor M33, and the source of the NMOS transistor M36 is grounded.

A differential operational amplifier 40 and a differential operational amplifier 41 are included in the closed-loop negative feedback loop, and the drive circuit also includes a bias current source, specifically as follows:

The differential operational amplifier positive input terminal of the differential operational amplifier 40 is connected to the initial reference voltage Vrpin (Vrpin is generated by the bandgap reference and reference voltage generation circuit 30), and the differential operational amplifier negative input terminal of the differential operational amplifier 40 is connected to the NMOS transistor M34 The source of the differential operational amplifier 40 is connected to one end of the charge pump 24, and the other end of the charge pump 24 is connected to the gate of the NMOS transistor M34 to provide the first bias voltage;

The differential operational amplifier positive input terminal of the differential operational amplifier 41 is connected to the initial reference voltage Vrnin (Vrnin is generated by the bandgap reference and reference voltage generation circuit 30), and the differential operational amplifier negative input terminal of the differential operational amplifier 41 is connected to the NMOS transistor M35 The source of the differential operational amplifier 41 is connected to the gate of the NMOS transistor M35, and the second bias voltage is provided to the gates of the NMOS transistor M35 and the NMOS transistor M32;

The output end of the bias current source (Ibias) is connected to the drain of the NMOS transistor M37, the source of the NMOS transistor M37 is connected to the drain of the NMOS transistor M38, the source of the NMOS transistor M38 is grounded, and the output end of the bias current source The gates of the NMOS transistor M38 and the NMOS transistor M38 are both connected to the gates of the NMOS transistor M36, and the third bias voltage is provided to the gates of the NMOS transistor M36 and the NMOS transistor M33.

As shown in FIG. 3 , the ADC reference voltages Vrp and Vrn are output by an open-loop branch 20 driven by a closed-loop negative feedback loop 19 . The closed-loop negative feedback loop 19 copies the branch 21 as the second stage of the closed-loop negative feedback loop according to the open-loop branch 20 according to the width-to-length ratio relationship of 1:K, and the duplication here refers to the open-loop branch 20 and the branch The type and quantity of devices in 21 are the same, and the structure is very similar, and the proportional relationship between the current of branch 21 and the current of open-loop branch 20 is 1:K, for example, the devices in open-loop branch 20 and branch 21 are both When it is an NMOS tube, the proportional relationship between the width-to-length ratio of the NMOS tube in the branch 21 and the width-to-length ratio of the NMOS tube in the open-loop branch 20 can be set to 1:K, thereby ensuring that the branch 21 and the open-loop branch The corresponding node voltages of the circuit 20 are equal and the magnitude relationship of the current is 1:K.

The input voltages Vrpin and Vrnin are generated by the bandgap reference and reference voltage generating circuit 30. According to the negative feedback characteristics of the loop 22 and the loop 23, the source voltage values of the NMOS transistor M34 and the NMOS transistor M35 are equal to Vrpin and Vrnin respectively.

In order to provide a reasonable DC operating point for the open-loop branches 20 and 21 , a charge pump 24 is introduced in the loop 22 . The charge pump 24 includes a capacitor C1 and a capacitor C2. One end of the capacitor C1 is connected or disconnected from the DC voltage Vbn2 through the switch K11 and connected or disconnected from one end of the capacitor C2 through the switch K21. The other end of the capacitor C1 is connected to or disconnected from the DC voltage Vbn2 through the switch K12. The power supply VDD is turned on or off, and the other end of the capacitor C2 is connected or disconnected through the switch K22; one end of the capacitor C2 is also connected to the output end of the differential operational amplifier 40, and the other end of the capacitor C2 is also connected to the NMOS tube M34 the grid.

clk1 and clk2 are two-phase working clocks of the charge pump, and Vbn2 is a DC voltage. clk1 and clk2 are different, the closing and opening of switches K11 and K12 are controlled according to clk1, and the closing and opening of switches K21 and K22 are controlled according to clk2. The charge pump makes the voltage Vop (the first bias voltage connected to the gate of the NMOS transistor M34) increase by C1(VDD-Vbn2)/(C1+C2) than the voltage Vop1, and the first bias voltage can be adjusted by adjusting Vbn2 , so as to ensure that the first bias voltage on the gate of the NMOS transistor M34 is large enough to ensure the normal operation of the NMOS transistors M31 and M34.

The gate voltage of M32 and M35 is provided by the voltage Von of the output terminal of the differential operational amplifier 41, M33, M36 and M38, and M32, M35 and M37 form a current mirror, Ibias is the input bias current, and the current mirror provides the gate voltage for M33 and M36 (ie the third bias voltage).

Optionally, a decoupling capacitor 25 , a decoupling capacitor 26 and a decoupling capacitor 27 are also provided for the NMOS transistor to stabilize the gate voltage respectively. Wherein, the gate of the NMOS transistor M34 is also connected to one end of the capacitor 25, and the other end of the capacitor 25 is grounded, so that the gate of the NMOS transistor M31 can be decoupled to the ground through the decoupling capacitor 25, reducing the coupling of the power line to the output terminal The function improves the PSRR of the circuit; the gate of the NMOS transistor M35 is also connected to one end of the capacitor 26, and the other end of the capacitor 26 is grounded; the gate of the NMOS transistor M36 is also connected to one end of the capacitor 27, and the other end of the capacitor 27 is grounded.

Optionally, the differential operational amplifier negative input terminal of the differential operational amplifier 40 is connected to the source of the NMOS transistor M34 through the resistor R1; the differential operational amplifier negative input terminal of the differential operational amplifier 41 is connected to the source of the NMOS transistor M35 through the resistor R2 pole. The function of stabilizing the voltage and current is played by the resistor R1 and the resistor R2.

From the above, the open-loop branch 20 used as the output terminal in this embodiment is only implemented by an NMOS source follower, the circuit is simple to implement, and can provide a large driving current for the reference voltages Vrp and Vrn to achieve a faster reference voltage builds up. The NMOS source follower in the open-loop branch 20 has a good isolation effect, avoiding the influence of voltage jitter on the open-loop branch, ensuring the stability of the open-loop branch; and reducing the power supply line to the output The coupling effect of the terminal achieves a high PSRR. Since the open-loop branch is implemented with NMOS transistors, in order to meet the requirements of the same output voltage establishment speed, compared with the PMOS transistor drive branch, this solution only needs a smaller design size, thereby reducing current consumption and saving power consumption .

Moreover, in this embodiment, the NMOS transistor M33 is used as the isolation electrical device, and the current mirror is used to provide the gate voltage for the NMOS transistor M33, which can improve the accuracy of the output reference voltages Vrp and Vrn.

From the above, the embodiment of the present invention is realized by the source follower formed by the NMOS transistor in the open-loop branch, which avoids the need for a large-sized PMOS transistor when the NMOS transistor and the PMOS transistor are used in the open-loop branch. The problem of slow reference voltage establishment speed and large circuit power consumption can quickly establish reference voltages Vrp and Vrn to reduce circuit power consumption; moreover, in this solution, the NMOS tube is connected with a source follower, and the gate is decoupled The capacitor is connected to the ground, which reduces the coupling effect from the power line to the output end, and can obtain better PSRR, thereby improving circuit performance.

Moreover, the reference voltage driving circuit of this solution has a simple circuit structure, does not require large-capacity capacitors outside the chip, does not need to add additional chip pads and packaging pins, reduces circuit power consumption, and optimizes circuit performance.

Another reference voltage drive circuit provided by the embodiment of the present invention is different from the drive circuit shown in Figure 3 mainly in that the isolation electrical device is realized by a resistor R33, and the position of the NMOS transistor M36 in Figure 3 is also realized by a resistor , while the bias current source Ibias, NMOS transistors M37 and M38 in FIG. 3 can be removed, and other components in FIG. 3 remain unchanged.

Specifically, one end of the resistor R33 is connected to the source of the NMOS transistor M32, and the other end of the resistor R33 is grounded.

The closed-loop negative feedback loop includes a branch 21, which includes an NMOS transistor M34, an NMOS transistor M35 and a resistor R36, and the branch 21 is set to The proportional relationship between the current on the branch 21 and the current on the open-loop branch is 1:K, where,

The drain of the NMOS transistor M34 is connected to the power supply VDD, the gate of the NMOS transistor M34 is connected to the first bias voltage and connected to the gate of the NMOS transistor M31, and the source of the NMOS transistor M34 is connected to the drain of the NMOS transistor M35 ;

The gate of the NMOS transistor M35 is connected to the second bias voltage and connected to the gate of the NMOS transistor M32, and the source of the NMOS transistor M35 is connected to one end of the resistor R36;

The other end of the resistor R36 is grounded.

The differential operational amplifier positive input terminal of the differential operational amplifier 40 is connected to the initial reference voltage Vrpin (Vrpin is generated by the bandgap reference and reference voltage generation circuit 30), and the differential operational amplifier negative input terminal of the differential operational amplifier 40 is connected to the NMOS transistor M34 The source of the differential operational amplifier 40 is connected to one end of the charge pump 24, and the other end of the charge pump 24 is connected to the gate of the NMOS transistor M34 to provide the first bias voltage;

The differential operational amplifier positive input terminal of the differential operational amplifier 41 is connected to the initial reference voltage Vrnin (Vrnin is generated by the bandgap reference and reference voltage generation circuit 30), and the differential operational amplifier negative input terminal of the differential operational amplifier 41 is connected to the NMOS transistor M35 The source of the differential operational amplifier 41 is connected to the gate of the NMOS transistor M35 to provide the second bias voltage to the gates of the NMOS transistor M35 and the NMOS transistor M32.

From the above, the embodiment of the present invention is realized by the source follower formed by the NMOS transistor in the open-loop branch, which avoids the need for a large-sized PMOS transistor when the NMOS transistor and the PMOS transistor are used in the open-loop branch. The problem of slow reference voltage establishment speed and large circuit power consumption can quickly establish reference voltages Vrp and Vrn to reduce circuit power consumption; moreover, this scheme reduces the coupling effect from the power line to the output terminal, and can get better PSRR, thereby improving circuit performance.

Moreover, the driving circuit of the reference voltage in this solution has a simple circuit structure and does not require an off-chip large-capacity capacitor, which not only reduces circuit power consumption, optimizes circuit performance, but also improves the generality of the circuit, which is convenient for practical use.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present invention are included in the protection scope of the present invention.

Claims (10)

1. A reference voltage drive circuit, characterized in that the drive circuit includes a closed-loop negative feedback loop and an open-loop branch, and the open-loop branch includes an N-channel metal oxide semiconductor NMOS transistor (M31) And NMOS tube (M32); The drain of the NMOS transistor (M31) is connected to the power supply VDD, the gate of the NMOS transistor (M31) is connected to the first bias voltage provided by the closed-loop negative feedback loop, and the source of the NMOS transistor (M31) outputs the reference voltage Vrp; The drain of the NMOS transistor (M32) is connected to the source of the NMOS transistor (M31), the gate of the NMOS transistor (M32) is connected to the second bias voltage provided by the closed-loop negative feedback loop, and the NMOS transistor (M32) The source is grounded through the isolation electrical device, and the source of the NMOS transistor (M32) outputs the reference voltage Vrn. 2. The driving circuit according to claim 1, characterized in that, The isolated electrical device is an NMOS transistor (M33), the drain of the NMOS transistor (M33) is connected to the source of the NMOS transistor (M32), and the gate of the NMOS transistor (M33) is connected to a closed-loop negative feedback loop For the provided third bias voltage, the source of the NMOS transistor (M33) is grounded. 3. The driving circuit according to claim 2, characterized in that the closed-loop negative feedback loop includes a branch (21), and the branch (21) includes an NMOS transistor (M34), an NMOS transistor (M35) and an NMOS transistor (M35) Tube (M36), branch (21) is set such that the proportional relationship between the current on branch (21) and the current on the open-loop branch is 1:K, where, The drain of the NMOS transistor (M34) is connected to the power supply VDD, the gate of the NMOS transistor (M34) is connected to the first bias voltage and connected to the gate of the NMOS transistor (M31), and the source of the NMOS transistor (M34) is connected to the The drain of the NMOS transistor (M35) is connected; The gate of the NMOS transistor (M35) is connected to the second bias voltage and connected to the gate of the NMOS transistor (M32), and the source of the NMOS transistor (M35) is connected to the drain of the NMOS transistor (M36); The gate of the NMOS transistor (M36) is connected to the third bias voltage and connected to the gate of the NMOS transistor (M33), and the source of the NMOS transistor (M36) is grounded. 4. The drive circuit according to claim 3, characterized in that, the closed-loop negative feedback loop includes a differential op amp (40) and a differential op amp (41), and the drive circuit also includes a bias current source, The differential operational amplifier positive input terminal of the differential operational amplifier (40) is connected to the initial reference voltage Vrpin, the differential operational amplifier negative input terminal of the differential operational amplifier (40) is connected to the source of the NMOS transistor (M34), and the differential operational amplifier The output end of (40) is connected to one end of the charge pump (24), and the other end of the charge pump (24) is connected to the gate of the NMOS transistor (M34), and the gates of the NMOS transistor (M34) and the NMOS transistor (M31) are provided the first bias voltage; The differential operational amplifier positive input terminal of the differential operational amplifier (41) is connected to the initial reference voltage Vrnin, the differential operational amplifier negative input terminal of the differential operational amplifier (41) is connected to the source of the NMOS transistor (M35), and the differential operational amplifier The output terminal of (41) is connected to the gate of the NMOS transistor (M35), and the second bias voltage is provided to the gates of the NMOS transistor (M35) and the NMOS transistor (M32); The output end of the bias current source is connected to the drain of the NMOS transistor (M37), the source of the NMOS transistor (M37) is connected to the drain of the NMOS transistor (M38), and the source of the NMOS transistor (M38) is grounded, Both the output end of the bias current source and the gate of the NMOS transistor (M38) are connected to the gate of the NMOS transistor (M36), and the third bias is provided to the gates of the NMOS transistor (M36) and the NMOS transistor (M33). Voltage. 5. The driving circuit according to claim 4, characterized in that, The negative input terminal of the differential operational amplifier (40) is connected to the source of the NMOS transistor (M34) through a resistor (R1); The negative input terminal of the differential operational amplifier (41) is connected to the source of the NMOS transistor (M35) through a resistor (R2). 6. The drive circuit according to claim 4, characterized in that, The gate of the NMOS transistor (M34) is also connected to one end of the capacitor (25), and the other end of the capacitor (25) is grounded; The gate of the NMOS transistor (M35) is also connected to one end of the capacitor (26), and the other end of the capacitor (26) is grounded; The gate of the NMOS transistor (M36) is also connected to one end of the capacitor (27), and the other end of the capacitor (27) is grounded. 7. The drive circuit according to claim 4, characterized in that the charge pump (24) includes a capacitor (C1) and a capacitor (C2), One end of the capacitor (C1) is connected or disconnected from the DC voltage Vbn2 through the switch (K11) and connected or disconnected from one end of the capacitor (C2) through the switch (K21), and the other end of the capacitor (C1) is connected or disconnected through the switch (K12) ) is connected or disconnected with the power supply VDD and connected or disconnected with the other end of the capacitor (C2) through the switch (K22); One end of the capacitor (C2) is also connected to the output end of the differential operational amplifier (40), and the other end of the capacitor (C2) is also connected to the gate of the NMOS transistor (M34). 8. The drive circuit according to claim 1, characterized in that the electrical isolation device is a resistor (R33), one end of the resistor (R33) is connected to the source of the NMOS transistor (M32), and the resistor ( The other end of R33) is grounded. 9. The drive circuit according to claim 8, characterized in that the closed-loop negative feedback loop includes a branch (21), and the branch (21) includes an NMOS transistor (M34), an NMOS transistor (M35) and a resistor (R36), the branch (21) is set so that the proportional relationship between the current on the branch (21) and the current on the open-loop branch is 1:K, where, The drain of the NMOS transistor (M34) is connected to the power supply VDD, the gate of the NMOS transistor (M34) is connected to the first bias voltage and connected to the gate of the NMOS transistor (M31), and the source of the NMOS transistor (M34) is connected to the The drain of the NMOS transistor (M35) is connected; The gate of the NMOS transistor (M35) is connected to the second bias voltage and connected to the gate of the NMOS transistor (M32), and the source of the NMOS transistor (M35) is connected to one end of the resistor (R36); The other end of the resistor (R36) is grounded. 10. The driving circuit according to claim 9, characterized in that, the closed-loop negative feedback loop includes a differential operational amplifier (40) and a differential operational amplifier (41), The differential operational amplifier positive input terminal of the differential operational amplifier (40) is connected to the initial reference voltage Vrpin, the differential operational amplifier negative input terminal of the differential operational amplifier (40) is connected to the source of the NMOS transistor (M34), and the differential operational amplifier The output end of (40) is connected to one end of the charge pump (24), and the other end of the charge pump (24) is connected to the gate of the NMOS transistor (M34), and the gates of the NMOS transistor (M34) and the NMOS transistor (M31) are provided the first bias voltage; The differential operational amplifier positive input terminal of the differential operational amplifier (41) is connected to the initial reference voltage Vrnin, the differential operational amplifier negative input terminal of the differential operational amplifier (41) is connected to the source of the NMOS transistor (M35), and the differential operational amplifier The output terminal of (41) is connected to the gate of the NMOS transistor (M35), and provides the second bias voltage to the gates of the NMOS transistor (M35) and the NMOS transistor (M32).

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