CN103646954A - A method for manufacturing a dual stress liner and a semiconductor device containing a dual stress liner - Google Patents
A method for manufacturing a dual stress liner and a semiconductor device containing a dual stress liner Download PDFInfo
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- CN103646954A CN103646954A CN201310625572.4A CN201310625572A CN103646954A CN 103646954 A CN103646954 A CN 103646954A CN 201310625572 A CN201310625572 A CN 201310625572A CN 103646954 A CN103646954 A CN 103646954A
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- 238000000034 method Methods 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 230000009977 dual effect Effects 0.000 title description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 65
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000011261 inert gas Substances 0.000 claims abstract description 15
- 230000006835 compression Effects 0.000 claims description 16
- 238000007906 compression Methods 0.000 claims description 16
- 238000009832 plasma treatment Methods 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 6
- 229910052786 argon Inorganic materials 0.000 claims description 5
- 230000008859 change Effects 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 9
- 150000002500 ions Chemical class 0.000 abstract description 6
- 238000000151 deposition Methods 0.000 abstract description 3
- 230000001965 increasing effect Effects 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 230000035882 stress Effects 0.000 description 41
- 239000010410 layer Substances 0.000 description 18
- 238000005516 engineering process Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- -1 argon ion Chemical class 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 230000003446 memory effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
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- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本发明提供了一种双应力薄膜的制造方法及具有双应力薄膜的半导体器件，该制造方法在衬底上沉积一层具有张应力的氮化硅薄膜后，对NMOS区域的氮化硅薄膜进行掩盖，然后利用惰性气体离子对PMOS区域的氮化硅薄膜进行离子注入，使得PMOS区域的氮化硅薄膜从张应力薄膜转变成压应力薄膜，避免了传统的SMT工艺对PMOS器件产生负面影响的问题，在提高NMOS器件速度的情况下，也提高了PMOS器件的性能，且工艺简单且易实施。
The invention provides a method for manufacturing a double-stress film and a semiconductor device with a double-stress film. In the manufacturing method, after depositing a layer of silicon nitride film with tensile stress on a substrate, the silicon nitride film in the NMOS region is Covering, and then using inert gas ions to perform ion implantation on the silicon nitride film in the PMOS area, so that the silicon nitride film in the PMOS area changes from a tensile stress film to a compressive stress film, avoiding the negative impact of the traditional SMT process on the PMOS device. The problem is that in the case of increasing the speed of NMOS devices, the performance of PMOS devices is also improved, and the process is simple and easy to implement.
Description
Technical field
The present invention relates to integrated circuit and manufacture field, particularly the manufacture method of a kind of pair of stress film and there is the semiconductor device of two stress films.
Background technology
Along with the development of cmos semiconductor device technology and in proportion size dwindle, stress engineering is playing increasing effect aspect semiconductor technology and device performance; In cmos device, introduce stress, mainly in order to improve device carrier mobility, useful to NMOS electron mobility at the upper tensile stress of cmos device channel direction (longitudinal), and compression is useful to PMOS hole mobility, tensile stress in channel width dimension (transverse) is all useful to the carrier mobility of NMOS and PMOS device, and useful to nmos device electron mobility in the compression of vertical-channel in-plane (out-of-plane), tensile stress is useful to PMOS device hole mobility.
Stress memory effect (SMT, Stress memorization technique) be a kind of method of stress of introducing in CMOS technique, conventionally its technological process is: after device source/leakage is injected, deposition one deck silicon nitride film protective layer (cap layer), and then carry out source/leakage annealing, in source/leakage annealing process, can produce silicon nitride film protective layer, thermal stress between polysilicon gate and side wall and internal stress effect, these stress can be by memory among polysilicon gate, in polysilicon, along vertical-channel in-plane (out-of-plane), can produce tensile stress, and channel direction (longitudinal) can produce compression, in ensuing technique, silicon nitride film protective layer is etched away, but the stress of memory in polysilicon gate, still can be transmitted among the raceway groove of cmos semiconductor device, the stress being transmitted in raceway groove is the compression of vertical-channel in-plane (out-of-plane) and the tensile stress on channel direction (longitudinal), by above-mentioned stress, on the impact of cmos device carrier mobility, can be drawn, such stress effect is useful to improving nmos device electron mobility, can improve nmos device performance.
Strained silicon technology (Stain silicon) integrated technique starts to be applied on a large scale in 45 nanometer nodes.For (PMD loop) in dielectric deposition process section before metal, two stress films (Dual StressLiner) become essential option, are used for improving device speed especially.But with regard to technique is integrated at present, it is a difficult point that the overlapping region of different stress films is processed, and is easy to cause because of overlapping region the loss of yield.At present for overlapping problem, the mainly adjustment by dry etch process or take in the time of layout design, to reduce the impact on yield as far as possible, but increased the difficulty of technology controlling and process, and said method all can not thoroughly be dealt with problems effectively.
Summary of the invention
The invention provides the manufacture method of a kind of pair of stress film, solved the problem that traditional SMT technique has a negative impact to PMOS device, in the situation that improving nmos device speed, also improved the performance of PMOS device, technique simply and is easily implemented.
For solving the problems of the technologies described above, the invention provides the manufacture method of a kind of pair of stress film, comprising:
One substrate with territory, nmos area and PMOS region is provided, on described substrate, is formed with silicon nitride film, described silicon nitride film is tensile stress film;
On the silicon nitride film in territory, described nmos area, cover photoresist layer;
Adopt inert gas ion to carry out plasma treatment to the silicon nitride film in described PMOS region, make the silicon nitride film in described PMOS region change compression film into; And
Remove the photoresist layer on the silicon nitride film in territory, described nmos area.
Optionally, described inert gas is argon gas, carries out the time of inert gas plasma processing between 3～6 minutes, and the flow of inert gas is between 1000～6000sccm, and reaction chamber pressure is between 1～5Torr, and radio-frequency power is between 500～2000W.
Optionally, carry out the tensile stress of the silicon nitride film before plasma treatment between 500～2000MPa, carry out the compression of the silicon nitride film after plasma treatment between-500～-3500MPa.
Optionally, the thickness of described silicon nitride film, between 100～1000 dusts, utilizes plasma enhanced chemical vapor deposition technique on substrate, to form silicon nitride film.
The present invention also provides a kind of semiconductor device with two stress films, comprising:
The substrate with territory, nmos area and PMOS region; And
Be formed at the silicon nitride film on described substrate, the silicon nitride film on territory, described nmos area is tensile stress film, and the silicon nitride film on described PMOS region is compression film.
Compared with prior art, the present invention deposits after the silicon nitride film that one deck has tensile stress on substrate, carrying out photoetching covers the silicon nitride film in territory, nmos area, then utilize inert gas ion the silicon nitride film in PMOS region to be carried out to Implantation as argon ion, make the silicon nitride film in PMOS region be transformed into compression film from tensile stress film, the problem of not only having avoided traditional SMT technique to have a negative impact to PMOS device, and in the situation that improving nmos device speed, also improved the performance of PMOS device, technique simply and is easily implemented.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of manufacture method of two stress films of one embodiment of the invention;
Fig. 2 to Fig. 6 is the device profile structural representation in the manufacture method process of two stress films of one embodiment of the invention.
Embodiment
Although below with reference to accompanying drawings the present invention is described in more detail, wherein represented the preferred embodiments of the present invention, be to be understood that those skilled in the art can revise the present invention described here and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensive instruction for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details to realize developer's specific objective, for example, according to the restriction of relevant system or relevant business, by an embodiment, change into another embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, with reference to accompanying drawing, with way of example, the present invention is more specifically described.Will be clearer according to following explanation and claims advantages and features of the invention.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, on substrate, deposit after the silicon nitride film that one deck has tensile stress, carrying out photoetching covers the silicon nitride film in territory, nmos area, then utilize inert gas ion the silicon nitride film in PMOS region to be carried out to Implantation as argon ion, make the silicon nitride film in PMOS region be transformed into compression film from tensile stress film, the problem of not only having avoided traditional SMT technique to have a negative impact to PMOS device, and in the situation that improving nmos device speed, also improved the performance of PMOS device, technique simply and is easily implemented.
As shown in Figure 1, the manufacture method of two stress films of one embodiment of the invention, comprises the steps:
Step S1 a: substrate with territory, nmos area and PMOS region is provided, is formed with silicon nitride film on described substrate, described silicon nitride film is tensile stress film;
As shown in Figure 2, first, the substrate 100 that comprises territory, nmos area 100a and PMOS region 100b is provided, on the territory 100a of described nmos area, be formed with first grid 111 and around the first side wall 121 of described first grid 111, on described PMOS region 100b, be formed with second grid 112 and around the second side wall 122 of described second grid 112.Described substrate 100 is including but not limited to the silicon materials that comprise semiconductor element, and for example the silicon of monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe), can be also silicon-on-insulator (SOI).Described nmos area territory 100a is in order to form nmos pass transistor, and described PMOS region 100b is in order to form PMOS transistor.In described substrate 100, can also be formed with dopant well, wherein, described dopant well can utilize ion implantation technology to complete, and the dopant well of described P type or N-type is used to form the conducting channel of NMOS or PMOS.Take NMOS as example, and described dopant well is P type, and this dopant well is not shown.On the territory 100a of described nmos area, be also formed with first grid dielectric layer 131, on described PMOS region 100b, be also formed with second gate dielectric layer 132, described first grid dielectric layer 131 and second gate dielectric layer 132 comprise silicon oxide layer or silicon oxynitride layer.Described the first side wall 121 and the second side wall 122 comprise silicon oxide layer, silicon oxynitride layer and/or silicon nitride layer.In addition, in described substrate 100, be also formed with fleet plough groove isolation structure 200.
As shown in Figure 3, then, deposition forms silicon nitride film 140, described silicon nitride film 140 covers described nmos area territory 100a, PMOS region 100b, first grid 111, second grid 112, the first side wall 121 and the second side wall 122, that is, described silicon nitride film 140 covers whole substrate 100 surfaces.In the present embodiment, adopt nitrogenous gas on substrate 100, to deposit the silicon nitride film 140 of preset thickness.Can utilize plasma enhanced chemical vapor deposition technique (PECVD) to form the silicon nitride film 140 of described preset thickness.Wherein, the process conditions of described plasma enhanced chemical vapor deposition technique are for example: reaction chamber pressure is between 2～10torr, and radio-frequency power is between 100～1500w, and temperature is between 300～450 ℃.The reacting gas of described plasma enhanced chemical vapor deposition technique is SiH4 and NH3.In this step, also can adopt helium (He) as the protective gas of reaction, to guarantee to react, carry out smoothly, by the oxygen in the middle of air, do not disturbed.In the present embodiment, the predetermined thickness of described silicon nitride film 140 is between 100～1000 dusts.
Step S2: cover photoresist layer on the silicon nitride film in territory, described nmos area;
As shown in Figure 4, use conventional methods and on the silicon nitride film of described nmos area territory 100a, cover photoresist layer 150a, described photoresist layer 150a is not affected by follow-up step in order to block the silicon nitride film of described nmos area territory 100a, the thickness of described photoresist layer 150a can need to be adjusted according to technique.
Step S4: adopt inert gas ion to carry out plasma treatment to the silicon nitride film in described PMOS region, make the silicon nitride film in described PMOS region change compression film into;
As shown in Figure 5, adopt inert gas ion as argon ion to as described in the silicon nitride film of PMOS region 100b carry out plasma treatment, through present inventor's discovery of repeatedly testing and study for a long period of time, after plasma treatment, the silicon nitride film originally with tensile stress changes compression film into, that is to say, after treatment, the silicon nitride film of PMOS region 100b changes compression film into, for convenience of description, the follow-up silicon nitride film by process plasma treatment is designated as silicon nitride film 140 '.In the present embodiment, the tensile stress of initial silicon nitride film 140 is between 500～2000MPa, and the compression of the silicon nitride film 140 ' after plasma treatment is between-500～-3500MPa.In the present embodiment, carry out the time of inert gas plasma processing between 3～6 minutes, the flow of inert gas is between 1000～6000sccm, and reaction chamber pressure is between 1～5Torr, and radio-frequency power is between 500～2000W.
Step S5: remove the photoresist layer on the silicon nitride film in territory, described nmos area;
As shown in Figure 6, after step S4, can utilize traditional method ashing to remove the photoresist layer 150a on the silicon nitride film of territory, nmos area 100a.So, can obtain two stress films (silicon nitride film 140 ', 140 ' ') with higher tensile stress and higher pressure stress simultaneously.
Subsequently, adopt HARP technique on substrate 100, to deposit HARP film, and carry out chemical mechanical milling tech until expose described grid structure, subsequent technique is routine techniques, repeats no more herein.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these change and modification.
Claims (8)
1. a manufacture method for two stress films, is characterized in that,
One substrate with territory, nmos area and PMOS region is provided, on described substrate, is formed with silicon nitride film, described silicon nitride film is tensile stress film;
On the silicon nitride film in territory, described nmos area, cover photoresist layer;
Adopt inert gas ion to carry out plasma treatment to the silicon nitride film in described PMOS region, make the silicon nitride film in described PMOS region change compression film into; And
Remove the photoresist layer on the silicon nitride film in territory, described nmos area.
2. the manufacture method of as claimed in claim 1 pair of stress film, is characterized in that, described inert gas is argon gas.
3. the manufacture method of as claimed in claim 2 pair of stress film, it is characterized in that, carry out the time of inert gas plasma processing between 3～6 minutes, the flow of inert gas is between 1000～6000sccm, reaction chamber pressure is between 1～5Torr, and radio-frequency power is between 500～2000W.
4. the manufacture method of as claimed in claim 1 pair of stress film, is characterized in that, carries out the tensile stress of the silicon nitride film before plasma treatment between 500Mpa to 2000MPa.
5. the manufacture method of as claimed in claim 1 pair of stress film, is characterized in that, the compression of carrying out the silicon nitride film after plasma treatment at-500Mpa between-3500MPa.
6. the manufacture method of as claimed in claim 1 pair of stress film, is characterized in that, the thickness of described silicon nitride film is between 100～1000 dusts.
7. the manufacture method of as claimed in claim 1 pair of stress film, is characterized in that, utilizes plasma enhanced chemical vapor deposition technique on substrate, to form silicon nitride film.
8. there is a semiconductor device for two stress films, utilize the manufacture method of two stress films of any one in claim 1～7 to obtain, comprising:
The substrate with territory, nmos area and PMOS region; And
Be formed at the silicon nitride film on described substrate, the silicon nitride film on territory, described nmos area is tensile stress film, and the silicon nitride film on described PMOS region is compression film.
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| CN116111455A (en) * | 2023-03-08 | 2023-05-12 | 江苏第三代半导体研究院有限公司 | A GaN-based laser and its preparation method |
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Application publication date: 20140319 |