CN103604968B - Eliminate the system that peakvalue's checking produces burr by mistake - Google Patents
Eliminate the system that peakvalue's checking produces burr by mistake Download PDFInfo
- Publication number
- CN103604968B CN103604968B CN201310665549.8A CN201310665549A CN103604968B CN 103604968 B CN103604968 B CN 103604968B CN 201310665549 A CN201310665549 A CN 201310665549A CN 103604968 B CN103604968 B CN 103604968B
- Authority
- CN
- China
- Prior art keywords
- value
- minimum value
- maximal value
- maximal
- comparer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Radar Systems Or Details Thereof (AREA)
Abstract
The invention provides and eliminate the system that peakvalue's checking produces burr by mistake, invention increases the ranking function of maximal value and minimum value, store the sampling order of maximal value and minimum value strictly according to the facts, sort according to two kinds of orders respectively in the rising and decline state of signal like this, edge would not increase burr by mistake.
Description
Technical field
The present invention relates to digital storage oscilloscope data sampling field, especially eliminate the system that peakvalue's checking produces burr by mistake.
Background technology
Data sampling, data processing and data display are digital oscilloscope major parts, and data sampling is exactly that digital to analog converter carries out digital quantization sampling to simulating signal, and sampled data is postponed being flushed in storer, wait for data processing.Sample as the basis of the data processings such as digital oscilloscope wave form analysis computing, sampling interval is less, and namely sampling rate is higher, and display waveform is more close to original signal; Peakvalue's checking is exactly digital to analog converter in most high sampling rate down-sampled data, when different the corresponding extraction yield N of base gear one group of sampled data in maximal value detected, in minimum value data input reservoir.
But existing peak detection methods does not keep former sampling time sequence to the maximal value gathered and minimum value when storing, but with default behavior, with fixing order Dmin, Dmax or Dmax, Dmin sorts, but two kinds of orders exist in the rising and decline state of signal simultaneously, sort according to default behavior, a kind of order meeting mistake must be had, there is burr in the waveform edge of display, for square wave, as Figure 1-1, Dmax is selected in figure, Dmin order, at waveform rising edge, point Dmin, Dmax selects this order timing error, there is burr in waveform, as shown in Figure 1-2, select Dmin in figure, Dmax order, at waveform negative edge, some Dmax, Dmin select this order timing error, and burr appears in waveform.
Summary of the invention
Technical matters to be solved: the invention provides for above problem and eliminate the system that peakvalue's checking produces burr by mistake, invention increases the ranking function of maximal value and minimum value, store the sampling order of maximal value and minimum value strictly according to the facts, sort according to two kinds of orders respectively in the rising and decline state of signal like this, edge would not increase burr by mistake.
Technical scheme: in order to overcome the above problems, the invention provides and eliminate the system that peakvalue's checking produces burr by mistake, comprise PLL, ADC, CLK1, CLK2, reduction of speed processor module, peak detection block, reservoir;
Described PLL is phaselocked loop, provides the clock frequency needed for ADC sampling;
Described ADC provides the data-signal of analog-converted numeral;
Described CLK1 is ADC sampling clock, and CLK2 is the clock that after reduction of speed, data export, and reduction of speed coefficient is 2
n, meet CLK2=CLK1/2
n;
Described reduction of speed processing module utilizes string to turn and technology, and data bit is expanded, and the data-signal that ADC exports is synchronous through CLK1, is input to reduction of speed processor module;
Described peak detection block comprises peak value parallel detection module, peak value serial detection module, output switch, N digit counter; The data of ADC are become 2 by described peak value parallel detection module after reduction of speed processor module
nindividual parallel data, is compared between two by comparer at different levels and exports large value and little value, compare obtain maximal value and minimum value through n level;
Described peak value serial detection module comprises maximum value detector, minimum detector, the maximal value exported through peak value parallel detection module and minimum value are input in corresponding maximum value detector and minimum detector respectively, contrast with the maximal value of last time and minimum value respectively, the maximal value of new input is greater than the maximal value of last time and just the maximal value newly inputted is remained, otherwise keep the maximal value of last time, the minimum value of new input is less than the minimum value of last time and just the minimum value newly inputted is remained, otherwise keeps the minimum value of last time constant;
Described N digit counter is the number of times of counting input maximal value and minimum value, N digit counter counts CLK2, often carry out a clock, counter adds 1, when N digit counter does not complete counting, output switch disconnects, when N digit counter completes counting, output switch closes, and is input in reservoir by final maximal value and final minimum value;
It is characterized in that: described peak value parallel detection module also comprises S1 comparer, data also export and indicate position Pmax.i or Pmin.i while comparer at different levels compares the large value of output and little value between two; And i=2
n-2, n is positive integer; Through n level compare select maximal value and minimum value while export sequencing signal S1, wherein the 1st grade has 2
n-1individual comparer, the 2nd grade has 2
n-2individual large value comparer and 2
n-2little value comparer, the like have 1 large value comparer and 1 little value comparer at n-th grade; Described sequencing signal S1 is that Smax and Smin compares acquisition through S1 comparer, described Smax and Smin be export maximal value and minimum value 2
nposition in individual data, this position is that Pmin.i determines, method is as follows by sign position Pmax.i at different levels:
First according to the afterbody i.e. sign position Pmax.i of n-th grade of comparer, Pmin.i, determine that maximal value and minimum value are the upper half or bottom half got, described upper half is 2
nthe first half of individual data, bottom half is 2
nthe latter half of individual data; And then according to the penultimate stage i.e. sign position of (n-1)th grade of comparer, in the district of place half, reduce the position of half scope determination maximal value and minimum value again; Recursion one-level forward in the same way again, reduces the position of half scope determination maximal value and minimum value again, recursion so layer by layer, finally determines that maximal value and minimum value are 2 in place half district
nparticular location in individual data;
When comparing for the 1st grade, when one is large value, another is then little value, and Pmax.i and Pmin.i is negate relation, that is: during Pmax.i=1, during Pmin.i=0 or Pmax.i=0, and Pmin.i=1;
As Smax>Smin, sequencing signal S1=1, data output sequence: Dmin, Dmax is propradation, as Smax<Smin, sequencing signal S1=0, data output sequence: Dmax, Dmin, for being decline state;
Described peak value serial detection module also comprises S2 comparer, and described peak detection block also comprises switch, sequence;
Described peak value serial detection module exports a sequencing signal S2 while selecting final maximal value and final minimum value, described sequencing signal S2 is that in peak value serial detection module, maximal value update times FNmax and minimum value update times FNmin compares acquisition through S2 comparer, the maximal value exported through peak value parallel detection module and minimum value are input in corresponding maximum value detector and minimum detector respectively, contrast with the maximal value of last time and minimum value respectively, if the maximal value that the new maximal value inputted is greater than last time just the maximal value newly inputted is remained and update times FNmax adds 1, otherwise keep last time maximal value and update times FNmax is constant, if the minimum value that the new minimum value inputted is less than last time just the minimum value newly inputted is remained and update times FNmin adds 1, otherwise keep last time minimum value and update times FNmin is constant,
Maximal value update times FNmax and minimum value update times FNmin inputs S2 comparer, if FNmax is greater than FNmin and maximal value update times is greater than minimum value update times, sequencing signal S2=1, data output sequence: Dmin, Dmax, it is propradation, if FNmax is less than FNmin and maximal value update times is less than minimum value update times, sequencing signal S2=0, data output sequence: Dmax, Dmin, for being decline state, if FNmax equals FNmin and maximal value update times equals minimum value update times, need not again differentiation order, can be included in rising or decline state,
As N=1, switch disconnects, and the maximal value that peak value parallel detection module exports and minimum value, without peak value serial detection module, be directly inputted to after sequence in reservoir, sorts and determines the sequencing of maximal value and minimum value output according to sequencing signal S1; As N>1, switch closes, peak value parallel detection module export maximal value and minimum value synchronous through CLK2, be input to peak value serial detection module, when N digit counter completes counting, the final maximal value exported and final minimum value are input in reservoir after sequence, sort and determine the sequencing of final maximal value and the output of final minimum value according to sequencing signal S2.
Beneficial effect: the ranking function that invention increases maximal value and minimum value, stores the sampling order of maximal value and minimum value strictly according to the facts, sorts respectively like this, edge would not increase burr by mistake in the rising and decline state of signal according to two kinds of orders.
Accompanying drawing explanation
Waveform rising edge burr dotted line in Fig. 1-1 the present invention is correct tactic waveform, and solid line is the burr waveform of wrong sequence arrangement.
Waveform negative edge burr dotted line in Fig. 1-2 the present invention is correct tactic waveform, and solid line is the burr waveform of wrong sequence arrangement.
Waveform propradation in Fig. 2-1 the present invention.
Waveform decline state in Fig. 2-2 the present invention.
Waveform equivalent state in Fig. 2-3 the present invention.
Peakvalue's checking entire block diagram in Fig. 3 the present invention.
Peak value parallel detection schematic diagram in Fig. 4 the present invention.
Peak value serial Cleaning Principle figure in Fig. 5 the present invention.
Embodiment
Below in conjunction with Figure of description, the invention will be further described.
Embodiment
As shown in Fig. 2-1 to Fig. 5, eliminate the system that peakvalue's checking produces burr by mistake, comprise PLL, ADC, CLK1, CLK2, reduction of speed processor module, peak detection block, reservoir;
Described PLL is phaselocked loop, provides the clock frequency needed for ADC sampling;
Described ADC provides the data-signal of analog-converted numeral;
Described CLK1 is ADC sampling clock, and CLK2 is the clock that after reduction of speed, data export, and reduction of speed coefficient is 2
n, meet CLK2=CLK1/2
n;
Described reduction of speed processing module utilizes string to turn and technology, and data bit is expanded, and the data-signal that ADC exports is synchronous through CLK1, is input to reduction of speed processor module;
Described peak detection block comprises peak value parallel detection module, peak value serial detection module, switch, sequence, output switch, N digit counter;
As shown in Figure 4, during n=3,2
nwhen=8, the data of ADC are become 8 parallel datas by described peak value parallel detection module after reduction of speed processor module, compared between two by comparer, also export while exporting large value and little value and indicate position Pmax.i or Pmin.i, compare through 3 grades and obtain maximal value and minimum value, export sequencing signal S1 simultaneously, described 3 grades relatively in the first order compare and comprise comparer 1 to 4, the second level is compared and is comprised large value comparer 5 to 6, little value comparer 7 to 8, the third level is compared and comprises large value comparer 9 and little value comparer 10; Described sequencing signal S1 is that Smax and Smin compares acquisition through S1 comparer, described Smax and Smin be export maximal value and minimum value in the position of 8 data, this position is that Pmin.i determines by sign position Pmax.i at different levels:
First according to afterbody and 3rd level comparer, the sign position Pmax.6 of large value comparer 9, the sign position Pmin.6 of little value comparer 10, determines that maximal value is the upper half (D got
a, D
b, D
c, D
d) i.e. bottom half (the D that still gets of large value comparer 5
e, D
f, D
g, D
h) being namely worth comparer 6 greatly, minimum value is the upper half (D got
a, D
b, D
c, D
d) i.e. little value comparer 7, the bottom half (D still got
e, D
f, D
g, D
h) i.e. little value comparer 8;
And then the position of maximal value and minimum value is determined according to the sign position of the 2nd grade of comparer, if maximal value gets big value comparer 5, minimum value is the little value comparer 7 got, then according to the sign position Pmax.4 of large value comparer 5, the sign position Pmin.4 of little value comparer 7, in the district of place half, reduce half scope again, determine the comparer 1 that maximal value and minimum value are got or comparer 2; In like manner, if maximal value gets big value comparer 6, minimum value is the little value comparer 8 got, then according to the sign position Pmax.5 of large value comparer 6, the sign position Pmin.5 of little value comparer 8, in the district of place half, reduce half scope again, determine the comparer 3 that maximal value and minimum value are got or comparer 4;
Last in the same way to previous stage recursion, according to the sign position Pmax.0 of the 1st grade of comparer, Pmin.0 or Pmax.1, Pmin.1, or Pmax.2, Pmin.2 or Pmax.3, Pmin.3 finally determines maximal value and the particular location of minimum value in 8 data.
When comparing for the 1st grade, when one is large value, another is then little value, and Pmax.i and Pmin.i is negate relation, that is: during Pmax.0=1, during Pmin.0=0 or Pmax.0=0, and Pmin.0=1; During Pmax.1=1, during Pmin.1=0 or Pmax.1=0, Pmin.1=1; During Pmax.3=1, during Pmin.3=0 or Pmax.3=0, Pmin.3=1; During Pmax.4=1, during Pmin.4=0 or Pmax.4=0, Pmin.4=1;
As Smax>Smin, sequencing signal S1=1, data output sequence: Dmin, Dmax is propradation, as Smax<Smin, sequencing signal S1=0, data output sequence: Dmax, Dmin is decline state;
Described peak value serial detection module also comprises S2 comparatively device, and described peak detection block also comprises switch, sequence;
Described peak value serial detection module exports a sequencing signal S2 while selecting final maximal value and final minimum value, described sequencing signal S2 is that in peak value serial detection module, maximal value update times FNmax and minimum value update times FNmin compares acquisition through S2 comparer, the maximal value exported through peak value parallel detection module and minimum value are input in corresponding maximum value detector and minimum detector respectively, contrast with the maximal value of last time and minimum value respectively, if the maximal value that the new maximal value inputted is greater than last time just the maximal value newly inputted is remained and update times FNmax adds 1, otherwise keep last time maximal value and update times FNmax is constant, if the minimum value that the new minimum value inputted is less than last time just the minimum value newly inputted is remained and update times FNmin adds 1, otherwise keep last time minimum value and update times FNmin is constant,
Maximal value update times FNmax and minimum value update times FNmin inputs S2 comparer, if FNmax is greater than FNmin and maximal value update times is greater than minimum value update times, sequencing signal S2=1, data output sequence: Dmin, Dmax, it is propradation, if FNmax is less than FNmin and maximal value update times is less than minimum value update times, sequencing signal S2=0, data output sequence: Dmax, Dmin, for being decline state, if FNmax equals FNmin and maximal value update times equals minimum value update times, need not again differentiation order, can be included in rising or decline state,
As shown in Fig. 2-1, when propradation, minimum value is first time sampling, maximal value is last sampling, namely the data of new sampling are becoming greatly always, and namely maximal value is upgrading always, and minimum value does not upgrade, so the update times of maximal value is greater than the update times of minimum value, S2=1 in S2 comparer, data output sequence is Dmin, Dmax, be propradation, conform to Fig. 2-1;
As shown in Fig. 2-2, when decline state, maximal value is first time sampling, minimum value is sampled the last time, namely the data of new sampling are diminishing always, and namely minimum value is upgrading always, and maximal value does not upgrade, so the update times of maximal value is less than the update times of minimum value, S2=0 in S2 comparer, data output sequence is Dmax, Dmin, be decline state, conform to Fig. 2-2;
As Figure 2-3, when not rising the state also do not declined, maximal value update times is equal with minimum value update times, need not again differentiation order, so just can be included in the state risen or decline, in the present invention this situation is included into decline state, conform to Fig. 2-3;
As N=1, switch disconnects, and the maximal value that peak value parallel detection module exports and minimum value, without peak value serial detection module, be directly inputted to after sequence in reservoir, sorts and determines the sequencing of maximal value and minimum value output according to sequencing signal S1; As N>1, switch closes, peak value parallel detection module export maximal value and minimum value synchronous through CLK2, be input to peak value serial detection module, when N digit counter completes counting, the final maximal value exported and final minimum value are input in reservoir after sequence, sort and determine the sequencing of final maximal value and the output of final minimum value according to sequencing signal S2.
When N digit counter completes counting, the maximal value after sequence and minimum value are outputted in reservoir, as a sampled point of peakvalue's checking; Whole peakvalue's checking repeated sampling, is filled with to storer and terminates sampling, complete a screen waveform acquisition.
Claims (1)
1. eliminate the system that peakvalue's checking produces burr by mistake, comprise PLL, ADC, CLK1, CLK2, reduction of speed processor module, peak detection block, reservoir;
Described PLL is phaselocked loop, provides the clock frequency needed for ADC sampling;
Described ADC provides the data-signal of analog-converted numeral;
Described CLK1 is ADC sampling clock, and CLK2 is the clock that after reduction of speed, data export, and reduction of speed coefficient is 2
n, meet CLK2=CLK1/2
n;
Described reduction of speed processor module utilizes string to turn and technology, and data bit is expanded, and the data-signal that ADC exports is synchronous through CLK1, is input to reduction of speed processor module;
Described peak detection block comprises peak value parallel detection module, peak value serial detection module, output switch, N digit counter; The data of ADC are become 2 by described peak value parallel detection module after reduction of speed processor module
nindividual parallel data, is compared between two by comparer at different levels and exports large value and little value, compare obtain maximal value and minimum value through n level;
Described peak value serial detection module comprises maximum value detector, minimum detector, the maximal value exported through peak value parallel detection module and minimum value are input in corresponding maximum value detector and minimum detector respectively, contrast with the maximal value of last time and minimum value respectively, the maximal value of new input is greater than the maximal value of last time and just the maximal value newly inputted is remained, otherwise keep the maximal value of last time, the minimum value of new input is less than the minimum value of last time and just the minimum value newly inputted is remained, otherwise keeps the minimum value of last time constant;
Described N digit counter is the number of times of counting input maximal value and minimum value, N digit counter counts CLK2, often carry out a clock, counter adds 1, when N digit counter does not complete counting, output switch disconnects, when N digit counter completes counting, output switch closes, and is input in reservoir by final maximal value and final minimum value;
It is characterized in that: described peak value parallel detection module also comprises S1 comparer, data also export and indicate position Pmax.i or Pmin.i while comparer at different levels compares the large value of output and little value between two, and i=2
n-2, n is positive integer; Through n level compare select maximal value and minimum value while export sequencing signal S1, wherein the 1st grade has 2
n-1individual comparer, the 2nd grade has 2
n-2individual large value comparer and 2
n-2little value comparer, the like have 1 large value comparer and 1 little value comparer at n-th grade; Described sequencing signal S1 is that Smax and Smin compares acquisition through S1 comparer, described Smax and Smin be export maximal value and minimum value 2
nposition in individual data, this position is that Pmin.i determines, method is as follows by sign position Pmax.i at different levels:
First according to the afterbody i.e. sign position Pmax.i of n-th grade of comparer, Pmin.i, determine that maximal value and minimum value are the upper half or bottom half got, described upper half is equal with the data volume of bottom half, and upper half is 2
nthe first half of individual data, bottom half is 2
nthe latter half of individual data; And then according to inverse the 2nd grade i.e. sign position of (n-1)th grade of comparer, in the district of place half, reduce the position of half scope determination maximal value and minimum value again; Recursion one-level forward in the same way again, reduces the position of half scope determination maximal value and minimum value again, recursion so layer by layer, finally determines that maximal value and minimum value are 2 in place half district
nparticular location in individual data;
When comparing for the 1st grade, when one is large value, another is then little value, and Pmax.i and Pmin.i is negate relation, that is: during Pmax.i=1, during Pmin.i=0 or Pmax.i=0, and Pmin.i=1;
As Smax>Smin, sequencing signal S1=1, data output sequence: Dmin, Dmax is propradation, as Smax<Smin, sequencing signal S1=0, data output sequence: Dmax, Dmin is decline state;
Described peak value serial detection module also comprises S2 comparer, and described peak detection block also comprises switch, sequence;
Described peak value serial detection module exports a sequencing signal S2 while selecting final maximal value and final minimum value, described sequencing signal S2 is that in peak value serial detection module, maximal value update times FNmax and minimum value update times FNmin compares acquisition through S2 comparer, the maximal value exported through peak value parallel detection module and minimum value are input in corresponding maximum value detector and minimum detector respectively, contrast with the maximal value of last time and minimum value respectively, if the maximal value that the new maximal value inputted is greater than last time just the maximal value newly inputted is remained and update times FNmax adds 1, otherwise keep last time maximal value and update times FNmax is constant, if the minimum value that the new minimum value inputted is less than last time just the minimum value newly inputted is remained and update times FNmin adds 1, otherwise keep last time minimum value and update times FNmin is constant,
Maximal value update times FNmax and minimum value update times FNmin inputs S2 comparer, if FNmax is greater than FNmin and maximal value update times is greater than minimum value update times, sequencing signal S2=1, data output sequence: Dmin, Dmax, it is propradation, if FNmax is less than FNmin and maximal value update times is less than minimum value update times, sequencing signal S2=0, data output sequence: Dmax, Dmin, it is decline state, if FNmax equals FNmin and maximal value update times equals minimum value update times, need not again differentiation order, can be included in rising or decline state,
As N=1, switch disconnects, and the maximal value that peak value parallel detection module exports and minimum value, without peak value serial detection module, be directly inputted to after sequence in reservoir, sorts and determines the sequencing of maximal value and minimum value output according to sequencing signal S1; As N>1, switch closes, peak value parallel detection module export maximal value and minimum value synchronous through CLK2, be input to peak value serial detection module, when N digit counter completes counting, the final maximal value exported and final minimum value are input in reservoir after sequence, sort and determine the sequencing of final maximal value and the output of final minimum value according to sequencing signal S2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310665549.8A CN103604968B (en) | 2013-12-10 | 2013-12-10 | Eliminate the system that peakvalue's checking produces burr by mistake |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310665549.8A CN103604968B (en) | 2013-12-10 | 2013-12-10 | Eliminate the system that peakvalue's checking produces burr by mistake |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103604968A CN103604968A (en) | 2014-02-26 |
| CN103604968B true CN103604968B (en) | 2015-12-09 |
Family
ID=50123209
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310665549.8A Active CN103604968B (en) | 2013-12-10 | 2013-12-10 | Eliminate the system that peakvalue's checking produces burr by mistake |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103604968B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105116318B (en) * | 2015-09-02 | 2018-02-02 | 电子科技大学 | A kind of method that burr detection is realized in logic analyser |
| CN105680947B (en) * | 2015-12-29 | 2018-01-19 | 暨南大学 | A kind of Serial data receiving method for filtering out burr |
| CN107517072B (en) * | 2016-06-16 | 2021-07-23 | 上海华虹集成电路有限责任公司 | Decoding circuit for magnetic medium signal reception in ISO7811 protocol |
| CN108288909B (en) * | 2018-01-12 | 2020-03-17 | 广东美的厨房电器制造有限公司 | Method and apparatus for bus voltage ripple control |
| CN114136209B (en) * | 2021-11-24 | 2023-11-24 | 京东方科技集团股份有限公司 | Eyeball position positioning circuit, eyeball position positioning method, substrate and virtual reality wearable device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5115404A (en) * | 1987-12-23 | 1992-05-19 | Tektronix, Inc. | Digital storage oscilloscope with indication of aliased display |
| US6121799A (en) * | 1999-04-29 | 2000-09-19 | Tektronix, Inc. | Interleaved digital peak detector |
| US7834780B2 (en) * | 2006-03-20 | 2010-11-16 | Tektronix, Inc. | Waveform compression and display |
| CN102520228A (en) * | 2011-12-21 | 2012-06-27 | 王子斌 | Peak value detection method in digital storage oscilloscope and system thereof |
-
2013
- 2013-12-10 CN CN201310665549.8A patent/CN103604968B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN103604968A (en) | 2014-02-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103604968B (en) | Eliminate the system that peakvalue's checking produces burr by mistake | |
| CN103294447B (en) | A kind of method and apparatus generating random number | |
| CN103969483B (en) | Digital triggering system of oscilloscope | |
| CN104252406B (en) | The method and device of data processing | |
| CN103310735A (en) | Display control method and display control system both supportive of gray level expansion | |
| CN104298634A (en) | Data transmission system based on FPGA and DSP | |
| CN1981442B (en) | Method and apparatus for subclocking a SAR analog-to-digital converter | |
| US6621443B1 (en) | System and method for an acquisition of data in a particular manner | |
| CN103869130A (en) | Scrolling measurement display ticker for test and measurement instruments | |
| CN106777060A (en) | Node type seismic detector data file management system and method | |
| CN103558434B (en) | A kind of quick position digital oscilloscope trigger point system | |
| CN105116318A (en) | Method for realizing burr detection in logic analyzer | |
| CN103391182A (en) | Frame detection method and device | |
| CN104361374A (en) | Collecting and processing system and method of radio-frequency signals | |
| CN107359868A (en) | Pulse density modulated change-over circuit and method | |
| CN108897038B (en) | A kind of micro-seismic event detection method and system | |
| CN104459259B (en) | A kind of modified waveform interpolation system for oscillograph | |
| CN105306058A (en) | High-speed digital signal acquisition system based on clock phase modulation | |
| CN106506961B (en) | A kind of image processing system and image processing method | |
| CN101232277B (en) | Sampling frequency converting apparatus | |
| CN101620241A (en) | Signal decoding system and decoding method therefor | |
| CN106936435B (en) | Method for rapidly determining ADC splicing sequence | |
| CN103226328B (en) | Synchronous control method of multithreading data acquisition system in acquisition times control mode | |
| CN110308644A (en) | Smart electric meter clock timing precision compensation method, device and equipment | |
| CN103336458B (en) | Multi-thread data acquisition system synchronization control method in acquisition time control mode |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |