CN103578536B - The determination method of flash memory and reference unit thereof - Google Patents
The determination method of flash memory and reference unit thereof Download PDFInfo
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- CN103578536B CN103578536B CN201210283442.2A CN201210283442A CN103578536B CN 103578536 B CN103578536 B CN 103578536B CN 201210283442 A CN201210283442 A CN 201210283442A CN 103578536 B CN103578536 B CN 103578536B
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Abstract
The invention discloses a kind of determination method of flash memory and reference unit thereof.Wherein, flash memory includes: memory element；Multiple reference units；First switch unit, the first switch unit is all connected with multiple reference units；Comparing unit, the first input end of comparing unit is connected with memory element, and the second input of comparing unit is connected by the first switch unit and the first reference unit；And control unit, all it is connected with the first reference unit and the first switch unit, for when the cycle of operation number of the first reference unit is more than or equal to preset times, control the second input of comparing unit by the first switch unit and the first reference unit disconnects, and control the second input of comparing unit and the second reference unit is connected.By the present invention, solve flash memory in prior art and the problem that reference current drifts about easily occurs, and then reached to increase the effect of the reliability under flash memory is repeatedly read and write.
Description
Technical field
The present invention relates to integrated circuit fields, in particular to a kind of flash memory and the determination of reference unit thereof
Method.
Background technology
Along with the development in consumption electronic product market, flash memory as main memorizer at mobile phone, digital camera
Being widely applied Deng in product, market scale is constantly expanding.Flash memory is energy in the case of not powered
The enough long-term information keeping storage, the schematic diagram of its read operation is as it is shown in figure 1, in memory element CA(Array Cell)
With reference unit CRRespectively add certain voltage on the grid of (Ref Cell), from drain electrode read current Ic and Iref, two
Person is compared to each other, if Ic > Iref, then SA exports logic 1；If Ic < Iref, then SA exports logical zero, thus
Reach to read the purpose of storage data.
During flash memory operation, its stable reference unit of needs and electric current thereof determine that memory element is being read
State in which in write operation.But, during actual application, reference unit may be affected by various factors, example
As, the disturbance of power supply is likely to result in the change of the voltage being added on reference unit, thus causes reference cell current
Change.Inventor finds: reference unit is originally after running repeatedly, and its performance can change, and causes with reference to electricity
Stream drifts about, and causes memorizer normally to work, and then causes the reduction of life of storage and stability.
For flash memory in correlation technique, the problem that reference current drifts about easily occurs, the most not yet propose effective
Solution.
Summary of the invention
A kind of flash memory of offer and the determination method of reference unit thereof are provided, existing to solve
There is flash memory in technology that the problem that reference current drifts about easily occurs.
To achieve these goals, according to an aspect of the invention, it is provided a kind of flash memory, including: deposit
Storage unit；Multiple reference units；First switch unit, the first switch unit is all connected with multiple reference units；Ratio
Relatively unit, the first input end of comparing unit is connected with memory element, and the second input of comparing unit passes through first
Switch unit and the first reference unit are connected, and wherein, the first reference unit is the arbitrary reference in multiple reference unit
Unit；And control unit, all it is connected with the first reference unit and the first switch unit, for obtaining the first reference
The cycle of operation number of unit, and when the cycle of operation number of the first reference unit is more than or equal to preset times, by the
Second input and first reference unit of one switch unit control comparing unit disconnect, and control comparing unit
Second input and the second reference unit are connected, and wherein, the second reference unit is the arbitrary ginseng in multiple reference unit
Examine unit, and the second reference unit and the first reference unit are different reference units, the operation of the second reference unit
Periodicity is less than preset times.
Further, control unit includes: enumerator, by call the first reference unit marking signal in terms of carrying out
Number；And controller, it is connected with enumerator, obtains the first reference unit for reading the count results of enumerator
Cycle of operation number.
Further, first input end and first reference unit of the first switch unit are connected, the first switch unit
Second input and the second reference unit are connected, the second input of comparing unit and the outfan of the first switch unit
Being connected, wherein, the first input end of outfan and the first switch unit that control unit controls the first switch unit breaks
Open connection, so that the second input of comparing unit and the first reference unit disconnect；And control unit controls the
The outfan of one switch unit and the second input of the first switch unit are connected, so that the second input of comparing unit
End is connected with the second reference unit.
Further, the first switch unit includes: drain electrode decoding circuit, the first input end conduct of drain electrode decoding circuit
The first input end of the first switch unit and the drain electrode of the first reference unit are connected, the second input of drain electrode decoding circuit
End is connected as the second input of the first switch unit and the drain electrode of the second reference unit, and drain the defeated of decoding circuit
Go out end to be connected with the second input of comparing unit as the outfan of the first switch unit；And gate decoder circuit,
First outfan of gate decoder circuit and the grid of the first reference unit are connected, the second output of gate decoder circuit
End is connected with the grid of the second reference unit, the 3rd outfan of gate decoder circuit and the grid of the 3rd reference unit
Being connected, the first input end of gate decoder circuit is unsettled or ground connection, and the second input of gate decoder circuit connects pre-
If voltage, wherein, the 3rd reference unit is the arbitrary reference unit in multiple reference unit, and the 3rd reference unit
It is different reference units, at the cycle of operation number of the first reference unit from the first reference unit, the second reference unit
During more than or equal to preset times, control unit is additionally operable to first input end and the gate decoder of control gate decoding circuit
First outfan and the 3rd outfan of circuit are all connected, and the second input of control gate decoding circuit and grid
Second outfan of decoding circuit is connected.
Further, the input of the first switch unit is all connected with the drain electrode of multiple reference units, flash memory
Also including: the second switch unit, the first outfan of the second switch unit and the grid of the first reference unit are connected,
Second outfan of the second switch unit and the grid of the second reference unit are connected, the 3rd output of the second switch unit
End is connected with the grid of the 3rd reference unit, and the first input end of the second switch unit is unsettled or ground connection, and second switches
Second input of unit connects predeterminated voltage, and wherein, the 3rd reference unit is the arbitrary reference in multiple reference unit
Unit, and the 3rd reference unit and the first reference unit, the second reference unit be different reference units,
When the cycle of operation number of one reference unit is more than or equal to preset times, control unit controls the first of the second switch unit
Input is all connected with the first outfan of the second switch unit and the 3rd outfan, and controls the second switch unit
Second outfan of the second input and the second switch unit is connected.
To achieve these goals, according to a further aspect in the invention, it is provided that a kind of memory reference unit
Determining method, this determines that method can be performed by the flash memory that foregoing of the present invention is provided.
To achieve these goals, according to a further aspect in the invention, it is provided that a kind of memory reference unit
Determine that method, flash memory include comparing unit and multiple reference unit, wherein it is determined that method includes: obtain the
The cycle of operation number of one reference unit, wherein, the first reference unit is to be connected with comparing unit in multiple reference unit
Reference unit；Judge that whether the cycle of operation number of the first reference unit is less than preset times；And judging first
When the cycle of operation number of reference unit is more than or equal to preset times, controls comparing unit and the first reference unit disconnects even
Connecing, and control comparing unit and the second reference unit is connected, wherein, the second reference unit is in multiple reference unit
Arbitrary reference unit, and the second reference unit and the first reference unit be different reference units, and second with reference to single
The cycle of operation number of unit is less than preset times.
Further, the cycle of operation number obtaining the first reference unit includes: call the marking signal of the first reference unit
To count；And reading obtains the cycle of operation number of the first reference unit to the count results of marking signal.
Further, when the cycle of operation number judging the first reference unit is more than or equal to preset times, the side of determination
Method also includes: control that the grid of the first reference unit is unsettled or ground connection；And the grid of control the 3rd reference unit is unsettled
Or ground connection, wherein, the 3rd reference unit is the arbitrary reference unit in multiple reference unit, and the 3rd reference unit
It is different reference units from the first reference unit, the second reference unit.
By the present invention, use the flash memory including following structure: memory element；Multiple reference units；First
Switch unit, the first switch unit is all connected with multiple reference units；Comparing unit, the first input of comparing unit
End is connected with memory element, and the second input of comparing unit is connected by the first switch unit and the first reference unit
Connecing, wherein, the first reference unit is the arbitrary reference unit in multiple reference unit；And control unit, with first
Reference unit and the first switch unit are all connected, for obtaining the cycle of operation number of the first reference unit, and first
When the cycle of operation number of reference unit is more than or equal to preset times, controlled the of comparing unit by the first switch unit
Two inputs and the first reference unit disconnect, and control the second input and the second reference unit phase of comparing unit
Connect, wherein, the second reference unit is the arbitrary reference unit in multiple reference unit, and the second reference unit with
First reference unit is different reference unit, and the cycle of operation number of the second reference unit is less than preset times.By
Flash memory arranges two or more multiple reference unit, then to first be connected with comparing unit
Whether the cycle of operation number of reference unit reaches certain preset times judges, and in the operation of the first reference unit
When periodicity reaches certain preset times, the second input and the first reference unit that control comparing unit disconnect,
And control the second input of comparing unit and the second reference unit is connected, it is achieved that mated at flash memory
Reference unit works and switches to standby reference unit after certain number of times, effectively prevent a reference unit many
The drift of the reference current that reference unit performance degradation is caused after task, solves flash memory in prior art
The problem that reference current drifts about easily occurs, and then has reached to increase the effect of the reliability under flash memory is repeatedly read and write
Really.
Accompanying drawing explanation
The accompanying drawing of the part constituting the application is used for providing a further understanding of the present invention, and the present invention's is schematic real
Execute example and illustrate for explaining the present invention, being not intended that inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is the circuit diagram of the flash memory according to correlation technique；
Fig. 2 is the circuit diagram of flash memory according to embodiments of the present invention；
Fig. 3 is the flow chart of determination method according to a first embodiment of the present invention；And
Fig. 4 is the flow chart of determination method according to a second embodiment of the present invention.
Detailed description of the invention
It should be noted that in the case of not conflicting, the embodiment in the application and the feature in embodiment can phases
Combination mutually.Describe the present invention below with reference to the accompanying drawings and in conjunction with the embodiments in detail.
Embodiments provide a kind of flash memory, the flash memory below embodiment of the present invention provided
It is specifically introduced:
Fig. 2 is the circuit diagram of flash memory according to embodiments of the present invention, as in figure 2 it is shown, the embodiment of the present invention
Flash memory includes memory element CA, set of reference cells CR, the first switch unit A, comparing unit SA and control
Unit B.
Specifically, set of reference cells CRIt is made up of two or more reference units, each reference unit therein
Specifications parameter the most identical, each reference unit is in same state before flash memory dispatches from the factory, it is assumed that reference unit
Group CRIn reference unit respectively be the first reference unit CR1, the second reference unit CR2... m is with reference to single
Unit CRm, the reference unit being connected by the first switch unit A and comparing unit SA is the first reference unit CR1,
Then the structure of the flash memory of the embodiment of the present invention consists of:
The input of the first switch unit A and the first reference unit CR1Drain electrode, the second reference unit CR2Leakage
Pole ... m reference unit CRmDrain electrode be all connected, the outfan of the first switch unit A is through resistance RRConnect
To power Vcc, an input of comparing unit SA is connected to outfan and the resistance R of the first switch unit ARIt
Between, it is achieved by the reference current I of reference unitrefAccess an input of comparing unit SA；Memory element CA's
Drain electrode is through resistance RABeing connected to power Vcc, another input of comparing unit SA is connected to memory element CAWith
Resistance RABetween, it is achieved by memory element CAElectric current IcAccess another input of comparing unit SA；Control
The control end of unit B and the first switch unit A and the first reference unit CR1All it is connected, when control unit B is to obtaining
The the first reference unit C gotR1Cycle of operation number contrast with preset times, obtain the first reference unit CR1
Cycle of operation number more than or equal to preset times time, control unit B transmitting control commands to the first switch unit A with
Make the second input and the first reference unit C of comparing unit SAR1Disconnect, make the of comparing unit SA simultaneously
Two inputs are connected to a cycle of operation number less than on the reference unit of preset times.For convenience, can arrange
When flash memory is in init state, the reference unit used is the first reference unit CR1, then first
Reference unit CR1After certain preset times is arrived in work, control the first switch unit and switch to the second reference unit
CR2, at the second reference unit CR2After certain preset times is arrived in work, control the first switch unit and switch to the 3rd
Reference unit, the like, until last standby reference unit CRm, the first switch unit plays the work of selection
With, under the effect of the control logic of control unit, it is ensured that the bit line of only one of which reference unit turns on (i.e., every time
The drain electrode of only one of which reference unit is connected with comparing unit), produce reference current, and remaining reference unit is all located
In off position, prevent the performance degradation that the applying bias on bit line may cause.
More specifically, the first switch unit A can be multiplexer, comparing unit SA can be comparator, when
Control unit B sends control instruction to after the first switch unit A, can trigger the first switch unit A and performs and control
Instruct corresponding action, if controlling the second input and the first reference unit C of comparing unit SAR1Disconnect,
And with the second reference unit CR2Set up and connect, then the first switch unit A performs corresponding action, disconnects comparing unit
The input of SA and the first reference unit CR1Drain electrode between line, and make the input and of comparing unit SA
Two reference unit CR2Drain electrode between set up and connect, it is assumed that the normal phase input end of comparing unit SA is with the first switching singly
The outfan of unit A is connected, the negative-phase input of comparing unit SA and memory element CADrain electrode be connected, then than
Relatively cell S A is respectively from memory element CADrain electrode and the second reference unit CR2Drain electrode read current Ic and Iref,
Both are compared to each other, if Ic > Iref, then the output end vo output logic 1 of SA；If Ic < Iref, then SA
Output end vo output logical zero, thus realize flash memory and utilize the second reference unit CR2It is written and read operation；With
Sample, accesses in flash memory circuit if controlling the 3rd reference unit, the most correspondingly by the drain electrode of the 3rd reference unit with
One input of comparing unit SA couples together.
By arranging two or more multiple reference unit in flash memory, then to comparing unit phase
Whether the cycle of operation number of the first reference unit connected reaches certain preset times judges, and in the first reference
When the cycle of operation number of unit reaches certain preset times, control second input and first of comparing unit with reference to single
Unit disconnects, and controls the second input of comparing unit and the second reference unit is connected, it is achieved that in flash memory
The reference unit that reservoir is mated works and switches to standby reference unit after certain number of times, effectively prevent one
After the many tasks of individual reference unit, the drift of the reference current that reference unit performance degradation is caused, solves prior art
Easily there is the problem that reference current drifts about in middle flash memory, and then has reached increase flash memory and repeatedly read and write down
Reliability and the effect in service life.
Further, control unit B can include enumerator, and with the control of the count results for reading enumerator
Device, wherein, enumerator determines this for the marking signal (that is, enabling signal) according to certain reference unit grid
The cycle of operation number of individual reference unit, the count results that controller reads from enumerator is corresponding reference unit
Cycle of operation number；It addition, in flash memory, every task of comparator all examines unit along with Radix Satyrii nepalensis
Call, so the marking signal of comparator work can also be counted, can be by these marking signals be carried out
Counting determines the work times of reference unit.
Further, the control unit of embodiment of the present invention flash memory is except the bit line (leakage to each reference unit
Pole) direction is controlled, so that suitably reference unit accesses outside the operating circuit of flash memory, it is also possible to pass through
Wordline (grid) direction of each reference unit is controlled by circuits below form:
The multiplexer that form one: the first switch unit A lock uses can include drain decoding circuit and gate decoder
Circuit, wherein, the input of drain electrode decoding circuit is connected with the drain electrode of each reference unit, drain electrode decoding circuit
Outfan is connected in comparator, illustrates: the first input end of drain electrode decoding circuit is as the first switch unit
The drain electrode of first input end and the first reference unit is connected, and the second input of drain electrode decoding circuit is as the first switching
Second input of unit and the drain electrode of the second reference unit are connected, and the outfan of drain electrode decoding circuit is cut as first
Second input of the outfan and comparator that change unit is connected；The outfan of gate decoder circuit is single with each reference
The grid of unit is connected, and illustrates: the first outfan of gate decoder circuit and the grid of the first reference unit are connected
Connecing, the second outfan of gate decoder circuit and the grid of the second reference unit are connected, the 3rd of gate decoder circuit
The grid of outfan and the 3rd reference unit is connected, and the first input end of gate decoder circuit is unsettled or ground connection, grid
Second input of decoding circuit connects predeterminated voltage, and wherein, the 3rd reference unit is arbitrary in multiple reference unit
Reference unit, and the 3rd reference unit and the first reference unit, the second reference unit be different reference units.
When control unit by the drain electrode decoding circuit of the first switch unit control certain reference unit be connected with comparator time,
This is access in the reference unit operationally wordline of comparator and adds default voltage (i.e. on grid), due at electricity
Lu Zhong, shares same wordline with the reference unit of a line, so the reference unit wordline not accessing comparator also can add
Same voltage, though so not resulting in mistake in logic, it is possible that to the reference unit not accessing comparator
Interfere, in such cases, can be by control unit by the drain electrode decoding circuit grid potential to each reference unit
It is controlled, specifically, controls the first input end of control gate decoding circuit and the first output of gate decoder circuit
End is all connected with the 3rd outfan, and the second input of control gate decoding circuit and the second of gate decoder circuit
Outfan is connected.
The preferred embodiment is by arranging gate decoder circuit, with the wordline to each reference unit in flash memory
Current potential is controlled, it is achieved that reduces circuit interference, strengthens the reliability of each stand-by unit of flash memory.
Form two: flash memory also includes the second switch unit, first input end outfan is unsettled or ground connection, and second
Input connects predeterminated voltage.It is connected with comparator when control unit controls certain reference unit by the first switch unit
When connecing, this is access in the reference unit operationally wordline of comparator and adds default voltage (i.e. on grid), by
In in circuit, share same wordline with the reference unit of a line, so not accessing the reference unit wordline of comparator
Also same voltage can be added, though so not resulting in mistake in logic, it is possible that to the ginseng not accessing comparator
Examine unit to interfere, in such cases, can be by control unit by second switch unit grid to each reference unit
Electrode potential is controlled, specifically, it is assumed that the first outfan of the second switch unit and the grid phase of the first reference unit
Connecting, the second outfan of the second switch unit and the grid of the second reference unit be connected, the of the second switch unit
The grid of three outfans and the 3rd reference unit is connected, and the reference unit accessing comparator is the second reference unit,
Then control unit controls the first input end of the second switch unit and the first outfan of the second switch unit and the 3rd output
End is all connected, and the second outfan of the second input and the second switch unit controlling the second switch unit disconnects even
Connect.
By arranging the second switch unit in flash memory, it is controlled with the word line potential to each reference unit,
Achieve reduction circuit interference, strengthen the reliability of each stand-by unit of flash memory.
The embodiment of the present invention additionally provides a kind of determination method of memory reference unit, and this determines that method can be led to
Any one flash memory that crossing embodiment of the present invention foregoing is provided performs, below to embodiment of the present invention institute
The determination method provided is specifically addressed:
Fig. 3 is the flow chart of determination method according to a first embodiment of the present invention, as it is shown on figure 3, with flash memory
The reference unit used when being written and read operation illustrates embodiment of the present invention quick flashing as a example by being the first reference unit
The determination method of memory reference unit, specifically includes following steps:
Obtain the cycle of operation number of the first reference unit；
Judge that whether the cycle of operation number of the first reference unit is less than preset times；And
When judging the cycle of operation number of the first reference unit more than or equal to preset times, control comparing unit and the
One reference unit disconnects, and controls comparing unit simultaneously and is connected to the reference less than preset times of the cycle of operation number
On unit (the hereinafter referred to as second reference unit).
By arranging two or more multiple reference unit in flash memory, then to comparing unit phase
Whether the cycle of operation number of the first reference unit connected reaches certain preset times judges, and in the first reference
When the cycle of operation number of unit reaches certain preset times, control second input and first of comparing unit with reference to single
Unit disconnects, and controls the second input of comparing unit and the second reference unit is connected, it is achieved that in flash memory
The reference unit that reservoir is mated works and switches to standby reference unit after certain number of times, effectively prevent one
After the many tasks of individual reference unit, the drift of the reference current that reference unit performance degradation is caused, solves prior art
Easily there is the problem that reference current drifts about in middle flash memory, and then has reached increase flash memory and repeatedly read and write down
Reliability and the effect in service life.
It is possible to further use enumerator to call the marking signal of certain reference unit to count, then to meter
The count results of number device is read out obtaining the cycle of operation number of this reference unit, i.e. obtains this reference unit
Work times.Wherein, before the work times of this reference unit is counted, need based on counting
Number device is zeroed out processing.For convenience, can after the first reference unit works certain preset times,
Control comparing unit and be connected to the second reference unit, the count results of enumerator is reset, then in the second reference simultaneously
Cell operation, to after certain preset times, controls comparing unit and is connected to the 3rd reference unit, the like, directly
To the reference unit that last is standby.
Fig. 4 is the flow chart of determination method according to a second embodiment of the present invention, and as shown in Figure 4, the present invention second is real
Executing the determination method of example compared with the determination method of first embodiment of the invention, the two difference is: work as flash memory
In last reference unit work times reach set maximum after, switch to initial first reference unit,
Then whole process is repeated.So ensure that the several reference units in flash memory can use uniformly, reaches equally
To the effect improving the stability of reference current, the reliability increased under flash memory is repeatedly read and write.
Preferably, when the cycle of operation number judging the first reference unit is more than or equal to preset times, the present invention is real
The determination method executing example also includes: control that the grid of reference unit that is not connected with comparing unit is unsettled or ground connection.
When flash memory is written and read operation, it is access in the reference unit operationally wordline of comparing unit (i.e.
On grid) add default voltage, owing in circuit, sharing same wordline with the reference unit of a line, so not
The reference unit wordline accessing comparing unit also can add same voltage, though so not resulting in mistake in logic, but
Be possible to the reference unit to not accessing comparing unit interfere, in such cases, by will not with comparing unit
The grid of the reference unit being connected is unsettled or ground connection, is controlled with the word line potential to each reference unit, it is achieved
The interference of reduction circuit, strengthens the reliability of each stand-by unit of flash memory.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for the skill of this area
For art personnel, the present invention can have various modifications and variations.All within the spirit and principles in the present invention, made
Any modification, equivalent substitution and improvement etc., should be included within the scope of the present invention.
Claims (6)
1. a flash memory, it is characterised in that including:
Memory element；
Multiple reference units；
First switch unit, described first switch unit is all connected with the plurality of reference unit；
Comparing unit, the first input end of described comparing unit is connected with described memory element, described the most single
Second input of unit is connected by described first switch unit and the first reference unit, wherein, and described first
Reference unit is the arbitrary reference unit in the plurality of reference unit；And
Control unit, is all connected with described first reference unit and described first switch unit, is used for obtaining institute
State the cycle of operation number of the first reference unit, and be more than or equal at the cycle of operation number of described first reference unit
During preset times, controlled second input and described first of described comparing unit by described first switch unit
Reference unit disconnects, and controls the second input of described comparing unit and the second reference unit is connected,
Wherein, described second reference unit is the arbitrary reference unit in the plurality of reference unit, and described second
Reference unit is different reference units from described first reference unit, the cycle of operation of described second reference unit
Number is less than described preset times,
Wherein, described control unit includes:
Enumerator, for calling the marking signal of described first reference unit to count；And
Controller, is connected with described enumerator, and the count results for reading described enumerator obtains described the
The cycle of operation number of one reference unit.
Flash memory the most according to claim 1, it is characterised in that the first input of described first switch unit
End is connected with described first reference unit, the second input of described first switch unit and described second reference
Unit is connected, and the second input of described comparing unit is connected with the outfan of described first switch unit,
Wherein,
The outfan that described control unit controls described first switch unit is defeated with the first of described first switch unit
Enter end to disconnect, so that the second input of described comparing unit disconnects with described first reference unit；
And
The outfan that described control unit controls described first switch unit is defeated with the second of described first switch unit
Enter end to be connected, so that the second input of described comparing unit is connected with described second reference unit.
Flash memory the most according to claim 2, it is characterised in that described first switch unit includes:
Drain electrode decoding circuit, the first input end of described drain electrode decoding circuit is as the of described first switch unit
One input is connected with the drain electrode of described first reference unit, and the second input of described drain electrode decoding circuit is made
It is connected with the drain electrode of described second reference unit for the second input of described first switch unit, described drain electrode
The outfan of the decoding circuit outfan as described first switch unit and the second input of described comparing unit
It is connected；And
The grid of gate decoder circuit, the first outfan of described gate decoder circuit and described first reference unit
Being connected, the second outfan of described gate decoder circuit is connected with the grid of described second reference unit, institute
The grid of the 3rd outfan and the 3rd reference unit of stating gate decoder circuit is connected, described gate decoder circuit
First input end is unsettled or ground connection, the second input of described gate decoder circuit connects predeterminated voltage, wherein,
Described 3rd reference unit is the arbitrary reference unit in the plurality of reference unit, and described 3rd reference is single
First and described first reference unit, described second reference unit are different reference units,
When the cycle of operation number of described first reference unit is more than or equal to described preset times, described control list
Unit is additionally operable to the first outfan of first input end and the described gate decoder circuit controlling described gate decoder circuit
All it is connected with the 3rd outfan, and controls the second input of described gate decoder circuit and described gate decoder
Second outfan of circuit is connected.
Flash memory the most according to claim 1, it is characterised in that the input of described first switch unit with
The drain electrode of the plurality of reference unit is all connected, and described flash memory also includes:
The grid of the second switch unit, the first outfan of described second switch unit and described first reference unit
Being connected, the second outfan of described second switch unit is connected with the grid of described second reference unit, institute
The grid of the 3rd outfan and the 3rd reference unit of stating the second switch unit is connected, described second switch unit
First input end is unsettled or ground connection, the second input of described second switch unit connects predeterminated voltage, wherein,
Described 3rd reference unit is the arbitrary reference unit in the plurality of reference unit, and described 3rd reference is single
First and described first reference unit, described second reference unit are different reference units,
When the cycle of operation number of described first reference unit is more than or equal to described preset times, described control list
Unit controls the first input end of described second switch unit and first outfan and the 3rd of described second switch unit
Outfan is all connected, and controls the second input of described second switch unit and described second switch unit
Second outfan is connected.
5. the determination method of a memory reference unit, it is characterised in that flash memory include comparing unit and
Multiple reference units, wherein it is determined that method includes:
Obtaining the cycle of operation number of the first reference unit, wherein, described first reference unit is the plurality of reference
The reference unit being connected with described comparing unit in unit；
Judge that whether the cycle of operation number of described first reference unit is less than preset times；And
When the cycle of operation number judging described first reference unit is more than or equal to described preset times, control
Described comparing unit disconnects with described first reference unit, and controls described comparing unit and second with reference to single
Unit is connected, and wherein, described second reference unit is the arbitrary reference unit in the plurality of reference unit, and
And described second reference unit is different reference units from described first reference unit, described second reference unit
Cycle of operation number less than described preset times,
Wherein, the cycle of operation number obtaining the first reference unit includes:
Call the marking signal of described first reference unit to count；And
Read the count results to described marking signal and obtain the cycle of operation number of described first reference unit.
The most according to claim 5 determine method, it is characterised in that in the fortune judging described first reference unit
When line period number is more than or equal to described preset times, described determine that method also includes:
Control that the grid of described first reference unit is unsettled or ground connection；And
Controlling that the grid of the 3rd reference unit is unsettled or ground connection, wherein, described 3rd reference unit is the plurality of
Arbitrary reference unit in reference unit, and described 3rd reference unit and described first reference unit, described
Second reference unit is different reference units.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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