[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

CN103545207A - 半导体器件制造方法 - Google Patents

半导体器件制造方法 Download PDF

Info

Publication number
CN103545207A
CN103545207A CN201210239480.8A CN201210239480A CN103545207A CN 103545207 A CN103545207 A CN 103545207A CN 201210239480 A CN201210239480 A CN 201210239480A CN 103545207 A CN103545207 A CN 103545207A
Authority
CN
China
Prior art keywords
source region
layer
region
forming
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201210239480.8A
Other languages
English (en)
Other versions
CN103545207B (zh
Inventor
尹海洲
朱慧珑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN201210239480.8A priority Critical patent/CN103545207B/zh
Priority to PCT/CN2012/079454 priority patent/WO2014008691A1/zh
Priority to US14/413,697 priority patent/US20150171186A1/en
Publication of CN103545207A publication Critical patent/CN103545207A/zh
Application granted granted Critical
Publication of CN103545207B publication Critical patent/CN103545207B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having non-planar bodies, e.g. having recessed gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • H10D64/259—Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明公开了一种半导体器件制造方法，包括：在衬底上形成栅极堆叠结构以及栅极侧墙，在栅极堆叠结构以及栅极侧墙两侧衬底中分别形成源区和漏区；在漏区上选择性形成阻挡层，其中阻挡层覆盖漏区并且暴露源区；在暴露的源区上外延形成提升源区；去除阻挡层。依照本发明的半导体器件制造方法，选择性地仅在源区一侧形成提升源区从而构成非对称器件结构，针对性减小源区一侧寄生电阻以及漏极一侧寄生电容，有效提高了器件性能。

Description

半导体器件制造方法
技术领域
本发明涉及半导体集成电路制造领域，更具体地，涉及一种半导体器件制造方法尤其是具有非对称源漏结构的MOSFET的制造方法。
背景技术
随着集成电路工艺持续发展，特别是器件尺寸不断等比例缩减，传统的MOSFET中各种寄生效应变得越来越突出。例如源漏寄生电阻在长沟道时远小于沟道区电阻而可以忽略，但是随着器件等比例缩小、沟道区本征电阻减小，源漏区电阻特别是接触电阻随着尺寸减小而迅速增加，使得等效工作电压下降。此外，源漏与栅极之间还存在寄生电容，其中包括由于边缘电场效应，栅极电力线穿过侧墙、层间介质等进入源漏区而引起的寄生电容，这些寄生电容可以导致器件响应速度恶化，降低器件高频性能。因此需要减小上述这些寄生电阻和寄生电容。
现有技术中对于减小寄生效应采取的措施包括在源漏区中/上均形成金属硅化物或者均提升源漏来同时减小源区、漏区的寄生电阻，还包括精确控制栅极高度、栅极侧墙线条、栅极侧墙组分以减少寄生电容。
然而上述这些方法在源区和漏区两侧上处理工艺都是相同的，也即形成的器件结构是对称的。并且，提升源漏由于减少了电力线由栅极穿过侧墙至源漏的距离，会增加边缘寄生电容。实际上，栅极与漏极之间的覆盖电容是跨接在输入端栅极与输出端漏极之间的密勒(Miller)电容，在反相放大电路中会因为放大器的放大作用而使得等效到输入端的电容值会扩大1+K倍(K是该级放大电路电压放大倍数)，因此由于这种Miller效应使得漏极一侧寄生电容对于器件性能的影响要大于源极一侧寄生电容的影响。此外，由于在器件开启情况下，源端寄生电阻使源端电压发生变化，从而改变栅源电压，对NMOS来说降低了栅源电压，对PMOS来说降低了栅源电压的绝对值。这将增大沟道电阻、减少沟道电荷，从而降低驱动电流、影响器件性能。相对的，漏端寄生电阻对漏端电压的影响不会影响到栅源电压，对器件性能影响较小。因此总的来说，在源极一侧寄生电阻对于器件性能的影响则要大于漏极一侧寄生电阻的影响。
因此，现有技术中具有对称结构的MOSFET并未考虑到上述源、漏区之间寄生效应的差异，制约器件性能进一步提高。
发明内容
有鉴于此，本发明的目的在于提供一种半导体器件制造方法尤其是具有非对称源漏结构的MOSFET的制造方法，以针对性减小源区一侧寄生电阻以及漏极一侧寄生电容。
实现本发明的上述目的，是通过提供一种半导体器件制造方法，包括：在衬底上形成栅极堆叠结构以及栅极侧墙，在栅极堆叠结构以及栅极侧墙两侧衬底中分别形成源区和漏区；在漏区上选择性形成阻挡层，其中阻挡层覆盖漏区并且暴露源区；在暴露的源区上外延形成提升源区；去除阻挡层。
其中，阻挡层材料与衬底材料不同。
其中，在漏区上选择性形成阻挡层的步骤进一步包括；在整个器件上形成阻挡材料层；在阻挡材料层上形成光刻胶图形，覆盖漏区上的阻挡材料层并且暴露源区上的阻挡材料层；刻蚀暴露的源区上的阻挡材料层，仅留下漏区上的部分阻挡材料层而构成阻挡层；去除光刻胶图形。
其中，提升源区包括Si、SiGe、Si：C及其组合。
其中，在形成提升源区的同时原位掺杂，或者在形成提升源区之后注入掺杂，使得提升源区与源区导电类型相同。
其中，去除阻挡层之后还包括：在漏区和提升源区上形成金属硅化物；在整个器件上形成层间介质层；刻蚀层间介质层直至暴露金属硅化物，形成源漏接触孔；在源漏接触孔中沉积形成源漏接触塞。
其中，栅极堆叠结构为假栅极堆叠结构，包括氧化硅的垫氧化层以及多晶硅、非晶硅、氧化硅的假栅极填充层。
其中，在形成层间介质之后，刻蚀层间介质之前还可包括：平坦化层间介质层以及假栅极堆叠结构直至暴露栅极填充层；去除栅极填充层，形成栅极沟槽；栅极沟槽中形成功函数调节层和电阻调节层。
其中，源区和/或漏区包括轻掺杂的延伸区以及重掺杂区。
其中，源区与漏区对称。
依照本发明的半导体器件制造方法，选择性地仅在源区一侧形成提升源区从而构成非对称器件结构，针对性减小源区一侧寄生电阻以及漏极一侧寄生电容，有效提高了器件性能。
附图说明
以下参照附图来详细说明本发明的技术方案，其中：
图1为根据本发明的半导体器件制造方法的流程图；以及
图2至图8为根据本发明的半导体器件制造方法各步骤的剖视图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果。需要指出的是，类似的附图标记表示类似的结构，本申请中所用的术语“第一”、“第二”、“上”、“下”、“厚”、“薄”等等可用于修饰各种器件结构。这些修饰除非特别说明并非暗示所修饰器件结构的空间、次序或层级关系。
参照图1以及图2，在衬底上形成栅极堆叠结构以及栅极侧墙，在栅极堆叠结构以及栅极侧墙两侧衬底中分别形成源区和漏区。
提供衬底1，其材质可以是(体)Si(例如单晶Si晶片)、SOI、GeOI(绝缘体上Ge)，也可以是其他化合物半导体，例如GaAs、SiGe、GeSn、InP、InSb、GaN等等。优选地，衬底1选用体Si或SOI，以便与CMOS工艺兼容。优选地，刻蚀衬底1形成浅沟槽并随后沉积填充氧化硅等绝缘材料而形成浅沟槽隔离(STI)1A，STI 1A包围的衬底1区域构成器件的有源区。
采用LPCVD、PECVD、HDPCVD、MOCVD、MBE、ALD、蒸发、溅射等常规沉积方法，在有源区上依次沉积并且随后刻蚀形成栅极绝缘层2A、栅极填充层2B、以及优选地栅极盖层2C。当栅极堆叠结构采用后栅工艺时，也即用作假栅极堆叠结构，假栅极绝缘层2A是氧化硅的垫氧化层，假栅极填充层2B是多晶硅、非晶硅、甚至可以是氧化硅，随后工艺中刻蚀去除假栅极堆叠结构形成栅极沟槽，在栅极沟槽中依次填充高k材料的栅极绝缘层以及金属材料的栅极填充层，栅极绝缘层2A是高k材料，包括但不限于氮化物(例如SiN、AlN、TiN)、金属氧化物(主要为副族和镧系金属元素氧化物，例如Al2O3、Ta2O5、TiO2、ZnO、ZrO2、HfO2、CeO2、Y2O3、La2O3)、钙钛矿相氧化物(例如PbZrxTi1-xO3(PZT)、BaxSr1-xTiO3(BST))；栅极填充层2B是金属、金属氮化物及其组合，其中金属包括Al、Ti、Cu、Mo、W、Ta以用作栅极填充层(电阻调节层)，金属氮化物包括TiN、TaN以用作功函数调节层；栅极盖层2C是氮化硅，用作栅极刻蚀的硬掩模。栅极绝缘层包围了栅极填充层的底部以及侧面(未示出)。值得注意的是，虽然以下本发明实施例中针对的是后栅工艺也即图2中的栅极堆叠结构是假栅极堆叠结构，但是本发明也可以采用前栅工艺。前栅工艺栅极堆栈结构与填充金属种类与后栅工艺不同。由于目前主流工艺是后栅工艺，此处不详细描述。
可选地，执行第一次源漏注入，在栅极绝缘层2A、栅极填充层2B、栅极盖层2C构成的栅极堆叠结构2两侧的衬底1中对称地以较低能量和剂量注入B、P、Ga、Al、N等及其组合的杂质形成轻掺杂源区3LS以及轻掺杂漏区3LD(这些轻掺杂源漏区也即源漏延伸区构成LDD结构，可以抑制热电子效应)。注入剂量和能量依照结深以及导电类型和浓度大小需要而合理设定。可以采用退火以激活注入的杂质。
在栅极绝缘层2A、栅极填充层2B、栅极盖层2C构成的栅极堆叠结构2的两侧通过沉积后刻蚀形成了包括氮化硅、氧化硅、氮氧化硅、类金刚石无定形碳(DLC)及其组合的材质的栅极侧墙4。
可选地，执行第二次源漏注入，在栅极侧墙4两侧的衬底1(源区3LS、漏区3LD)中对称地以较高能量和剂量注入相同导电类型的杂质以形成重掺杂源区3HS以及重掺杂漏区3HD。可以再次采用退火以激活注入的杂质。
参照图1以及图3至图6，在漏区上选择性形成阻挡层，覆盖了漏区一侧并且暴露了源区一侧。
参照图3，在整个器件上沉积阻挡材料层5。例如通过LPCVD、PECVD、HDPCVD、MBE、ALD等常规方法，在STI 1A、源区3HS、栅极侧墙4、栅极盖层2C、漏区3HD上沉积阻挡材料层5。阻挡材料层5的材质包括氧化硅、氮化硅、氮氧化硅及其组合，可以是单层也可以是这些材料的复合层叠结构。原则上，阻挡层材料可以是一切与源区、漏区不同的材料。为了保证栅极源端侧墙以及栅极盖层(刻蚀停止层)2C不被刻蚀，应保证阻挡材料5与侧墙4以及刻蚀停止层2C的材料均不同。例如，衬底1、源区、漏区为Si，侧墙4、盖层2C为SiN时，阻挡材料层5可以是氧化硅或氮氧化硅。阻挡材料层5用作后续外延形成提升源区的阻挡材料，被该阻挡层覆盖的区域上将无法外延生长衬底/源漏区材料。阻挡材料层5的厚度依照外延工艺需要而设定，例如是5～30nm。
参照图4，在阻挡材料层5上形成暴露了源区一侧的掩模图形6。在阻挡材料层5上旋涂、喷涂、丝网印刷例如是光刻胶的软掩模图形，曝光、显影之后，去除了源区一侧的光刻胶，而仅在漏区一侧保留下光刻胶图形6。其中(光刻胶)掩模图形6可以如图4所示严格以器件中轴线为界而占据了漏区的全部和栅极堆叠结构的一半，但是也可以采取其他形式，只要暴露出源区一侧并且覆盖漏区一侧，例如光刻胶图形6的左边界位于左侧栅极侧墙4左侧面的右方并且位于右侧栅极侧墙4右侧面的左方，光刻胶图形6的右边界位于漏区3HD右侧面的右方。
参照图5，刻蚀暴露的阻挡材料层5，直至露出源区3HS(以及栅极侧墙4、栅极盖层2C)。刻蚀方法依照阻挡材料层5的材质不同而合理选择，可以是干法刻蚀或湿法刻蚀。干法刻蚀包括等离子体刻蚀、反应离子刻蚀等，刻蚀气体可以采用氟基气体(碳氟基气体，例如CF4、CHF3、CH3F、CH2F2；NF3；SF6)、Cl2/HCl、Br2/HBr、氧气、稀有气体(Ar、He)及其组合。湿法刻蚀的刻蚀液可以包括HF、HF：NH4F、H2O2、H2SO4、HNO3及其组合。刻蚀也可是是干法刻蚀和湿法刻蚀的组合，例如先干法后湿法，或者对于层叠的阻挡材料层5采用不同的干法刻蚀组合、湿法刻蚀组合、或者干法与湿法刻蚀的组合。如前所述，阻挡材料5与侧墙4、刻蚀停止层2C的材料不同，因此在刻蚀过程中侧墙4、刻蚀停止层2C不会被刻蚀。
参照图6，去除掩模图形6，在漏区3HD一侧留下了阻挡层5D。去除光刻胶的方法可以是有机溶剂溶解、无机溶剂氧化、或者氧气等离子灰化等。
参照图1以及图7，在源区上外延生长提升源区。采用MBE、ALD、MOCVD等方法，在暴露的源区3HS上外延生长提升源区3RS。由于STI 1A、栅极侧墙4、栅极盖层2C以及阻挡层5D的材质均不同于衬底1/源区3HS的材质，因此外延仅发生在源区3HS上，因此也称为选择性外延。提升源区3RS的材质包括Si、SiGe、Si：C及其组合。优选地，采用SiGe、Si：C以向沟道区施加应力、提高沟道区载流子迁移率。优选地，在外延生长的同时，原位掺杂使得提升源区3RS具有与源区3HS相同的导电类型。可选地，在外延提升源区3RS之后，再次执行掺杂离子注入并随后退火以激活杂质，使得提升源区3RS具有与源区3HS相同的导电类型。此时，由于阻挡层5D的限制，漏区3HD上没有形成提升漏区，因此栅极2B的电力线不会额外穿入到提升漏区中而引起寄生电容增大，也即不形成提升漏区降低了漏区一侧的寄生电容。此外，源区一侧的提升源区3RS使得源区面积增大、掺杂浓度增大，寄生电阻减小，因此进一步提高了器件性能。
参照图1以及图8，去除阻挡层5D。依照阻挡层5D的材质，采用与图5所示步骤相同的工艺，去除剩余的阻挡层5D。随后，可以完成后续MOSFET制造工艺(未示出)，例如包括在提升源区3RS与漏区3HD上形成金属硅化物以进一步降低接触电阻，在整个器件上形成层间介质层(ILD)，刻蚀ILD直至暴露金属硅化物而形成源漏接触孔，在源漏接触孔中沉积金属/金属氮化物形成源漏接触塞等。当堆栈结构采用后栅工艺时，在形成层间介质之后，刻蚀层间介质之前还可包括：平坦化层间介质层以及假栅极堆叠结构直至暴露栅极填充层；去除栅极填充层，形成栅极沟槽；栅极沟槽中形成功函数调节层和电阻调节层。其中，功函数调节层与电阻调节层金属如前所述。
依照本发明的半导体器件制造方法，选择性地仅在源区一侧形成提升源区从而构成非对称器件结构，针对性减小源区一侧寄生电阻以及漏极一侧寄生电容，有效提高了器件性能。
尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员可以知晓无需脱离本发明范围而对形成器件结构的方法做出各种合适的改变和等价方式。此外，由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此，本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例，而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims (10)

1.一种半导体器件制造方法，包括：
在衬底上形成栅极堆叠结构以及栅极侧墙，在栅极堆叠结构以及栅极侧墙两侧衬底中分别形成源区和漏区；
在漏区上选择性形成阻挡层，其中阻挡层覆盖漏区并且暴露源区；
在暴露的源区上外延形成提升源区；
去除阻挡层。
2.如权利要求1的半导体器件制造方法，其中，阻挡层材料与衬底材料不同。
3.如权利要求1的半导体器件制造方法，其中，在漏区上选择性形成阻挡层的步骤进一步包括：
在整个器件上形成阻挡材料层；
在阻挡材料层上形成光刻胶图形，覆盖漏区上的阻挡材料层并且暴露源区上的阻挡材料层；
刻蚀暴露的源区上的阻挡材料层，仅留下漏区上的部分阻挡材料层而构成阻挡层；
去除光刻胶图形。
4.如权利要求1的半导体器件制造方法，其中，提升源区包括Si、SiGe、Si：C及其组合。
5.如权利要求1的半导体器件制造方法，其中，在形成提升源区的同时原位掺杂，或者在形成提升源区之后注入掺杂，使得提升源区与源区导电类型相同。
6.如权利要求1的半导体器件制造方法，其中，去除阻挡层之后还包括：
在漏区和提升源区上形成金属硅化物；
在整个器件上形成层间介质层；
刻蚀层间介质层直至暴露金属硅化物，形成源漏接触孔；
在源漏接触孔中沉积形成源漏接触塞。
7.如权利要求6的半导体器件制造方法，其中，栅极堆叠结构为假栅极堆叠结构，包括氧化硅的垫氧化层以及多晶硅、非晶硅、氧化硅的假栅极填充层。
8.如权利要求7所述的半导体器件制造方法，其中，在形成层间介质层之后，刻蚀层间介质层之前还包括：
平坦化层间介质层以及假栅极堆叠结构直至暴露假栅极填充层；
去除假栅极填充层，形成栅极沟槽；
栅极沟槽中形成功函数调节层和电阻调节层。
9.如权利要求1的半导体器件制造方法，其中，源区和/或漏区包括轻掺杂的延伸区以及重掺杂区。
10.如权利要求1的半导体器件制造方法，其中，源区与漏区对称。
CN201210239480.8A 2012-07-11 2012-07-11 半导体器件制造方法 Active CN103545207B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201210239480.8A CN103545207B (zh) 2012-07-11 2012-07-11 半导体器件制造方法
PCT/CN2012/079454 WO2014008691A1 (zh) 2012-07-11 2012-07-31 半导体器件制造方法
US14/413,697 US20150171186A1 (en) 2012-07-11 2012-07-31 Semiconductor device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210239480.8A CN103545207B (zh) 2012-07-11 2012-07-11 半导体器件制造方法

Publications (2)

Publication Number Publication Date
CN103545207A true CN103545207A (zh) 2014-01-29
CN103545207B CN103545207B (zh) 2017-07-11

Family

ID=49915344

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210239480.8A Active CN103545207B (zh) 2012-07-11 2012-07-11 半导体器件制造方法

Country Status (3)

Country Link
US (1) US20150171186A1 (zh)
CN (1) CN103545207B (zh)
WO (1) WO2014008691A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105280501A (zh) * 2014-06-13 2016-01-27 格罗方德半导体公司 用于晶体管装置的改良应力记忆技术

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10134459B2 (en) * 2015-02-03 2018-11-20 Globalfoundries Singapore Pte. Ltd. MRAM with metal-insulator-transition material
US9882125B2 (en) * 2015-02-11 2018-01-30 Globalfoundries Singapore Pte. Ltd. Selector device for a non-volatile memory cell
US9391204B1 (en) 2015-03-12 2016-07-12 International Business Machines Corporation Asymmetric FET
CN115763377A (zh) * 2022-11-23 2023-03-07 武汉新芯集成电路制造有限公司 半导体器件及其制造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090250772A1 (en) * 2008-04-08 2009-10-08 Botula Alan B Field effect transistor and method of manufacture
CN102487014A (zh) * 2010-12-03 2012-06-06 中国科学院微电子研究所 一种半导体结构及其制造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6506649B2 (en) * 2001-03-19 2003-01-14 International Business Machines Corporation Method for forming notch gate having self-aligned raised source/drain structure
US7459382B2 (en) * 2006-03-24 2008-12-02 International Business Machines Corporation Field effect device with reduced thickness gate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090250772A1 (en) * 2008-04-08 2009-10-08 Botula Alan B Field effect transistor and method of manufacture
CN102487014A (zh) * 2010-12-03 2012-06-06 中国科学院微电子研究所 一种半导体结构及其制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105280501A (zh) * 2014-06-13 2016-01-27 格罗方德半导体公司 用于晶体管装置的改良应力记忆技术

Also Published As

Publication number Publication date
US20150171186A1 (en) 2015-06-18
CN103545207B (zh) 2017-07-11
WO2014008691A1 (zh) 2014-01-16

Similar Documents

Publication Publication Date Title
KR101901059B1 (ko) 상이한 핀 높이를 갖는 핀펫을 형성하는 기구
US8779475B2 (en) Semiconductor device and method of manufacturing the same
CN103762236B (zh) 集成电路组件及其制造方法
CN103545188B (zh) 半导体器件制造方法
US20130087833A1 (en) Semiconductor device and method of manufacturing the same
US20110079856A1 (en) Strained structure of semiconductor device
US9385212B2 (en) Method for manufacturing semiconductor device
CN103545208B (zh) 半导体器件制造方法
US9640660B2 (en) Asymmetrical FinFET structure and method of manufacturing same
CN103578991B (zh) 半导体器件制造方法
US9576802B2 (en) Semiconductor device and method for manufacturing the same
CN103545207A (zh) 半导体器件制造方法
CN107785314B (zh) 半导体器件的形成方法
US20090152670A1 (en) Semiconductor device and method of fabricating the same
US8703567B2 (en) Method for manufacturing a semiconductor device
TW201318073A (zh) 具有鰭狀結構之場效電晶體的結構及其製作方法
CN102842614B (zh) 半导体器件及其制造方法
US20120261674A1 (en) Semiconductor device and method for forming the same
CN104347704B (zh) 隧穿场效应晶体管及其制造方法
CN106486370A (zh) 半导体器件的形成方法
CN106328706A (zh) 鳍式场效应晶体管的形成方法
CN103681844A (zh) 半导体器件及其制造方法
CN109003902B (zh) 一种半导体结构及其制备方法
CN106328531A (zh) 鳍式场效应晶体管的形成方法
CN109817524A (zh) 半导体器件及其形成方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant