CN103531621A - Non-punch-through type insulated gate bipolar transistor with side polysilicon electrode trench - Google Patents
Non-punch-through type insulated gate bipolar transistor with side polysilicon electrode trench Download PDFInfo
- Publication number
- CN103531621A CN103531621A CN201310528583.0A CN201310528583A CN103531621A CN 103531621 A CN103531621 A CN 103531621A CN 201310528583 A CN201310528583 A CN 201310528583A CN 103531621 A CN103531621 A CN 103531621A
- Authority
- CN
- China
- Prior art keywords
- type
- electrode
- bipolar transistor
- trench
- silicon dioxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 67
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 64
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 66
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 33
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 33
- 238000001465 metallisation Methods 0.000 claims description 37
- 230000005684 electric field Effects 0.000 abstract description 22
- 238000009825 accumulation Methods 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 abstract description 3
- 210000000746 body region Anatomy 0.000 abstract 2
- 238000000034 method Methods 0.000 description 18
- 150000002500 ions Chemical class 0.000 description 11
- 238000000137 annealing Methods 0.000 description 10
- 238000005530 etching Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 6
- 238000002513 implantation Methods 0.000 description 6
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000004411 aluminium Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000005465 channeling Effects 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 230000004308 accommodation Effects 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000007521 mechanical polishing technique Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- -1 phosphonium ion Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000011946 reduction process Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H01L29/7397—
-
- H01L29/423—
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a non-punch-through type insulated gate bipolar transistor with a side polysilicon electrode trench, and relates to a bipolar transistor. The non-punch-through type insulated gate bipolar transistor is provided with a metalized collector electrode, a P type collector electrode region, an N- type drift region, a silicon dioxide side polysilicon oxide layer, a side polysilicon electrode, a metalized side polysilicon electrode, a P+ type body region, a metalized emitter electrode, an N+ type source region, a P type base region, a metalized gate electrode, a polysilicon gate electrode and a silicon dioxide gate oxide layer. A side polysilicon electrode technology is introduced in a traditional non-punch-through type insulated gate bipolar transistor with a trench; a mask plate does not need to be arranged and the junction depth of an original P+ type body region is expanded to be connected with the N- type drift region; a positive voltage is applied to Side-poly (the side polysilicon electrode trench), so that a reverse electric field can be generated, the shortcoming of electric field accumulation due to small bottom curve rate of the trench in Trench-NPT-IGBT (the non-punch-through type insulated gate bipolar transistor with the side polysilicon electrode trench) is overcome, and the peak electric field at the bottom of a trench gate is effectively reduced. Therefore, the non-punch-through type insulated gate bipolar transistor has the characteristics of higher breakdown voltage and lower threshold voltage.
Description
Technical field
The present invention relates to bipolar transistor, particularly relate to a kind of with side polysilicon electrode groove non-through insulated-gate bipolar transistor.
Background technology
The input impedance of the existing MOSFET of igbt (IGBT) is high, and driving power is little, and switching loss is low, has again the current density of bipolar power transistor large, the advantages such as saturation pressure reduction.As novel power semiconductor device, be widely used in field of power electronics.Yet owing to adopting trench gate art designs IGBT, in the little reason of the bottom of groove curved surface rate, electric field is easily concentrated in trench gate bottom, has made to limit the puncture voltage of trench gate type isolated-gate field effect transistor (IGFET).
Document [1] " Dual-Material-Gate Technique for Enhanced Transconductance and Breakdown Voltage of Trench Power MOSFETs " (author: Raghvendra S.Saxena, M.Jagadensh Kumar; Source: IEEE Transactions on Electron Devices, 2009, the 56th volume, the 517th page～the 522nd page) a kind of novel double-metal grid raceway groove thought proposed, original trench-gate is carried out to chemico-mechanical polishing reduction process, then deposit P+ type polysilicon, then carries out the deep groove in inside of grid groove, the metal of the little work function of deposit.The way of the document has improved puncture voltage and has reduced mutual conductance.
Document [2] " The Super-junction Insulated Gate Bipolar Transistor Optimization and Modeling " (author: Marina Antoniou, Florin Udrea, Friedhelm Bauer; Source: IEEE Transactions on Electron Devices, 2010, the 57th volume, the 594th page～the 600th page) proposed to utilize charge compensation principle, below P type base, introduce the P-pillar directly extend to N-type resilient coating, N-pillar and P-pillar under device blocking state are exhausted completely.The way of the document improves the doping content of N-type base, reduces quiescent dissipation, improves device breakdown withstand voltage simultaneously.
Document [3] " Trench gate IGBT structure with floating P region, " (author: Mengliang Qian, Zehong Li, Bo Zhang and Zhaoji Li; Source: Journal of Semiconductors, 2012, the 31st phase, 024003-1 page～the 024003-3 page) propose channel bottom and introduced collecting region, a P+ hole, avoid hole to enter P type tagma, played the effect of hole bypass, thereby weakened parasitic thyristor effect, the safety operation area of device is increased, and has also obtained superior hot properties.
But this way of document [1] need to increase a plurality of mask plates, also increased multiple tracks process simultaneously, grid groove is carried out to chemical Mechanical Polishing Technique also immature, wherein the required precision of secondary cutting is high, and difficulty is large, has also strengthened cut-in voltage.Doping content and breadth length ratio that document [2] will be controlled P-pillar and N-pillar accurately accurately due to needs realize charge compensation, and this is high to technological requirement, and need more thermal process.This kind of structural manufacturing process difficulty and cost are high, and dynamic avalanche ability.The technique that document [3] is realized P region needs multistep Implantation, and effect is bad aspect raising puncture voltage.
Non-through insulated-gate bipolar transistor (Trench-NPT-IGBT) device architecture, in traditional Trench-NPT-IGBT device, to introduce side polysilicon electrode (Side-poly), can improve the puncture voltage of this device, reduce the threshold voltage of its unlatching.
Summary of the invention
The object of the present invention is to provide a kind of with side polysilicon electrode groove non-through insulated-gate bipolar transistor.
The present invention is provided with metallization collector electrode, P type collector area, N-type drift region, silicon dioxide side polysilicon oxide layer, side polysilicon electrode, metallization side polysilicon electrode, P+ tagma, metallization emitter, N+ type source region, P type base, metallization grid, polygate electrodes and silicon dioxide gate oxide;
Described metallization collector electrode is positioned at the back side of P type collector area, and N-type drift region is positioned at the front of P type collector area; N+ type source region and P+ tagma are positioned at metallization emitter below side by side, and N+ type source region is connected with metallization emitter with P+ tagma, wherein, below P+ tagma, be directly connected with N-type drift region, between N+ type source region and N-type drift region across P type base; Polygate electrodes is located at top device and is positioned at a side of metallization emitter, and polygate electrodes side is surrounded by silicon dioxide gate oxide; The sidewall of silicon dioxide gate oxide contacts with N+ type source region, P type base and N-type drift region respectively, and silicon dioxide gate oxide bottom contacts with N-type drift region; Side polysilicon electrode is located at top device and is positioned at the opposite side of metallization emitter, and side polysilicon electrode side is surrounded by silicon dioxide side polysilicon oxide layer; The sidewall of silicon dioxide side polysilicon oxide layer contacts with P+ tagma, N-type drift region respectively, and silicon dioxide side polysilicon oxide layer bottom contacts with N-type drift region.
Side polysilicon electrode of the present invention is realized by cutting, oxidation, polycrystalline silicon deposition process.The extension of P+ tagma junction depth is injected ionic weight, injection length and annealing time by increase and is realized.When doing side polysilicon process, adopt and manufacture polygate electrodes to share a mask plate.
When growth oxide layer process intermediate ion injects, the atom of silicon chip surface is knocked into amorphous state, first generates buffer oxide film and reduces this destruction, and growth buffer oxide film has adopted dry oxygen-wet oxygen-dry oxygen three-step approach.
When Implantation, be easy to occur channeling effect, for fear of channeling effect, used off-axis injection, inclination angle is 7 °, in order to reduce Implantation direction, by chance arranges consistent probability with crystal orientation, injects the angle of rotating 30 ° of left and right.
When doing N+ type source region, with two step injection methods, because the diffusion coefficient of arsenic is little, advance the speed of diffusion slow, the knot of formation is also just more shallow, and the diffusion coefficient of phosphorus is large, the mixing of two kinds of ions is injected, and can reach the ohmic contact that surperficial high concentration is done emitter, also can reach enough junction depths.
Reverse ion is carried out while injecting in the back side of silicon chip, and B Implanted ion to be to form shallow P type collector area, because the device architecture that is over has been done on surface, deposit aluminium lamination, so the back side adds man-hour, can not adopt high annealing, and adopt 400 ° of process annealings.
The present invention introduces side polysilicon electrode Side-poly technology in traditional groove non-through insulated-gate bipolar transistor Trench-NPT-IGBT.Trench-NPT-IGBT of the present invention is by increase the technique of manufacturing together Side-poly in manufacturing grid (Gate) technical process, this technical process does not need to increase mask plate, the junction depth in original P+ tagma is expanded to N-type drift region and is joined simultaneously.At Side-poly, add positive voltage like this, just can form reversed electric field, solved the shortcoming of traditional Trench-NPT-IGBT electric field accumulation because channel bottom curved surface rate is little, effectively reduce the peak value electric field of trench-gate bottom.Trench-NPT-IGBT of the present invention has advantages of higher puncture voltage and lower threshold voltage.
Accompanying drawing explanation
Fig. 1 is the structural representation of the embodiment of the present invention.
Fig. 2 is that the present invention is with the etching technics figure of side polysilicon electrode groove and grid groove.
Fig. 3 is the present invention and the conventional groove non-through insulated-gate bipolar transistor Electric Field Distribution comparison diagram near communication channel when critical puncturing.In Fig. 3, abscissa is N-drift region thickness (μ m), and ordinate is electric field strength (V/cm); Curve a is conventional groove non-through insulated-gate bipolar transistor Electric Field Distribution curve; Curve b is the Electric Field Distribution curve of device of the present invention.
Embodiment
The present invention is further illustrated in connection with accompanying drawing for following examples.
Referring to Fig. 1 and 2, the embodiment of the present invention is provided with metallization collector electrode 1, P type collector area 2, N-type drift region 3, silicon dioxide side polysilicon oxide layer 4, side polysilicon electrode 5, metallization side polysilicon electrode 6, P+ tagma 7, metallization emitter 8, N+ type source region 9, P type base 10, metallization grid 11, polygate electrodes 12 and silicon dioxide gate oxide 13.
Described metallization collector electrode 1 is positioned at the back side of P type collector area 2, and N-type drift region 3 is positioned at the front of P type collector area 2; N+ type source region 9 and P+ tagma 7 are positioned at metallization emitter 8 belows side by side, N+ type source region 9 is connected with metallization emitter 8 with P+ tagma 7, wherein, 7 belows, P+ tagma are directly connected with N-type drift region 3, between N+ type source region 9 and N-type drift region 3 across P type base 10; Polygate electrodes 12 is located at top device and is positioned at a side of metallization emitter 8, and polygate electrodes 12 sides are surrounded by silicon dioxide gate oxide 13; The sidewall of silicon dioxide gate oxide 13 contacts with N+ type source region 9, P type base 10 and N-type drift region 3 respectively, and silicon dioxide gate oxide 13 bottoms contact with N-type drift region 3; Side polysilicon electrode 5 is located at top device and is positioned at the opposite side of metallization emitter 8, and side polysilicon electrode 5 sides are surrounded by silicon dioxide side polysilicon oxide layer 4; The sidewall of silicon dioxide side polysilicon oxide layer 4 contacts with P+ tagma 7, N-type drift region 3 respectively, and silicon dioxide side polysilicon oxide layer 4 bottoms contact with N-type drift region 3.
When growth oxide layer process intermediate ion injects, the atom of silicon chip surface is knocked into amorphous state, first generates buffer oxide film and reduces this destruction, and growth buffer oxide film has adopted dry oxygen-wet oxygen-dry oxygen three-step approach.
When Implantation, be easy to occur channeling effect, for fear of channeling effect, used off-axis injection, inclination angle is 7 °, in order to reduce Implantation direction, by chance arranges consistent probability with crystal orientation, injects the angle of rotating 30 ° of left and right.
When doing N+ type source region 9, with two step injection methods, because the diffusion coefficient of arsenic is little, advance the speed of diffusion slow, the knot of formation is also just more shallow, and the diffusion coefficient of phosphorus is large, the mixing of two kinds of ions is injected, and can reach the ohmic contact that surperficial high concentration is done emitter, also can reach enough junction depths.
Reverse ion is carried out while injecting in the back side of silicon chip, and B Implanted ion to be to form shallow P type collector area 2, because the device architecture that is over has been done on surface, deposit aluminium lamination, so the back side adds man-hour, can not adopt high annealing, and adopt 400 ° of process annealings.
Described side polysilicon electrode adopts slot type structure, and its electrode material is only polysilicon, and described silicon dioxide side polysilicon oxidation layer thickness is the same with silicon dioxide gate oxidated layer thickness.
The present invention illustrates with 1200V groove non-through insulated-gate bipolar transistor, when the present invention specifically implements with side polysilicon electrode groove non-through insulated-gate bipolar transistor, adopts thin slice technique, and key step is:
Step 1) substrate preparation: adopt the molten N-single crystalline substrate in<100> district, its doping content is to calculate according to requirement of withstand voltage, and this example of thickness is 300 μ m.
Step 2) growth oxide-film: adopt dry oxygen-wet oxygen-dry oxygen three-step approach, add HCl to introduce chlorine element, improved the breakdown characteristics of oxide layer, reduced interface state density and surface fixed electronic charge density.
Step 3) P type base 10 forms: B Implanted ion, push away trap annealing, and form the P base junction depth needing.
Step 4) P+ tagma 7 forms: deposit photoresist, and mask plate, exposed photoresist, B Implanted ion, forms the high ohmic contact of mixing, and removes photoresist, and oxide-film is removed in annealing.
The formation of step 5) side polysilicon electrode 5 and polygate electrodes 12: etching side polysilicon groove and grid groove in same template, as shown in Figure 2.Growth silicon dioxide side polysilicon oxide layer 4 and silicon dioxide gate oxide 13, depositing polysilicon, chemical-mechanical planarization, removes groove unnecessary polysilicon in addition, makes whole silicon chip surface obtain planarization, then oxide layer etching.
Step 6) N+ type source region 9 forms: deposit photoresist, and mask plate, exposed photoresist, two steps are injected arsenic and phosphorus, first inject arsenic ion, are injecting phosphonium ion, and annealing is removed photoresist.
Step 7) front separator forms, deposit silicon dioxide oxide layer, mask plate, etching silicon dioxide, deposit boron-phosphorosilicate glass BPSG, mask plate, etching BPSG, deposition surface metal, etching metal forms metallization side polysilicon electrode 6, metallization emitter 8, metallization grid 11.
P type collector area, the step 8) back side 2 forms: upset silicon chip, and thinning back side, thickness thinning can be adjusted according to requirement of withstand voltage; Thickness is 160 μ m, deposited oxide layer, reverse ion B Implanted and annealing, the collector electrode of formation device.
Step 9) back face metalization collector electrode 1 forms: remove the back side as the oxide-film of boron Implantation buffering, sputter back side aluminium lamination, etching aluminium.
In implementation process, can as the case may be, in the situation that basic structure according to the invention is constant, carry out certain accommodation design.
According to above-mentioned technological process and structural design, when metallization side polysilicon electrode voltage 6 is 5V, the situation that the voltage of metallization grid 11 and metallization emitter 8 is 0V, device is in blocking state.Groove non-through insulated-gate bipolar transistor with side polysilicon electrode provided by the invention and traditional groove non-through insulated-gate bipolar transistor near the comparison of the Electric Field Distribution at communication channel place as Fig. 3.Can find out that new IGBT of the present invention has scabbled the spike electric field value of original channel bottom, becomes mild electric field and rises.
The present invention introduces a groove side polysilicon electrode on the basis of traditional igbt, and groove side polysilicon electrode is polycrystalline silicon material, by thin dioxide layer, is surrounded.When metallization adds positive potential on collector electrode 1, when metallization grid 11 and metallization emitter 8 short circuit connecting to neutral current potential, device, in cut-off state, forms without raceway groove, the PN junction that P type base 10 and N-type drift region 3 form, and depletion layer is to expansion in N-type drift region 3.Direction of an electric field from bottom to top, still due to little in channel bottom curved surface rate, can concentrate in groove polygate electrodes bottom by electric field, and this has just increased peak value electric field herein, makes to puncture in advance here to occur.By apply a forward voltage on groove side polysilicon electrode, can form sensing reversed electric field from the top down, thereby offset the peak value electric field of groove polygate electrodes bottom, make the electric field compromise of this peak value electric field and groove side polysilicon electrode bottom.Secondly, be applied with certain bias voltage on grid, raceway groove forms, and electric current can flow to emitter from collector electrode, and device is in conducting state.Now, by add certain voltage on groove side polysilicon electrode, can form how sub-accumulation layer in silicon dioxide side polysilicon oxide layer outside, reduce conducting resistance, thus the on-state loss while reducing forward conduction.The present invention proposes groove side polysilicon electrode can well solve channel bottom due to the shortcoming of the too small electric field accumulation of curvature, improves the compressive resistance of Trench-NPT-IGBT device and reduces cut-in voltage.
Claims (1)
1. with a side polysilicon electrode groove non-through insulated-gate bipolar transistor, it is characterized in that being provided with metallization collector electrode, P type collector area, N-type drift region, silicon dioxide side polysilicon oxide layer, side polysilicon electrode, metallization side polysilicon electrode, P+ tagma, metallization emitter, N+ type source region, P type base, metallization grid, polygate electrodes and silicon dioxide gate oxide;
Described metallization collector electrode is positioned at the back side of P type collector area, and N-type drift region is positioned at the front of P type collector area; N+ type source region and P+ tagma are positioned at metallization emitter below side by side, and N+ type source region is connected with metallization emitter with P+ tagma, wherein, below P+ tagma, be directly connected with N-type drift region, between N+ type source region and N-type drift region across P type base; Polygate electrodes is located at top device and is positioned at a side of metallization emitter, and polygate electrodes side is surrounded by silicon dioxide gate oxide; The sidewall of silicon dioxide gate oxide contacts with N+ type source region, P type base and N-type drift region respectively, and silicon dioxide gate oxide bottom contacts with N-type drift region; Side polysilicon electrode is located at top device and is positioned at the opposite side of metallization emitter, and side polysilicon electrode side is surrounded by silicon dioxide side polysilicon oxide layer; The sidewall of silicon dioxide side polysilicon oxide layer contacts with P+ tagma, N-type drift region respectively, and silicon dioxide side polysilicon oxide layer bottom contacts with N-type drift region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310528583.0A CN103531621A (en) | 2013-10-31 | 2013-10-31 | Non-punch-through type insulated gate bipolar transistor with side polysilicon electrode trench |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310528583.0A CN103531621A (en) | 2013-10-31 | 2013-10-31 | Non-punch-through type insulated gate bipolar transistor with side polysilicon electrode trench |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103531621A true CN103531621A (en) | 2014-01-22 |
Family
ID=49933485
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310528583.0A Pending CN103531621A (en) | 2013-10-31 | 2013-10-31 | Non-punch-through type insulated gate bipolar transistor with side polysilicon electrode trench |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103531621A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105762077A (en) * | 2016-05-12 | 2016-07-13 | 中山港科半导体科技有限公司 | Manufacturing method of insulated gate bipolar transistor |
| CN105789294A (en) * | 2016-05-12 | 2016-07-20 | 中山港科半导体科技有限公司 | Insulated gate bipolar transistor structure |
| CN107799582A (en) * | 2017-10-20 | 2018-03-13 | 电子科技大学 | A kind of trench gate electric charge memory type insulated gate bipolar transistor and its manufacture method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002190595A (en) * | 2000-12-21 | 2002-07-05 | Denso Corp | Semiconductor device and method of manufacturing the same |
| US20050029557A1 (en) * | 2002-03-25 | 2005-02-10 | Tetsuo Hatakeyama | High-breakdown-voltage semiconductor device |
| CN101694850A (en) * | 2009-10-16 | 2010-04-14 | 电子科技大学 | Carrier-storing grooved gate IGBT with P-type floating layer |
-
2013
- 2013-10-31 CN CN201310528583.0A patent/CN103531621A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002190595A (en) * | 2000-12-21 | 2002-07-05 | Denso Corp | Semiconductor device and method of manufacturing the same |
| US20050029557A1 (en) * | 2002-03-25 | 2005-02-10 | Tetsuo Hatakeyama | High-breakdown-voltage semiconductor device |
| CN101694850A (en) * | 2009-10-16 | 2010-04-14 | 电子科技大学 | Carrier-storing grooved gate IGBT with P-type floating layer |
Non-Patent Citations (1)
| Title |
|---|
| LINGFENG JIANG ET AL: ""Side-poly technique for enhanced breakdown voltage of Trench-NPT-IGBT"", 《ANTI-COUNTERFEITING, SECURITY AND IDENTIFICATION (ASID), 2013 IEEE INTERNATIONAL CONFERENCE ON》, 27 October 2013 (2013-10-27) * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105762077A (en) * | 2016-05-12 | 2016-07-13 | 中山港科半导体科技有限公司 | Manufacturing method of insulated gate bipolar transistor |
| CN105789294A (en) * | 2016-05-12 | 2016-07-20 | 中山港科半导体科技有限公司 | Insulated gate bipolar transistor structure |
| CN105762077B (en) * | 2016-05-12 | 2018-09-07 | 中山汉臣电子科技有限公司 | The manufacturing method of igbt |
| CN105789294B (en) * | 2016-05-12 | 2019-01-01 | 中山汉臣电子科技有限公司 | Insulated gate bipolar transistor structure |
| CN107799582A (en) * | 2017-10-20 | 2018-03-13 | 电子科技大学 | A kind of trench gate electric charge memory type insulated gate bipolar transistor and its manufacture method |
| CN107799582B (en) * | 2017-10-20 | 2021-03-16 | 电子科技大学 | Trench gate charge storage type insulated gate bipolar transistor and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11728421B2 (en) | Split trench gate super junction power device | |
| CN109166924B (en) | Transverse MOS type power semiconductor device and preparation method thereof | |
| CN102364688B (en) | Vertical double-diffusion metal oxide semiconductor field effect transistor (MOSFET) | |
| CN114122123B (en) | Silicon carbide split gate MOSFET (Metal-oxide-semiconductor field Effect transistor) integrated with high-speed freewheeling diode and preparation method | |
| CN109119461B (en) | Super-junction MOS type power semiconductor device and preparation method thereof | |
| CN110600537B (en) | Separation gate CSTBT with PMOS current clamping and manufacturing method thereof | |
| CN103441148A (en) | Groove gate VDMOS device integrated with Schottky diode | |
| CN108461537B (en) | A kind of trench gate charge storage type IGBT and preparation method thereof | |
| CN109065627A (en) | A kind of LDMOS device with polysilicon island | |
| CN113838922A (en) | Split-gate super-junction IGBT device structure with carrier concentration enhancement function and method | |
| CN106098777A (en) | A kind of splitting bar accumulation type DMOS device | |
| CN101694851A (en) | Grooved gate IGBT with P-type floating layer | |
| CN106298939A (en) | A kind of accumulation type DMOS with complex media Rotating fields | |
| CN102130169B (en) | Power MOS (Metal Oxide Semiconductor) device structure with shielding grid and manufacturing method thereof | |
| CN113838914A (en) | RET IGBT device structure with separation gate structure and manufacturing method | |
| CN110534576B (en) | Split-gate 4H-SiC VDMOS device | |
| CN103515443B (en) | A kind of super junction power device and manufacture method thereof | |
| CN103531621A (en) | Non-punch-through type insulated gate bipolar transistor with side polysilicon electrode trench | |
| CN105957894A (en) | DMOS with composite dielectric layer structure | |
| CN105789291A (en) | Double split trench gate charge storage type insulated gate bipolar transistor (IGBT) and manufacturing method thereof | |
| CN102637731A (en) | Terminal structure of channel power metal oxide semiconductor (MOS) device and manufacture method of terminal structure | |
| CN110504313B (en) | Transverse groove type insulated gate bipolar transistor and preparation method thereof | |
| CN102832134B (en) | Preparation method of trench grid VDMOS (vertical double-diffused metal oxide semiconductor) device with ultra-thin source region | |
| CN113838913B (en) | Segmented injection self-clamping IGBT device and manufacturing method thereof | |
| CN102522338B (en) | Forming method of high-voltage super-junction metal oxide semiconductor field effect transistor (MOSFET) structure and P-shaped drift region |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140122 |
|
| RJ01 | Rejection of invention patent application after publication |