CN103490777B - low spurious frequency synthesizer - Google Patents
low spurious frequency synthesizer Download PDFInfo
- Publication number
- CN103490777B CN103490777B CN201310460310.7A CN201310460310A CN103490777B CN 103490777 B CN103490777 B CN 103490777B CN 201310460310 A CN201310460310 A CN 201310460310A CN 103490777 B CN103490777 B CN 103490777B
- Authority
- CN
- China
- Prior art keywords
- frequency
- signal
- output
- dds
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000001629 suppression Effects 0.000 claims abstract description 21
- 230000010355 oscillation Effects 0.000 claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 6
- 238000003786 synthesis reaction Methods 0.000 claims abstract description 6
- 239000013078 crystal Substances 0.000 claims description 8
- 239000008186 active pharmaceutical agent Substances 0.000 abstract 1
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention relates to the technical field of digital communication and discloses a low spurious frequency synthesizer. The low spurious frequency synthesizer comprises a reference clock circuit and a phase-locked loop circuit. The reference clock circuit comprises a direct digital synthesizer (DDS), a frequency mixer and a first frequency divider which are sequentially connected in series. The frequency mixer performs frequency mixing on output signals of the DS. The first frequency divider enables the mixed signal frequencies to be reduced through frequency division and outputs the signal frequencies for serving as reference signals to a frequency synthesis circuit. The phase-locked loop circuit utilizes the reference signals sent by the reference clock circuit to control the frequencies and phases of oscillation signals inside a loop and outputs specified broadband signals. Compared with traditional frequency synthesizers and when the output frequencies are identical, spurious suppression indexes of the low spurious frequency synthesizer are obviously improved, and broadband signals with specified frequencies and bandwidths can be conveniently and flexibly achieved.
Description
Technical Field
The invention relates to the technical field of digital communication, in particular to a low spurious frequency synthesizer.
Background
Modern communication systems and radar systems have increasingly demanding spurious suppression indicators for frequency synthesizers. The spurious suppression degree of the frequency synthesizer will directly affect the sensitivity of the receiver, and especially the near-end spurious of the frequency synthesizer will have a significant effect on the receiver.
In order to implement a wideband frequency Synthesizer with low spurious emissions and meet the requirements of the system on Phase noise and frequency stepping, a conventional implementation is to use an output signal of a DDS (Direct Digital Synthesizer) as a reference signal of a PLL (Phase Locked Loop) to excite the PLL to generate a desired frequency, as shown in fig. 1 (where the PLL is composed of a Phase detector, a Loop filter and a voltage controlled oscillator VCO). In the frequency synthesizer implemented in this way, the degree of suppression of the near-end spur of the output signal mainly depends on the degree of suppression of the near-end spur of the DDS and the size of the feedback frequency division ratio N of the phase-locked loop, and is expressed by the formula: SPSYNTH＝SPDDS+20lgN, wherein SPSYNTHThe near-end spurious suppression degree of the output signal of the frequency synthesizer is shown in the unit of-dBc, SPDDSThe unit is also-dBc for the near-end spurious suppression level of DDS. It can be seen from this equation that the scheme shown in fig. 1 has a near-end stray suppression level that is exacerbated by 20lgN based on the DDS near-end stray suppression level. In the case of a frequency determination of the output signal, obtaining low spurs in this way requires an increase in the phase detection frequency FPFDThereby reducing N or reducing DDS near-end spurs.
However, there are also some significant disadvantages with the above-described prior art: increasing the phase discrimination frequency requires increasing the output frequency of the DDS, and for the same DDS, the higher the output frequency is, the worse the near-end spurs are, so the improvement degree of the spurs by this method is very limited; similarly, to reduce the near-end spurs of the DDS, for the same DDS, only the system clock frequency of the DDS is increased, but the increase of the system clock frequency of the DDS is limited, and the higher the system clock is, the higher the cost of the DDS chip is.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the technical problem to be solved by the present invention is how to quickly and efficiently reduce the near-end spurs of the DDS.
To solve the above technical problem, the present invention provides a low spurious frequency synthesizer, comprising: a reference clock circuit and a frequency synthesis phase-locked loop circuit; improving the near-end spurious suppression degree of the output signal of the frequency synthesizer by improving the near-end spurious suppression degree of the output signal of the DDS; wherein,
the reference clock circuit comprises a DDS, a frequency mixer and a first frequency divider which are sequentially connected in series; the mixer mixes the output signal of the DDS; the first frequency divider reduces the frequency of the mixed signal through frequency division and outputs the signal to the frequency synthesis circuit as a reference signal;
the phase-locked loop circuit utilizes the reference signal sent by the reference clock circuit to control the frequency and the phase of the oscillation signal in the loop circuit and output a specified broadband signal.
Preferably, the reference clock circuit further comprises a crystal oscillator, a dot frequency source and a second frequency divider; wherein,
the output end of the crystal oscillator is coupled with the input end of the point frequency source;
the output end of the point frequency source is coupled to the input ends of the DDS and the second frequency divider at the same time;
the output end of the second frequency divider is coupled with the local oscillation signal input end of the frequency mixer.
Preferably, the phase-locked loop circuit comprises a phase detector, a loop filter and a voltage-controlled oscillator; wherein,
the input end of the phase detector is coupled with the output end of the reference clock circuit, and the feedback signal input end of the phase detector is coupled with the output end of the voltage-controlled oscillator;
the input end of the loop filter is coupled with the output end of the phase discriminator, and the output end of the loop filter is coupled with the input end of the voltage-controlled oscillator;
and the output end of the voltage-controlled oscillator is simultaneously used as the output end of the low spurious frequency synthesizer and the feedback signal input end of the phase discriminator.
Preferably, the frequency divider is a digitally controllable frequency divider with a division ratio.
Preferably, the first frequency divider and the second frequency divider have different division ratios.
Preferably, the first frequency divider has a higher frequency division ratio than the second frequency divider.
Preferably, the frequency dividing ratio of the first frequency divider is above 20, and the frequency dividing ratio of the second frequency divider is below 5.
Preferably, the mixer also filters the output signal of the DDS at the same time.
Preferably, the mixing is up-converting.
Preferably, the frequency of the broadband signal is located between the L-band and the K-band.
Compared with the prior art, when the output frequency of the low-spurious frequency synthesizer is the same, the spurious suppression index is obviously improved, the near-end spurious of the output signal is greatly improved with lower cost and complexity, and the low-spurious and small-step signal output is realized.
Drawings
Fig. 1 is a schematic diagram of a frequency synthesizer according to the prior art.
Fig. 2 is a schematic diagram of a low spurious frequency synthesizer according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the embodiments described are presently preferred modes of carrying out the invention, and that the description is made for the purpose of illustrating the general principles of the invention and not for the purpose of limiting the scope of the invention. The protection scope of the present invention shall be defined by the appended claims, and all other embodiments obtained by those skilled in the art without any inventive work shall fall within the protection scope of the present invention.
The traditional wideband frequency synthesizer implemented by using DDS to excite PLL depends on increasing the output frequency of DDS or increasing the system clock frequency of DDS, and each way has limited improvement on near-end spurs, and the effect is not ideal. In the embodiment of the invention, signal spurious suppression characteristics can be improved by researching and finding that signal frequency division is carried out, and by utilizing the principle, the DDS output signal is converted into a higher frequency through frequency conversion, and then the signal is subjected to frequency division, so that the near-end spurious suppression of the DDS output signal is further improved.
Referring to fig. 2, in one embodiment of the present invention, a C-band, small-step, low-spurious wideband frequency source is implemented by signal division. In the embodiment of fig. 2, the low spur frequency synthesizer comprises: a reference clock circuit and a phase-locked loop circuit; the reference clock circuit comprises a DDS, a frequency mixer and a first frequency divider which are sequentially connected in series, wherein an output signal of the DDS is subjected to frequency mixing and up-conversion to a higher frequency in the reference clock circuit, and then the frequency is reduced through frequency division to serve as a reference signal of the phase-locked loop circuit; the phase-locked loop circuit controls the frequency and the phase of an internal oscillation signal of the loop by using a reference signal sent by the reference clock circuit, and finally outputs a specified broadband signal. Preferably, the mixer also filters the output signal of the DDS simultaneously.
In fig. 2, the reference clock circuit further includes a crystal oscillator, a dot frequency source, and a second frequency divider; the crystal oscillator (crystal oscillator) is used for generating a stable initial signal, the point frequency source converts the crystal oscillator signal into a fixed output frequency and provides the fixed output frequency to the DDS (as a reference clock signal of the DDS) and the second frequency divider, and the second frequency divider divides the frequency of the output frequency of the point frequency source and provides the divided frequency to the mixer to serve as an up-conversion local oscillator signal. Preferably, the second frequency divider is a divide-by-two frequency divider. The local oscillation signal of the DDS up-conversion is generated by the reference clock of the DDS after frequency division, so that the volume of the equipment is further reduced, and the cost of the equipment is reduced.
Further, the phase-locked loop circuit includes: the phase detector, the loop filter and the voltage controlled oscillator VCO; the phase discriminator compares the frequency and the phase of an input reference signal and a feedback signal sent by the voltage-controlled oscillator and outputs a signal representing the difference between the two signals; the loop filter filters out high-frequency components in the signal output by the phase discriminator, and a reserved direct current part is sent to the voltage-controlled oscillator; the voltage-controlled oscillator outputs a periodic signal whose frequency is controlled by the input voltage, and the signal output by the voltage-controlled oscillator is also fed back to the phase detector for feedback. Preferably, the phase detector is a digital phase detector.
The invention realizes the low spurious characteristic of the output signal, and the key point is to adopt the reference clock circuit which is different from the traditional scheme. In the conventional scheme, the reference clock is directly generated by the DDS, and its spur suppression index is also directly determined by the spur-free dynamic range of the DDS (i.e., the spur suppression degree of the DDS). In the scheme adopted by the invention, the reference clock is generated by up-converting and frequency-dividing the output signal of the DDS, and the spurious suppression index is greatly improved on the basis of the spurious-free dynamic range of the DDS.
In a preferred embodiment of the present invention, the adopted frequency divider is a frequency divider with a digitally controllable frequency division ratio, so that the frequency division manner of the signal can be set more flexibly, so as to provide different local oscillator signals or reference signals for the mixer or the PLL circuit, thereby flexibly and conveniently obtaining output broadband signals with different frequencies and/or ranges, so that the apparatus of the present invention can be applied to more application occasions. Preferably, the first and second frequency dividers have different division ratios; the first frequency divider is used for generating a reference signal of the PLL circuit and has a higher frequency dividing ratio; the second frequency divider is used for generating a local oscillation signal of the frequency mixer and has a lower frequency dividing ratio. More preferably, the division ratio of the first frequency divider is above 20, and the division ratio of the second frequency divider is below 5. In addition, the bandwidth of the finally output broadband signal is determined by the bandwidth of the output signal of the VCO, and can generally reach one octave or even two octaves; the frequency of the broadband signal is also determined by the VCO, and the output from the L waveband to the K waveband can be realized by selecting different types of VCOs. Typically, a VCO produced by Z-COMM company is selected, and an SMV1100C-LF type can output L-band signals of 980MHz-1200 MHz; the SMV3400C-LF type can output 3180 and 3430S-band signals; the SMV5550B-LF type can output C-band signals of 5000MHz-6000MHz and the like.
For example, the first frequency divider is a frequency divider for dividing frequency by 20 (to reduce the frequency to 1/20 of the original frequency), and when the second frequency divider is a frequency divider, the VCO is selected to realize the output of the C-band, and a width signal with a frequency of 4GHz-8GHz is obtained. In this embodiment, since the narrow-band spurious-free dynamic range of the DDS chip can reach-95 dBc (assuming that the DDS model used is AD9914), the near-end spurious suppression of the reference clock signal of the frequency synthesizer after 20-division can reach-95 dBc-20lg 20-121 dBc. The spurious rejection is improved by 26dB compared to the reference clock signal generated directly with DDS. And finally outputting a 4GHz-8GHz signal through a frequency synthesis circuit. Calculated according to the highest output frequency of 8GHz, the near-end stray rejection of the output signal can reach-121 dBc +20lg 80-83 dBc.
Compared with the traditional frequency synthesizer, the technical scheme of the invention obviously improves the spurious suppression index when the output frequency is the same, can conveniently and flexibly realize broadband signals with specific frequency and bandwidth while realizing low spurious and low phase noise, greatly improves the near-end spurious of the output signals with lower cost and complexity, and realizes the signal output with low spurious and small step.
The foregoing description shows and describes several preferred embodiments of the invention, but as aforementioned, it is to be understood that the invention is not limited to the forms disclosed herein, but is not to be construed as excluding other embodiments and is capable of use in various other combinations, modifications, and environments and is capable of changes within the scope of the inventive concept as expressed herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (6)
1. A low spurious frequency synthesizer, wherein said frequency synthesizer comprises: a reference clock circuit and a frequency synthesis phase-locked loop circuit; improving the near-end spurious suppression degree of the output signal of the frequency synthesizer by improving the near-end spurious suppression degree of the output signal of the DDS; wherein,
the reference clock circuit comprises a DDS, a frequency mixer and a first frequency divider which are sequentially connected in series; the mixer mixes the output signal of the DDS; the first frequency divider reduces the frequency of the mixed signal through frequency division and outputs the signal to the frequency synthesis circuit as a reference signal;
the reference clock circuit also comprises a crystal oscillator, a dot frequency source and a second frequency divider; the output end of the crystal oscillator is coupled with the input end of the point frequency source; the output end of the point frequency source is coupled to the input ends of the DDS and the second frequency divider at the same time; the output end of the second frequency divider is coupled with the local oscillation signal input end of the frequency mixer; the first frequency divider and the second frequency divider are frequency dividers with digitally controllable frequency dividing ratios and have different frequency dividing ratios;
the phase-locked loop circuit comprises a phase discriminator, a loop filter and a voltage-controlled oscillator; wherein,
the input end of the phase detector is coupled with the output end of the reference clock circuit, and the feedback signal input end of the phase detector is coupled with the output end of the voltage-controlled oscillator;
the input end of the loop filter is coupled with the output end of the phase discriminator, and the output end of the loop filter is coupled with the input end of the voltage-controlled oscillator;
the output end of the voltage-controlled oscillator is simultaneously used as the output end of the low spurious frequency synthesizer and the feedback signal input end of the phase discriminator, and the phase-locked loop circuit utilizes the frequency and the phase of the internal oscillation signal of the reference signal control loop sent by the reference clock circuit to output a specified broadband signal.
2. The low spurious frequency synthesizer of claim 1, wherein the first frequency divider has a higher frequency division ratio than the second frequency divider.
3. The low spurious frequency synthesizer of claim 2, wherein a division ratio of the first divider is above 20 and a division ratio of the second divider is below 5.
4. A low spurious frequency synthesizer as recited in claim 1, wherein said mixer also simultaneously filters the output signal of said DDS.
5. A low spurious frequency synthesizer as recited in claim 1, wherein said mixing is performed as an upconversion.
6. The low spurious frequency synthesizer of claim 1, wherein a frequency of the wideband signal is located between an L-band and a K-band.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310460310.7A CN103490777B (en) | 2013-09-30 | 2013-09-30 | low spurious frequency synthesizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310460310.7A CN103490777B (en) | 2013-09-30 | 2013-09-30 | low spurious frequency synthesizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103490777A CN103490777A (en) | 2014-01-01 |
| CN103490777B true CN103490777B (en) | 2017-03-22 |
Family
ID=49830774
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310460310.7A Active CN103490777B (en) | 2013-09-30 | 2013-09-30 | low spurious frequency synthesizer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103490777B (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105372512B (en) * | 2014-08-26 | 2019-06-18 | 苏州普源精电科技有限公司 | RF measurement device with phase fixation |
| CN104579335A (en) * | 2014-09-26 | 2015-04-29 | 中国人民解放军总参谋部第六十三研究所 | Frequency design method for frequency synthesizer |
| CN104320133A (en) * | 2014-10-13 | 2015-01-28 | 中国电子科技集团公司第四十一研究所 | Electric circuit and method for restraining fractional stray of fractional phase locking loops |
| CN104393871A (en) * | 2014-12-02 | 2015-03-04 | 贵州航天计量测试技术研究所 | Frequency synthesizer for driving phase-locked loop after up-converting DDS |
| CN104467827B (en) * | 2014-12-31 | 2018-09-21 | 陕西烽火电子股份有限公司 | A kind of fractional-N frequency synthesizer spurious reduction method |
| CN106656176A (en) * | 2016-12-30 | 2017-05-10 | 重庆华伟工业（集团）有限责任公司 | Wide-frequency-band agile frequency synthesizer |
| CN106533439B (en) * | 2017-01-09 | 2023-06-06 | 成都西蒙电子技术有限公司 | Low phase noise frequency synthesizer |
| CN109412589B (en) * | 2017-08-16 | 2024-04-05 | 天津乾铁科技有限公司 | Optimizing method and system for integer boundary spurious of fractional frequency synthesizer |
| CN108092663B (en) * | 2017-12-26 | 2022-01-21 | 海能达通信股份有限公司 | Frequency generating device and frequency generating method |
| WO2020041967A1 (en) * | 2018-08-28 | 2020-03-05 | 华为技术有限公司 | Phase locked loop circuit and device using same |
| CN110176928A (en) * | 2019-05-29 | 2019-08-27 | 江苏华讯电子技术有限公司 | A kind of extra small stepping based on DDS and PLL structure, low spurious broadband frequency synthesizer |
| CN111835340B (en) * | 2020-09-21 | 2020-12-08 | 成都雷通科技有限公司 | Double-loop frequency source for driving PLL (phase locked loop) by fine stepping broadband PLL |
| CN112653426A (en) * | 2020-12-21 | 2021-04-13 | 贵州航天计量测试技术研究所 | Broadband extremely-narrow pulse signal generating circuit |
| CN113726334B (en) * | 2021-07-20 | 2024-03-08 | 江苏华讯电子技术有限公司 | S-band low-phase-noise low-stray fine stepping frequency source assembly and use method |
| CN117040530B (en) * | 2023-08-01 | 2024-04-26 | 南京威翔科技有限公司 | Broadband frequency synthesis module |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5859570A (en) * | 1994-09-29 | 1999-01-12 | Mitsubishi Denki Kabushiki Kaisha | Frequency synthesizer using divided and frequency converted DDS signal as reference for PLL |
| CN202652188U (en) * | 2012-07-02 | 2013-01-02 | 中国电子科技集团公司第五十四研究所 | Frequency hopping frequency synthesizer |
| CN202978896U (en) * | 2012-11-09 | 2013-06-05 | 北京中科飞鸿科技有限公司 | Combined broadband rapid frequency hopping source |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102013889A (en) * | 2010-06-29 | 2011-04-13 | 上海杰盛无线通讯设备有限公司 | Low-stray small-stepping high-speed frequency-hopping synthesizer |
-
2013
- 2013-09-30 CN CN201310460310.7A patent/CN103490777B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5859570A (en) * | 1994-09-29 | 1999-01-12 | Mitsubishi Denki Kabushiki Kaisha | Frequency synthesizer using divided and frequency converted DDS signal as reference for PLL |
| CN202652188U (en) * | 2012-07-02 | 2013-01-02 | 中国电子科技集团公司第五十四研究所 | Frequency hopping frequency synthesizer |
| CN202978896U (en) * | 2012-11-09 | 2013-06-05 | 北京中科飞鸿科技有限公司 | Combined broadband rapid frequency hopping source |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103490777A (en) | 2014-01-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103490777B (en) | low spurious frequency synthesizer | |
| CN108736889B (en) | Low spurious/low phase noise frequency synthesizer | |
| US8890590B1 (en) | Wideband frequency synthesizer and frequency synthesizing method thereof | |
| US7602254B2 (en) | System and method for generating signals with a preselected frequency relationship in two steps | |
| CN102651649A (en) | Design method of low-phase-noise microwave wideband frequency combiner | |
| US7521974B2 (en) | Translational phase locked loop using a quantized interpolated edge timed synthesizer | |
| CN103178838A (en) | A phase-locked loop or phase-locked loop frequency synthesis device and method | |
| CN102237890B (en) | Integrated RF transceiver circuit and method for forming digital clock signals | |
| CN101136631B (en) | Frequency synthesizer and frequency synthesis method | |
| US8736326B1 (en) | Frequency synthesizer and frequency synthesis method thereof | |
| CN204633753U (en) | Based on HMC835 broadband low phase noise low spurious frequency hopping source | |
| JP2003534700A (en) | Rotation frequency synthesizer | |
| US8044725B2 (en) | Signal generator with directly-extractable DDS signal source | |
| CN110289858B (en) | Broadband fine stepping agile frequency conversion combination system | |
| CN105553475A (en) | High frequency point frequency source synthetic circuit based on digital frequency division and harmonic frequency mixing | |
| CN113726334B (en) | S-band low-phase-noise low-stray fine stepping frequency source assembly and use method | |
| CN117081583B (en) | Frequency source for improving phase noise | |
| US20170026050A1 (en) | Frequency synthesizer | |
| KR101298621B1 (en) | Fmcw synthesizer and control method thereof | |
| CN115347868B (en) | Signal generating apparatus and signal generating method for generating low phase noise signal | |
| CN115940938A (en) | Low-phase-noise fast broadband frequency sweeping frequency source | |
| KR101661241B1 (en) | A method of synthesizing microwave frequency signal for multiple atomic clocks and an apparatus thereof | |
| US7772932B1 (en) | Quadrature local oscillator generation for direct conversion radio transceiver | |
| JP6584330B2 (en) | Frequency synthesizer | |
| JP6753132B2 (en) | Signal source |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |