CN103489399B - Electroluminescent pixel circuit - Google Patents

Abstract

The invention discloses an electroluminescent pixel circuit, which includes an organic light-emitting diode, a compensation unit and a switching transistor. The cathode terminal of the organic light emitting diode is electrically connected to the first voltage source. The compensation unit is electrically connected to the second voltage source and is used to receive the control signal, the first scanning signal and the second scanning signal. The pulse enabling periods of the first scanning signal and the second scanning signal are both within the pulse enabling period of the control signal. within, and the pulse enabling period of the first scanning signal is before the pulse enabling period of the second scanning signal. The switching transistor has a first terminal, a second terminal and a gate terminal. The two terminals of the switching transistor are electrically connected between the compensation unit and the anode terminal of the organic light emitting diode, and the switching transistor is turned on according to the control signal.

Description

Electroluminescence pixel circuit

technical field

The invention relates to the technical field of organic light emitting diode displays, and in particular to an electroluminescent pixel circuit of an organic light emitting diode display.

Background technique

Please refer to FIG. 1 , which is a schematic diagram of a conventional OLED (Organic Light Emitting Diode, OLED) electroluminescent pixel circuit. The electroluminescent pixel circuit 100 includes a driving transistor 102 , a switching transistor 104 , a capacitor 106 and an organic light emitting diode 110 . The first end of the driving transistor 102 is electrically connected to the voltage source OVDD. The gate terminal of the switching transistor 104 receives the scan signal SCAN due to the electrical connection, the first terminal of the switching transistor 104 receives the data voltage Vdata due to the electrical connection, and the second terminal is electrically connected to the gate terminal of the driving transistor 102 . Both ends of the capacitor 106 are connected between the gate terminal and the first terminal of the driving transistor 102 . An anode terminal of the OLED 110 is electrically connected to the second terminal of the driving transistor 102 , and a cathode terminal is electrically connected to another voltage source OVSS. The foregoing pixel structure generates a pixel current I _oled according to the potential difference Vsg between the first terminal and the gate terminal of the driving transistor 102 to drive the organic light emitting diode 110 to light up, and the pixel current flowing through the organic light emitting diode 110 is I _oled =K*(V _sg -|V _TH |) ² . K is a constant, the magnitude of V _sg is related to the magnitude of the voltage source OVDD and the data voltage Vdata, and VTH is the threshold voltage of the driving transistor 102 .

Due to the influence of the manufacturing process, the threshold voltage VTH of the drive transistor 102 of each pixel is not the same, resulting in a difference in the pixel current I _oled between pixels in the organic light emitting diode display, so that the current I oled flowing through each organic light emitting diode OLED The brightness produced by different currents will be different, thus causing the problem of uneven panel display.

Contents of the invention

The invention proposes an electroluminescence pixel circuit, which includes an organic light emitting diode, a compensation unit and a switch transistor. The organic light emitting diode has an anode end and a cathode end, and the cathode end of the organic light emitting diode is electrically connected to the first voltage source. The compensation unit is electrically connected to the second voltage source and is used for receiving the control signal, the first scanning signal and the second scanning signal, wherein the pulse enabling periods of the first scanning signal and the second scanning signal are all within the pulse enabling period of the control signal During the period, the pulse enabling period of the first scan signal is before the pulse enabling period of the second scan signal. The switch transistor has a first terminal, a second terminal and a gate terminal, and the two terminals of the switch transistor are electrically connected between the compensation unit and the anode terminal of the organic light emitting diode, and are turned on according to a control signal, wherein the first voltage source and The second voltage sources are all fixed voltages, and the level of the first voltage source is opposite to that of the second voltage source.

The present invention further provides an electroluminescence pixel circuit, which includes an organic light emitting diode, a switch transistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a first capacitor. Wherein, the organic light emitting diode has an anode end and a cathode end, and the cathode end of the organic light emitting diode is electrically connected to the first voltage source. The switch transistor has a first terminal, a second terminal and a gate terminal, the second terminal of the switch transistor is electrically connected to the anode terminal of the organic light emitting diode, and the gate terminal of the switch transistor is used for receiving a control signal and turning on the switch according to the control signal transistor. The first transistor has a first terminal, a second terminal and a gate terminal, wherein the first terminal of the first transistor is electrically connected to the second voltage source, and the gate terminal of the first transistor is used for receiving a control signal. The second transistor has a first terminal, a second terminal and a gate terminal, wherein the first terminal of the second transistor is electrically connected to the second terminal of the first transistor, and the second terminal of the second transistor is electrically connected to the first terminal of the switching transistor. one end. The third transistor has a first terminal, a second terminal and a gate terminal, wherein the first terminal of the third transistor is used to receive the data voltage, the second terminal of the third transistor is electrically connected to the first terminal of the second transistor, and the first terminal of the third transistor is electrically connected to the first terminal of the second transistor. The gate terminals of the three transistors are used for receiving the second scan signal. The fourth transistor has a first terminal, a second terminal and a gate terminal, wherein the first terminal of the fourth transistor is electrically connected to the second terminal of the second transistor, and the second terminal of the fourth transistor is electrically connected to the second terminal of the second transistor. The gate terminal of the fourth transistor is used for receiving the second scan signal. The fifth transistor has a first terminal, a second terminal and a gate terminal, the first terminal of the fifth transistor and the gate terminal of the fifth transistor are both electrically connected to the second voltage source, and the second terminal of the fifth transistor is electrically connected to the Gate terminal of the second transistor. The first capacitor, one end of the first capacitor is used to receive the first scan signal, and the other end of the first capacitor is electrically connected to the gate end of the second transistor.

The present invention further provides an electroluminescence pixel circuit, which includes a light emitting element, a switch transistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor and a second capacitor. The light emitting element has an anode end and a cathode end, and the cathode end of the light emitting element is electrically connected to the first voltage source. The switch transistor, the switch transistor has a first terminal, a second terminal and a gate terminal, the second terminal of the switch transistor is electrically connected to the anode terminal of the light emitting element, and the gate terminal of the switch transistor is used for receiving a control signal. The first transistor has a first terminal, a second terminal and a gate terminal. The first terminal of the first transistor is electrically connected to the second voltage source, and the gate terminal of the first transistor is used for receiving a control signal. The second transistor has a first terminal, a second terminal and a gate terminal, the first terminal of the second transistor is electrically connected to the second terminal of the first transistor, and the second terminal of the second transistor is electrically connected to the switch transistor. first end. The third transistor has a first terminal, a second terminal and a gate terminal, the first terminal of the third transistor is electrically connected to the second terminal of the second transistor, and the second terminal of the third transistor is electrically connected to the gate of the second transistor terminal, and the gate terminal of the third transistor is used to receive the first scan signal. The fourth transistor has a first terminal, a second terminal and a gate terminal, the first terminal of the fourth transistor is used to receive the data voltage, the second terminal of the fourth transistor is electrically connected to the gate terminal of the second transistor, and the fourth transistor The gate terminal is used to receive the third scan signal. The fifth transistor has a first terminal, a second terminal and a gate terminal, the first terminal of the fifth transistor is electrically connected to the second voltage source, the second terminal of the fifth transistor is electrically connected to the second terminal of the second transistor, The gate terminal of the fifth transistor is used for receiving the first scan signal. The first capacitor is electrically connected between the gate terminal of the second transistor and the first terminal of the second transistor. The second capacitor is electrically connected between the first terminal of the second transistor and the second scan signal.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are specifically cited below and described in detail with accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of a conventional electroluminescence pixel circuit.

FIG. 2 is a schematic diagram of an electroluminescence pixel circuit according to an embodiment of the invention.

FIG. 3 is a schematic diagram of the interior of a compensation unit according to an embodiment of the invention.

FIG. 4 is a timing diagram of some signals of the electroluminescence pixel circuit shown in FIG. 3 .

FIG. 5 is a schematic diagram of another compensation unit inside the electroluminescent pixel circuit according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of yet another compensation unit inside the electroluminescent pixel circuit according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of an electroluminescence pixel circuit according to another embodiment of the present invention.

FIG. 8 is a schematic diagram of the interior of a compensation unit according to another embodiment of the present invention.

FIG. 9 is a timing diagram of some signals of the electroluminescence pixel circuit shown in FIG. 8 .

FIG. 10 is a schematic diagram of an electroluminescent pixel circuit according to an embodiment of the present invention.

FIG. 11 is a timing diagram of some signals of the electroluminescence pixel circuit shown in FIG. 10 .

FIG. 12 is a schematic diagram of an electroluminescent pixel circuit according to another embodiment of the present invention.

FIG. 13 is a schematic diagram of an electroluminescent pixel circuit according to another embodiment of the present invention.

FIG. 14 is a timing diagram of some signals of the electroluminescence pixel circuit shown in FIG. 13 .

Among them, reference signs:

100, 200, 300, 500, 600, 700, 800: Electroluminescence pixel circuit

102: Drive transistor

104, 220, 720, 1002, 1302: switching transistors

106, 316, 517, 617, 816, C1, C2: capacitance

110, 230, 730: organic light-emitting diodes

OVDD, OVSS, Vref: voltage source

SCAN: scan signal

Vdata: data voltage

I _oled : pixel current

210, 310, 510, 610, 710, 810: compensation unit

EM: control signal

S1: first scan signal

S2: second scan signal

S3: The third scan signal

311, 811, 1003, 1303: first transistor

312, 812, 1004, 1304: second transistor

313, 813, 1005, 1305: the third transistor

314, 814, 1006, 1306: fourth transistor

315, 615, 815, 1007, 1207, 1307: fifth transistor

A: node

V _A : potential of node A

T1～T5: time

1000, 1200, 1300: electroluminescence pixel circuit

1001, 1301: light emitting element

Detailed ways

FIG. 2 is a schematic diagram of an electroluminescent pixel circuit according to an embodiment of the invention. The electroluminescence pixel circuit 200 includes a compensation unit 210 , a switch transistor 220 and an organic light emitting diode 230 . Wherein, the organic light emitting diode 230 has an anode end and a cathode end, and the cathode end of the organic light emitting diode 230 is electrically connected to the voltage source OVSS. The compensation unit 210 is electrically connected to another voltage source OVDD, and receives the control signal EM, the first scan signal S1 and the second scan signal S2 due to the electrical connection, wherein the first scan signal S1 and the second scan signal S2 The pulse enabling periods are all within the pulse enabling period of the control signal EM, and the pulse enabling period of the first scan signal S1 is before the pulse enable period of the second scan signal S2 . The switch transistor 220 has a first terminal, a second terminal and a gate terminal. The two ends of the switch transistor 220 are electrically connected between the compensation unit 210 and the anode terminal of the organic light emitting diode 230 , and the switch transistor 220 is turned on according to the control signal EM. Both the voltage sources OVSS and OVDD are fixed voltages, and the level of the voltage source OVSS is opposite to that of the voltage source OVDD. The voltage source OVSS is, for example, −4.4 volts, and the voltage source OVDD is, for example, +4.6 volts.

For details, please refer to FIG. 3 , which is a schematic diagram of the interior of the compensation unit. In FIG. 3 , the same symbols as those in FIG. 2 represent the same elements, voltage sources or signals. The compensation unit 310 shown in FIG. 3 includes a first transistor 311, a second transistor 312 (hereinafter referred to as the second transistor is the driving transistor), a third transistor 313, a fourth transistor 314, a fifth transistor 315 and a capacitor 316 , wherein the first to fifth transistors 311 - 315 all have a first terminal, a second terminal and a gate terminal. The first end of the first transistor 311 is electrically connected to the voltage source OVDD, and the gate end of the first transistor 311 receives the control signal EM due to the electrical connection. The first end of the second transistor 312 is electrically connected to the second end of the first transistor 311 , and the second end of the second transistor 312 is electrically connected to the first end of the switch transistor 220 . The first terminal of the third transistor 313 receives the data voltage Vdata due to the electrical connection, and the second terminal of the third transistor 313 is electrically connected to the first terminal of the second transistor 312, and the gate terminal of the third transistor 313 is The second scan signal S2 is received due to the electrical connection. The first terminal of the fourth transistor 314 is electrically connected to the second terminal of the second transistor 312, and the second terminal of the fourth transistor 314 is electrically connected to the gate terminal of the second transistor 312, and the gate terminal of the fourth transistor 314 Then, the second scan signal S2 is received due to the electrical connection. Both the first terminal and the gate terminal of the fifth transistor 315 are electrically connected to the voltage source OVDD, and the second terminal of the fourth transistor 314 is electrically connected to the gate terminal of the second transistor 312 . One terminal of the capacitor 316 is electrically connected to receive the first scan signal S1 , and the other terminal of the capacitor 316 is electrically connected to the gate terminal of the second transistor 312 .

In this embodiment, the first transistor 311 , the second transistor 312 , the third transistor 313 , the fourth transistor 314 , the fifth transistor 315 and the switch transistor 220 may all be PMOS transistors. Taking the PMOS transistor as an example, the timing of the first scan signal S1 , the second scan signal S2 and the control signal EM in FIG. 3 will be described below.

FIG. 4 is a timing diagram of some signals of the electroluminescence pixel circuit shown in FIG. 3 . In FIG. 4 , the same symbols as those in FIG. 3 represent the same signals, and the symbol VA is the potential of node A shown in FIG. 3 . It can be seen from FIG. 4 that during the period T1-T5, the pulse enabling periods of the first scanning signal S1 and the second scanning signal S2 are both within the pulse enabling period of the control signal EM, and the pulse enabling period of the first scanning signal S1 The pulse enabling period is before the pulse enabling period of the second scan signal S2. Wherein, in time T1 and time T5, the time interval between the rising edge of the control signal EM and the rising edge of the first scanning signal S1 is used to buffer the time required for the first scanning signal S1 to be pulled up from the low level to the high level, and The interval between the falling edge of the control signal EM and the rising edge of the second scanning signal S2 is used to buffer the time required for the second scanning signal S2 to be pulled up from the low level to the high level, so that the first scanning can be ensured. Both the pulse enabling periods of the signal S1 and the second scanning signal S2 are within the pulse enabling period of the control signal EM.

Although, in the present embodiment, the falling edge of the first scanning signal S1 and the falling edge of the second scanning signal S2 are mutually overlapped, but in some embodiments, the falling edge of the first scanning signal S1 and the falling edge of the second scanning signal S2 overlap each other. The falling edges of the second scan signal S2 may also be non-overlapping. That is to say, after the first scan signal S1 transitions from a high level to a low level, the second scan signal S2 starts to transition from a high level to a low level state. Therefore, whether the falling edge of the first scanning signal S1 overlaps with the falling edge of the second scanning signal S2, only the pulse enabling periods of the first scanning signal S1 and the second scanning signal S2 are within the pulse of the control signal EM. During the enabling period, the electroluminescence pixel circuit can be operated normally, and the present invention can be realized. The signal implementations listed above are only used as examples, and the present invention is not limited thereto.

The driving process of the electroluminescence pixel circuit 300 will be described in detail below in conjunction with FIG. 3 and FIG. The operation phases fall in time T2, time T3 and time T5 respectively.

Specifically, during the reset operation phase T2 of the electroluminescence pixel circuit 300, the control signal EM, the first scan signal S1 and the second scan signal S2 all exhibit a high level state, so that the fifth transistor 315 is in a conduction state, However, the first transistor 311 , the second transistor 312 , the third transistor 313 , the fourth transistor 314 and the switch transistor 220 are all turned off. At this time, the voltage source OVDD is provided to the capacitor 316 through the turned-on fifth transistor 315 so that the potential V _A of the node A is OVDD+|V _TH |.

Then during the writing and compensation operation phase T3, both the first scan signal S1 and the second scan signal S2 are in a low level state, while the control signal EM is in a high level state, so that the third transistor 313 and the fourth transistor 314 are both in a low level state. is in an on state, and the first transistor 311 , the fifth transistor 315 and the switch transistor 220 are all in an off state. At this time, since the potential of the node A is higher than the potential of the first terminal of the second transistor 312, the second transistor 312 is also in an off state. The charge originally stored in the capacitor 316 will be released gradually over time, and then when the potential VA of the node _A drops to a potential lower than Vdata−|V _TH |, the second transistor 312 will be turned on.

At this time, when the second transistor 312, the third transistor 313 and the fourth transistor 314 are all in the on state, and the first transistor 311, the fifth transistor 315 and the switch transistor 220 are in the off state, the value of the data voltage Vdata is The second transistor 312 , the third transistor 313 and the fourth transistor 314 are turned on to provide to the capacitor 316 so that the potential V _A of the node A is maintained at the level of Vdata−|V _TH |.

Finally, during the light-emitting operation period T5, both the first scanning signal S1 and the control signal EM are in a low-level state, while the second scanning signal S2 is in a high-level state, so that the first transistor 311, the second transistor 312 and the switching transistor 220 All are in the on state, and the third transistor 313 , the fourth transistor 314 and the fifth transistor 315 are all in the off state. In this way, the second transistor 312 (ie, the driving transistor) can generate a pixel current I _oled according to the potential difference V _sg between its first terminal and its gate terminal at this time to drive the OLED 230 to light up.

According to the above, the pixel current I _oled =K*(V _sg −|V _TH |) ² flowing through the OLED 230 . At this time, the potential difference V _sg between the first terminal and the gate terminal of the second transistor 312 is respectively the voltage source OVDD and the potential Vdata-|V _TH | of the node A, so the pixel current flowing through the organic light emitting diode 230 is I _oled =K*{[OVDD-(Vdata-|V _TH |)]-|V _TH |} ² =K*(OVDD-Vdata) ² . It can be known from this that during the period of the light-emitting operation phase T5, the pixel current I _oled flowing through the organic light emitting diode 230 is only related to the voltage source OVDD and the data voltage Vdata, and is not related to the threshold voltage of the second transistor 312 (ie, the driving transistor). V _TH is completely irrelevant. In this way, the problem of panel display unevenness caused by the influence of the manufacturing process of the organic light emitting diode on the threshold voltage of the driving transistor can be effectively improved, so that the organic light emitting diode display can compensate the threshold voltage when displaying a picture, and in It can still maintain better display quality under long-term use.

In addition, in some embodiments, the compensation unit inside the electroluminescent pixel circuit of the present invention can be slightly improved, which are illustrated in FIG. 5 and FIG. 6 respectively. 5 is a schematic diagram of another compensation unit inside the electroluminescent pixel circuit according to the present invention. In FIG. 5 , the same symbols as those in FIG. 3 represent the same objects, voltage sources or signals. The difference between the compensation unit 510 of the electroluminescence pixel circuit 500 shown in FIG. 5 and the compensation unit 310 of the electroluminescence pixel circuit 300 shown in FIG. 3 is that the compensation unit 510 inside the electroluminescence pixel circuit 500 also A capacitor 517 is included, which is electrically connected between the second terminal and the gate terminal of the fourth transistor 314 .

FIG. 6 is a schematic diagram of a compensation unit inside another electroluminescent pixel circuit according to the present invention. In FIG. 6 , the same symbols as those in FIG. 3 represent the same objects, voltage sources or signals. The difference between the compensation unit 610 of the electroluminescent pixel circuit 600 shown in FIG. 6 and the compensation unit 310 of the electroluminescent pixel circuit 300 shown in FIG. 3 is that the compensation unit 610 inside the electroluminescent pixel circuit 600 also The capacitor 617 is included, the first end of the capacitor 617 is electrically connected to the voltage source OVDD or the voltage source Vref, and the second end of the capacitor 617 is electrically connected to one end of the capacitor 316 . In addition, the fifth transistor 615 inside the compensation unit 610, the first terminal and the gate terminal of the fifth transistor 615 can be electrically connected to the voltage source Vref, and the second terminal of the fifth transistor 615 is electrically connected to the second transistor. 312 gate terminal. In this embodiment, the voltage sources OVSS, OVDD and Vref are all fixed voltages, and the level of the voltage source OVSS is opposite to that of the voltage source OVDD, and the level of the voltage source Vref is greater than or equal to the level of the voltage source OVDD. The aforementioned voltage source OVSS is, for example, −4.4 volts, the voltage source OVDD is, for example, +4.6 volts, and the voltage source Vref is, for example, greater than or equal to +4.6 volts. Those skilled in the art can deduce the driving processes of the above two electroluminescent pixel circuits 500 and 600 from the timing content described in FIG. 4 , so details are not repeated here.

FIG. 7 is a schematic diagram of an electroluminescence pixel circuit according to another embodiment of the present invention. The electroluminescent pixel circuit 700 includes a compensation unit 710 , a switching transistor 720 and an organic light emitting diode 730 . Wherein, the organic light emitting diode 730 has an anode end and a cathode end, and the anode end of the organic light emitting diode 730 is electrically connected to the voltage source OVDD. The compensation unit 710 is electrically connected to another voltage source OVSS, and receives the control signal EM, the first scan signal S1 and the second scan signal S2 due to the electrical connection, wherein the first scan signal S1 and the second scan signal S2 The pulse enabling periods are all within the pulse enabling period of the control signal EM, and the pulse enabling period of the first scanning signal S1 is before the pulse enabling period of the second scanning signal S2 (details will be described later). The switch transistor 720 has a first terminal, a second terminal and a gate terminal. The two ends of the switch transistor 720 are electrically connected between the compensation unit 710 and the cathode terminal of the organic light emitting diode 730 , and the switch transistor 720 is turned on according to the control signal EM. Both the voltage sources OVDD and OVSS are fixed voltages, and the level of the voltage source OVDD is opposite to that of the voltage source OVSS. The voltage source OVDD is, for example, +4.6 volts, and the voltage source OVSS is, for example, -4.4 volts.

For details, please refer to FIG. 8 , which is a schematic diagram of the interior of the compensation unit. In FIG. 8 , the same symbols as those in FIG. 7 represent the same objects, voltage sources or signals. The compensation unit 810 shown in FIG. 8 includes a first transistor 811, a second transistor 812 (that is, a driving transistor), a third transistor 813, a fourth transistor 814, a fifth transistor 815, and a capacitor 816, wherein the first to fifth transistors The transistors 811 - 815 all have a first terminal, a second terminal and a gate terminal. The first terminal of the first transistor 811 is electrically connected to the second voltage source OVSS, and the gate terminal of the first transistor 811 receives the control signal EM due to the electrical connection. The first end of the second transistor 812 is electrically connected to the second end of the first transistor 811 , and the second end of the second transistor 812 is electrically connected to the first end of the switch transistor 720 . The first terminal of the third transistor 813 receives the data voltage Vdata due to the electrical connection, and the second terminal of the third transistor 813 is electrically connected to the first terminal of the second transistor 812, and the gate terminal of the third transistor 813 is The second scan signal S2 is received due to the electrical connection. The first terminal of the fourth transistor 814 is electrically connected to the second terminal of the second transistor 812, and the second terminal of the fourth transistor 814 is electrically connected to the gate terminal of the second transistor 812, and the gate terminal of the fourth transistor 814 Then, the second scan signal S2 is received due to the electrical connection. Both the first terminal and the gate terminal of the fifth transistor 815 are electrically connected to the voltage source OVSS, and the second terminal of the fifth transistor 815 is electrically connected to the gate terminal of the second transistor 812 . One end of the capacitor 816 is electrically connected to receive the first scan signal S1 , and the other end of the capacitor 816 is electrically connected to the gate end of the second transistor 812 .

In this embodiment, the first transistor 811 , the second transistor 812 , the third transistor 813 , the fourth transistor 814 , the fifth transistor 815 and the switch transistor 720 are all implemented by NMOS transistors. The timing of the first scan signal S1 , the second scan signal S2 and the control signal EM in FIG. 8 will be described below by taking the NMOS transistor as an example.

FIG. 9 is a timing diagram of some signals of the electroluminescence pixel circuit shown in FIG. 8 . In FIG. 9 , the same symbols as those in FIG. 8 represent the same signals, and the symbol V _A is the potential of node A shown in FIG. 8 . It can be seen from FIG. 9 that during the period T1-T5, the pulse enabling periods of the first scanning signal S1 and the second scanning signal S2 are both within the pulse enabling period of the control signal EM, and the pulse enabling period of the first scanning signal S1 The pulse enabling period is before the pulse enabling period of the second scan signal S2. Wherein, in time T1 and time T5, the time interval between the falling edge of the control signal EM and the falling edge of the first scanning signal S1 is used to buffer the time required for the first scanning signal S1 to change from a high level to a low level, and The interval between the rising edge of the control signal EM and the falling edge of the second scanning signal S2 is used to buffer the time required for the second scanning signal S2 to change from a high level to a low level, so that the first scanning can be ensured. Both the pulse enabling periods of the signal S1 and the second scanning signal S2 are within the pulse enabling period of the control signal EM.

Although, in the present embodiment, the rising edge of the first scanning signal S1 and the rising edge of the second scanning signal S2 are overlapped, but in some embodiments, the rising edge of the first scanning signal S1 and the The rising edges of the second scanning signal S2 may also be non-overlapping. That is to say, after the first scan signal S1 transitions from a low level to a high level, the second scan signal S2 starts to transition from a low level to a high level. Therefore, whether the rising edge of the first scanning signal S1 overlaps with the rising edge of the second scanning signal S2, only the pulse enabling periods of the first scanning signal S1 and the second scanning signal S2 are within the pulse of the control signal EM. During the enabling period, the electroluminescence pixel circuit can be operated normally, and the present invention can be realized. The signal implementations listed above are only used as examples, and the present invention is not limited thereto.

Please refer to FIG. 9 again. Those skilled in the art can learn from the timing content described in the electroluminescence pixel circuit 300 of the foregoing embodiment, and according to the first scan signal S1, the second scan signal S2 and the first scan signal S2 shown in FIG. The timing sequence of the control signal EM is used to derive the driving process of the electroluminescent pixel circuit 800 in FIG. 8 , so details will not be repeated here.

FIG. 10 is a schematic diagram of an electroluminescent pixel circuit according to an embodiment of the present invention. The electroluminescence pixel circuit 1000 is mainly composed of a light emitting element 1001, a switching transistor 1002, a first transistor 1003, a second transistor 1004, a third transistor 1005, a fourth transistor 1006, a fifth transistor 1007, a capacitor C1 and a capacitor C2. As shown in the figure, the cathode terminal of the light emitting element 1001 is electrically connected to the voltage source OVSS. The second terminal of the switch transistor 1002 is electrically connected to the anode terminal of the light emitting element 1001, and the gate terminal of the switch transistor 1002 is used for receiving the control signal EM. The first terminal of the first transistor 1003 is electrically connected to the voltage source OVDD, and the gate terminal of the first transistor 1003 is used for receiving the control signal EM. The first terminal of the second transistor 1004 is electrically connected to the second terminal of the first transistor 1003 , and the second terminal of the second transistor 1004 is electrically connected to the first terminal of the switch transistor 1002 . The first terminal of the third transistor 1005 is electrically connected to the second terminal of the second transistor 1004, the second terminal of the third transistor 1005 is electrically connected to the gate terminal of the second transistor 1004, and the gate terminal of the third transistor 1005 is used for to receive the first scanning signal S1. The first terminal of the fourth transistor 1006 is used to receive the data voltage Vdata, the second terminal of the fourth transistor 1006 is electrically connected to the gate terminal of the second transistor 1004, and the gate terminal of the fourth transistor 1006 is used to receive the third scanning Signal S3. The first end of the fifth transistor 1007 is electrically connected to the voltage source OVDD, the second end of the fifth transistor 1007 is electrically connected to the second end of the second transistor 1004, and the gate end of the fifth transistor 1007 is used to receive the first A scanning signal S1. The capacitor C1 is electrically connected between the gate terminal of the second transistor 1004 and the first terminal of the second transistor 1004 . The capacitor C2 is electrically connected between the first end of the second transistor 1004 and the second scan signal S2. Both the voltage sources OVDD and OVSS are fixed voltages, and the level of the voltage source OVDD is opposite to that of the voltage source OVSS. The voltage source OVDD is, for example, +4.6 volts, and the voltage source OVSS is, for example, -4.4 volts. In addition, the light emitting element 1001 in this embodiment is realized by an organic light emitting diode.

In this embodiment, the switch transistor 1002 , the first transistor 1003 , the second transistor 1004 , the third transistor 1005 , the fourth transistor 1006 and the fifth transistor 1007 are all implemented by PMOS transistors. Taking the PMOS transistor as an example, the timing of the first scan signal S1 , the second scan signal S2 , the third scan signal S3 and the control signal EM in FIG. 10 will be described below.

FIG. 11 is a timing diagram of some signals of the electroluminescence pixel circuit shown in FIG. 10 . As shown in the figure, the times T1 to T4 are respectively represented as a reset period, a compensation period, a data writing period and a light emitting period of the electroluminescence pixel circuit. The first scan signal S1 is at the first level during the reset period (ie, time T1) and the compensation period (ie, time T2), and the first scan signal S1 is at the first level during the data writing period (ie, time T3) and the light emitting period (ie, time T4). ) is at the second level. The second scan signal S2 is at the first level during the reset period (ie time T1 ), and transitions from the first level to the second level at the beginning of the compensation period (ie time T2 ). The third scan signal S3 is at the second level during the reset period (ie time T1), the compensation period (ie time T2) and the light emitting period (ie time T4), and the third scan signal S3 is at the second level during the data writing period (ie time T3 ) is in the first position. The control signal EM is at the second level during the reset period (i.e. time T1), the compensation period (i.e. time T2) and the data writing period (i.e. time T3), and the control signal EM is at the second level during the light emitting period (i.e. time T4). First place. In this embodiment, the first level is a logic low level state, and the second bit criterion is a logic high level state.

In detail, when the electroluminescent pixel circuit 1000 is in the reset period (namely time T1), the first scan signal S1 and the second scan signal S2 both exhibit a logic low level state, while the third scan signal S3 and the control signal EM All present a logic high level state, so that the switch transistor 1002 , the first transistor 1003 , the second transistor 1004 and the fourth transistor 1006 are all off, and the third transistor 1005 and the fifth transistor 1007 are all on. At this time, the voltage source OVDD is provided to the capacitor C1 through the turned-on fifth transistor 1007 and the turned-on third transistor 1005 so that the potential of the node A is approximately DVDD.

Next, when the electroluminescence pixel circuit 1000 is in the compensation period (ie time T2), the first scan signal S1 is in a logic low state, and the second scan signal S2, the third scan signal S3 and the control signal EM are all in a logic high state. The quasi-state makes the switching transistor 1002, the first transistor 1003 and the fourth transistor 1006 all in the off state, and the second transistor 1004, the third transistor 1005 and the fifth transistor 1007 are all in the on state. At this time, the potential of the node A is approximately DVDD, and the potential of the first terminal of the second transistor 1004 is approximately DVDD+|V _TH |, so the potential of the node A is higher than the potential of the first terminal of the second transistor 1004 When low, the second transistor 1004 is on. When the electroluminescent pixel circuit 1000 is in the data writing period (time T3), the first scan signal S1, the second scan signal S2 and the control signal EM all exhibit a logic high level state, while the third scan signal S3 exhibits a logic state. In the low level state, the switching transistor 1002 , the first transistor 1003 , the third transistor 1005 and the fifth transistor 1007 are all turned off, and the second transistor 1004 and the fourth transistor 1006 are all turned on. At this time, the potential of the node A is approximately the data voltage Vdata received by the first terminal of the fourth transistor 1006, and the potential of the first terminal of the second transistor 1004 is approximately DVDD+| _VTH |+α(Vdata-DVDD). Among them, α is the ratio between the two capacitors C1 and C2, which is

$\mathrm{<span\; class="notranslate">\; \&alpha;</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}$

Finally, when the electroluminescent pixel circuit 1000 is in the light-emitting period (time T4), the first scan signal S1, the second scan signal S2 and the third scan signal S3 all exhibit a logic high level state, while the control signal EM exhibits a logic state. In the low level state, the switch transistor 1002 , the first transistor 1003 and the second transistor 1004 are all on, and the third transistor 1005 , the fourth transistor 1006 and the fifth transistor 1007 are all off. At this time, the potential of the first terminal of the second transistor 1004 is approximately OVDD, and the potential of the node A is approximately Vdata−| _VTH |+α(DVDD−Vdata). In this way, the second transistor 1004 can generate a pixel current I _oled according to the potential difference between its first terminal and its gate terminal to drive the light emitting element 1001 to light up.

Based on the above, the pixel current I _oled =1/2*K*(V _sg −|V _TH |) ² flowing through the light emitting element 1001 . At this time, the potential difference V _sg between the first terminal and the gate terminal of the second transistor 1004 is respectively the voltage source OVDD and the potential Vdata-|V _TH |+α(DVDD-Vdata) of the voltage source OVDD, so it flows through the light-emitting element 1001 The pixel current is I _oled =1/2*K*{OVDD-[Vdata-|V _TH |+α(DVDD-Vdata)]-|V _TH |} ² =1/2*K*[(1- α)*(OVDD–Vdata)] ² . It can be seen from this that the pixel current I _oled flowing through the light emitting element 1001 is only related to the voltage source OVDD and the data voltage Vdata, but not to the threshold voltage V _TH of the second transistor 1004 (ie, the driving transistor). In this way, the problem of panel display unevenness caused by the influence of the manufacturing process of the light-emitting element on the threshold voltage of the driving transistor can be effectively improved, so that the electroluminescence display pixel of this embodiment can display images. The critical voltage is compensated, and it can still maintain a good display quality under long-term use.

In addition, in some embodiments, the above-mentioned electroluminescence display pixel can also be slightly improved, which is illustrated by FIG. 12 . FIG. 12 is a schematic diagram of an electroluminescent pixel circuit according to another embodiment of the present invention. In FIG. 12 , the same symbols as those in FIG. 10 represent the same elements, voltage sources or signals. The difference between the electroluminescent display pixel 1200 shown in FIG. 12 and the electroluminescent display pixel 1000 shown in FIG. 10 is that the first terminal of the fifth transistor 1207 in the electroluminescent display pixel 1200 is electrically connected to the voltage source OVDD, and the second terminal of the fifth transistor 1207 is electrically connected to the first terminal of the third transistor 1005 . As for the detailed driving process of the electroluminescent display pixel 1200 , those skilled in the art can deduce it from the timing content described in FIG. 11 , so details are not repeated here.

FIG. 13 is a schematic diagram of an electroluminescent pixel circuit according to another embodiment of the present invention. The difference between the electroluminescent pixel circuit 1300 shown in FIG. 13 and the electroluminescent display pixel 1000 shown in FIG. The second transistor 1304 , the third transistor 1305 , the fourth transistor 1306 and the fifth transistor 1307 are formed. Wherein, these transistors are implemented by using NMOS transistors. As shown in the figure, the anode terminal of the light emitting element 1301 is electrically connected to the voltage source OVDD. The first terminal of the switch transistor 1302 is electrically connected to the cathode terminal of the light emitting element 1301, and the gate terminal of the switch transistor 1302 is used for receiving the control signal EM. The second terminal of the first transistor 1303 is electrically connected to the voltage source OVSS, and the gate terminal of the first transistor 1303 is used for receiving the control signal EM. The first terminal of the second transistor 1304 is electrically connected to the second terminal of the switch transistor 1302 , and the second terminal of the second transistor 1304 is electrically connected to the first terminal of the first transistor 1303 . The first terminal of the third transistor 1305 is electrically connected to the second terminal of the second transistor 1304, the second terminal of the third transistor 1305 is electrically connected to the gate terminal of the second transistor 1304, and the gate terminal of the third transistor 1305 is Used to receive the first scanning signal S1. The first terminal of the fourth transistor 1306 is used to receive the data voltage Vdata, the second terminal of the fourth transistor 1306 is electrically connected to the gate terminal of the second transistor 1304, and the gate terminal of the fourth transistor 1306 is used to receive the third scanning Signal S3. The first end of the fifth transistor 1307 is electrically connected to the voltage source OVSS, the second end of the fifth transistor 1307 is electrically connected to the second end of the second transistor 1004, and the gate end of the fifth transistor 1307 is used to receive the first A scanning signal S1. The capacitor C1 is electrically connected between the gate terminal of the second transistor 1304 and the first terminal of the second transistor 1304 . The capacitor C2 is electrically connected between the first end of the second transistor 1304 and the second scan signal S2. Both the voltage sources OVDD and OVSS are fixed voltages, and the level of the voltage source OVDD is opposite to that of the voltage source OVSS. The voltage source OVDD is, for example, +4.6 volts, and the voltage source OVSS is, for example, -4.4 volts. In addition, the light emitting element 1301 in this embodiment is realized by an organic light emitting diode.

FIG. 14 is a timing diagram of some signals of the electroluminescence pixel circuit shown in FIG. 13 . As shown in the figure, the times T1 to T4 are respectively represented as a reset period, a compensation period, a data writing period and a light emitting period of the electroluminescence pixel circuit. The first scan signal S1 is at the first level during the reset period (ie, time T1) and the compensation period (ie, time T2), and the first scan signal S1 is at the first level during the data writing period (ie, time T3) and the light emitting period (ie, time T4). ) is at the second level. The second scan signal S2 is at the first level during the reset period (ie time T1 ), and transitions from the first level to the second level at the beginning of the compensation period (ie time T2 ). The third scan signal S3 is at the second level during the reset period (ie time T1), the compensation period (ie time T2) and the light emitting period (ie time T4), and the third scan signal S3 is at the second level during the data writing period (ie time T3 ) is in the first position. The control signal EM is at the second level during the reset period (i.e. time T1), the compensation period (i.e. time T2) and the data writing period (i.e. time T3), and the control signal EM is at the second level during the light emitting period (i.e. time T4). First place. In this embodiment, the first level is a logic high level state, and the second bit criterion is a logic low level state. As for the detailed driving process of the electroluminescence display pixel 1300 , those skilled in the art can deduce it from the timing content described in FIG. 11 , so details are not repeated here.

To sum up, the main method of the present invention to solve the aforementioned problems is to design the electroluminescent pixel circuit structure so that the magnitude of the pixel current flowing through the organic light-emitting diode or light-emitting element is related to the voltage source and the data voltage , completely independent of the threshold voltage of the driving transistor. Therefore, the electroluminescence pixel circuit proposed by the embodiment of the present invention can effectively improve the problem of panel display unevenness, so as to provide a high-quality display image, thereby achieving the purpose of the present invention.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore The scope of protection of the present invention should be defined by the scope of protection of the appended claims.

Claims (10)

1. An electroluminescent pixel circuit, characterized in that, comprising: An organic light emitting diode has an anode end and a cathode end, and the cathode end of the organic light emitting diode is electrically connected to a first voltage source; A compensation unit, electrically connected to a second voltage source, and used to receive a control signal, a first scan signal and a second scan signal, the pulse enabling periods of the first scan signal and the second scan signal are both not within the pulse-enabled period of the control signal, and the pulse-enabled period of the first scan signal is before the pulse-enabled period of the second scan signal; and A switch transistor, the switch transistor has a first terminal, a second terminal and a gate terminal, the two terminals of the switch transistor are electrically connected between the compensation unit and the anode terminal of the organic light emitting diode, and according to the A control signal turns on the switching transistor, wherein both the first voltage source and the second voltage source are fixed voltages, and the level of the first voltage source is opposite to that of the second voltage source; Among them, the compensation unit includes: A first transistor, the first transistor has a first terminal, a second terminal and a gate terminal, the first terminal of the first transistor is electrically connected to the second voltage source, and the first transistor of the first transistor The gate terminal is used to receive the control signal; A second transistor, the second transistor has a first terminal, a second terminal and a gate terminal, the first terminal of the second transistor is electrically connected to the second terminal of the first transistor, the second the second end of the transistor is electrically connected to the first end of the switching transistor; A third transistor, the third transistor has a first terminal, a second terminal and a gate terminal, the first terminal of the third transistor is used to receive a data voltage, the second terminal of the third transistor is electrically Sexually connected to the first end of the second transistor, and the gate end of the third transistor is used to receive the second scan signal; A fourth transistor, the fourth transistor has a first end, a second end and a gate end, the first end of the fourth transistor is electrically connected to the second end of the second transistor, the fourth The second terminal of the transistor is electrically connected to the gate terminal of the second transistor, and the gate terminal of the fourth transistor is used for receiving the second scan signal; A fifth transistor, the fifth transistor has a first terminal, a second terminal and a gate terminal, both the first terminal and the gate terminal of the fifth transistor are electrically connected to the second voltage source, the first the second terminal of five transistors is electrically connected to the gate terminal of the second transistor; and A first capacitor, one end of the first capacitor is used to receive the first scan signal, and the other end is electrically connected to the gate end of the second transistor. 2. The electroluminescent pixel circuit according to claim 1, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the switch transistor are all the same type. 3. The electroluminescent pixel circuit according to claim 1, wherein the compensation unit further comprises a second capacitor, the second capacitor is electrically connected to the second terminal and the gate terminal of the fourth transistor between. 4. The electroluminescence pixel circuit according to claim 1, wherein during a first period, the control signal, the first scan signal and the second scan signal have a first level, During a second stage period, the first scan signal and the second scan signal have a second level, while the control signal has the first level, and during a third stage period, the first scan signal The second scan signal has the second level, while the control signal has the first level, and the polarity of the first level is opposite to that of the second level. 5. An electroluminescent pixel circuit, characterized in that it comprises: An organic light emitting diode has an anode end and a cathode end, and the cathode end of the organic light emitting diode is electrically connected to a first voltage source; A switch transistor, the switch transistor has a first terminal, a second terminal and a gate terminal, the second terminal of the switch transistor is electrically connected to the anode terminal of the organic light emitting diode, the gate terminal of the switch transistor is used for receiving a control signal, and turning on the switching transistor according to the control signal; A first transistor, the first transistor has a first terminal, a second terminal and a gate terminal, wherein the first terminal of the first transistor is electrically connected to a second voltage source, and the first transistor of the first transistor The gate terminal is used to receive the control signal; A second transistor, the second transistor has a first terminal, a second terminal and a gate terminal, wherein the first terminal of the second transistor is electrically connected to the second terminal of the first transistor, the first terminal the second terminal of the second transistor is electrically connected to the first terminal of the switching transistor; A third transistor, the third transistor has a first terminal, a second terminal and a gate terminal, wherein the first terminal of the third transistor is used to receive a data voltage, the second terminal of the third transistor electrically connected to the first terminal of the second transistor, and the gate terminal of the third transistor is used to receive a second scan signal; A fourth transistor, the fourth transistor has a first terminal, a second terminal and a gate terminal, wherein the first terminal of the fourth transistor is electrically connected to the second terminal of the second transistor, the first terminal The second terminal of the four transistors is electrically connected to the gate terminal of the second transistor, and the gate terminal of the fourth transistor is used for receiving the second scan signal; A fifth transistor, the fifth transistor has a first end, a second end and a gate end, the first end of the fifth transistor and the gate end of the fifth transistor are electrically connected to the second a voltage source, the second terminal of the fifth transistor is electrically connected to the gate terminal of the second transistor; and A first capacitor, one end of the first capacitor is used to receive a first scan signal, and the other end of the first capacitor is electrically connected to the gate end of the second transistor. 6. The electroluminescent pixel circuit as claimed in claim 5, further comprising a second capacitor electrically connected between the second terminal of the fourth transistor and the gate terminal. 7. An electroluminescent pixel circuit, characterized in that it comprises: A light-emitting element has an anode end and a cathode end, and the cathode end of the light-emitting element is electrically connected to a first voltage source; A switch transistor, the switch transistor has a first terminal, a second terminal and a gate terminal, the second terminal of the switch transistor is electrically connected to the anode terminal of the light emitting element, and the gate terminal of the switch transistor is used to receive a control signal; A first transistor, the first transistor has a first terminal, a second terminal and a gate terminal, the first terminal of the first transistor is electrically connected to a second voltage source, and the first transistor of the first transistor The gate terminal is used to receive the control signal; A second transistor, the second transistor has a first terminal, a second terminal and a gate terminal, the first terminal of the second transistor is electrically connected to the second terminal of the first transistor, and the first The second end of the second transistor is electrically connected to the first end of the switching transistor; A third transistor, the third transistor has a first end, a second end and a gate end, the first end of the third transistor is electrically connected to the second end of the second transistor, the third The second terminal of the transistor is electrically connected to the gate terminal of the second transistor, and the gate terminal of the third transistor is used to receive a first scan signal; A fourth transistor, the fourth transistor has a first terminal, a second terminal and a gate terminal, the first terminal of the fourth transistor is used to receive a data voltage, the second terminal of the fourth transistor is electrically Sexually connected to the gate terminal of the second transistor, and the gate terminal of the fourth transistor is used to receive a third scan signal; A fifth transistor, the fifth transistor has a first terminal, a second terminal and a gate terminal, the first terminal of the fifth transistor is electrically connected to the second voltage source, the first terminal of the fifth transistor two terminals are electrically connected to the second terminal of the second transistor, and the gate terminal of the fifth transistor is used for receiving the first scan signal; a first capacitor electrically connected between the gate terminal of the second transistor and the first terminal of the second transistor; and A second capacitor electrically connected between the first end of the second transistor and a second scan signal. 8. The electroluminescence pixel circuit according to claim 7, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the switching transistor are all of the same type transistor. 9. The electroluminescence pixel circuit according to claim 7, wherein the first voltage source and the second voltage source are both fixed voltages, and the level of the first voltage source is opposite to the second voltage source level. 10. The electroluminescent pixel circuit according to claim 7, further comprising a reset period, a compensation period, a data writing period, and a light emitting period, wherein the first scan signal is The setting period and the compensation period are at a first level, and the first scan signal is at a second level during the data writing period and the light emitting period; the second scan signal is at the first level during the reset period, and the second scan signal transitions from the first level to the second level at the beginning of the compensation period; the third scan signal is at the second level during the reset period, the compensation period and the light emitting period, and the third scan signal is at the first level during the data writing period; and The control signal is at the second level during the reset period, the compensation period and the data writing period, and the control signal is at the first level during the light emitting period.