CN103472782B - A kind of distributed time sequence trigger control system - Google Patents
A kind of distributed time sequence trigger control system Download PDFInfo
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- CN103472782B CN103472782B CN201310392637.5A CN201310392637A CN103472782B CN 103472782 B CN103472782 B CN 103472782B CN 201310392637 A CN201310392637 A CN 201310392637A CN 103472782 B CN103472782 B CN 103472782B
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Abstract
The invention discloses a kind of distributed time sequence trigger control system, comprise multiple time schedule controller and the optical fiber connecting into tree network; Also comprise one and trigger input, a clock input and an anxious stopping transportation enter; All outputs of each time schedule controller can provide clock or triggering to other equipment, or be connected to other time schedule controller clock or trigger input.If only use the function that sequential triggers, and during without the need to Precision Clock Synchronization, only the triggering of a node can be exported and couple together, without the need to connecting clock signal with the triggering input of another node.The present invention adopts tree network and optical fiber to achieve distributed system architecture, reduces the impact of electromagnetic interference (EMI), reduces wiring difficulty; High-precision sequential can be provided to trigger and clock signal to large-scale physics facility.
Description
Technical field
The invention belongs to large-scale physics facility field, more specifically, relate to a kind of distributed time sequence trigger control system.
Background technology
Large-scale physics facility, such as large-scale linear accelerator, tokamak fusion assay device, they all include a lot of subsystem and instrument and equipment, need do not entering different running statuses in the same time accurately.Therefore need a set of sequential control system, after program presets the time, send trigger pip to other equipment.The sequential triggering system of the large-scale physics facility use of special supply in the market.A lot of large-scale experimental device, takes to use modular instrument, as CPCI, PXI bus apparatus adds corresponding crate controller, then coordinates upper input/output interface module to form the sequential triggering system of a centralized configuration.
Along with the increase of unit scale, various equipment is distributed in different physical locations, the large-scale physics facility of part has used distributed system architecture, if sequential triggering system still adopts above-mentioned centralized configuration, a large amount of trigger pips is sent to one by one the subsystem in each place, wiring difficulty is large, cost is high, and system architecture is complicated, maintenance difficulties is large.
Meanwhile, strong electromagnetic interference (EMI) is often produced when large-scale physics facility is tested.In electromagnetic environment severe at the scene, use the modular instrument that above-mentioned business is general, owing to not being be this environment specialized designs, sequential triggering system stability can be subject to certain impact.Because these apparatus structures are complicated, be disturbed the operation result that rear easy appearance is unpredictable.
Summary of the invention
For above defect or the Improvement requirement of prior art, the invention provides a kind ofly can provide high-precision sequential to trigger and the distributed time sequence trigger control system of clock signal for large-scale physics facility.
The invention provides a kind of distributed time sequence trigger control system, comprise multiple time schedule controller and multiple time schedule controller is connected into the optical fiber of tree network; Each time schedule controller is used for providing clock signal or trigger pip.
Further, described time schedule controller also comprises Ethernet interface, for being connected with Ethernet.
Further, described time schedule controller comprises: mainboard, and the power module be connected with mainboard is arranged on the communication module on mainboard and sequence generation module, the first input/output board be connected with mainboard and the second input/output board; Power module is used for providing direct current supply for described time schedule controller; Described communication module is used for the instruction being used for the operation of Control timing sequence controller of ether transfers on network to pass to sequence generation module, and the running status of described sequence generation module is issued over ethernet; Described sequence generation module is used for generated clock signal and trigger pip; Described first input/output board and described second input/output board are used for the light signal of outside being converted to electric signal and passing to described sequence generation module, or the electric signal that described sequence generation module exports are converted to light signal and export.
Further, described sequence generation module comprises: clock generating module, serial communication module, controller, counter array, output control module and bus; Described serial communication module, described controller is all connected on the bus with described counter array and passes through bus transfer data; Described controller is connected respectively by control line with described serial communication module, described counter array, described clock generating module and described output control module and controls it; During work, by serial communication module and external communication; When receiving instruction described serial communication module by instruction and time sequence parameter configuration by described bus transfer to controller, the running status of controller is transferred to outside communication module simultaneously; The operation of described other modules of controller coordinate; Described output control module opens or closes the output of some passages under the control of described controller; Described clock generating module produces the clock signal that described counter array needs; The clock of described counter array to described clock generating module counts, and produce required for trigger pip and clock signal.
Further, described clock generating module also comprises: trigger port, for receiving the trigger pip of outside input; Clock port, for receiving the clock signal of outside input, and suddenly stopping port, stopping control signal for the urgency receiving outside input.
The present invention adopts tree network and optical fiber to achieve distributed system architecture, reduces the impact of electromagnetic interference (EMI), reduces wiring difficulty; High-precision sequential can be provided to trigger and clock signal to large-scale physics facility.
Accompanying drawing explanation
Fig. 1 is the one-piece construction schematic diagram of the distributed time sequence trigger control system that the embodiment of the present invention provides;
Fig. 2 is time schedule controller internal hardware schematic diagram in the distributed time sequence trigger control system that provides of the embodiment of the present invention;
Fig. 3 is sequence generation module internal module structural representation in the time schedule controller that provides of the embodiment of the present invention;
Fig. 4 is the physical circuit figure of input/output module in the distributed time sequence trigger control system that provides of the embodiment of the present invention.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.In addition, if below in described each embodiment of the present invention involved technical characteristic do not form conflict each other and just can mutually combine.
The distributed time sequence trigger control system that the embodiment of the present invention provides is mainly used in as large-scale experimental device provides clocked flip and clock synchronous; Can accurate sequential be provided to trigger and clock for the instrument and equipment in each subsystem in large-scale physics facility (as particle accelerator, tokamak device).
Fig. 1 shows the one-piece construction of the distributed time sequence trigger control system that the embodiment of the present invention provides, and for convenience of explanation, illustrate only the part relevant to the embodiment of the present invention, details are as follows:
Distributed time sequence trigger control system comprises: multiple time schedule controller and multiple time schedule controller is connected into the optical fiber of tree network; Each time schedule controller is used for providing clock signal or trigger pip.
In embodiments of the present invention, distribution type fiber-optic sequential triggering system is primarily of the optical fiber composition of multiple time schedule controller 1 together with connecting; Also comprise one simultaneously and trigger input, a clock input, and an anxious stopping transportation enters.All outputs of each time schedule controller can provide clock or triggering to other equipment, or be connected to other time schedule controller 1 clock or trigger input, multiple time schedule controller can form tree network.If when setting up tree network, only use the function that sequential triggers, and during without the need to Precision Clock Synchronization, can only the triggering input of the triggering of node output and another node be coupled together, without the need to connecting clock signal.Time schedule controller 1 has an Ethernet interface, can be connected with Ethernet 2 by this Ethernet interface, operating personnel can monitor the duty of all time schedule controllers, the clock configuring each passage and trigger parameter, startup or out of service by using computing machine.After time schedule controller configures into, if there is trigger pip to be input to the trigger input of this controller, or receive the instruction brought into operation that Ethernet transmits, controller just brings into operation, and triggers or clock according to default generation.Stop immediately exporting after receiving emergent stop signal.A time schedule controller can trigger other time schedule controller by output thus realize distributed system architecture.
Because native system uses optical fiber to realize distributed system architecture, optical fiber can long range propagation signal interference-free, each sequential nodal distance can wide apart, and node can be distributed in experimental provision everywhere, reduces wiring difficulty.High-precision sequential can be provided to trigger and clock signal to large-scale physics facility.The present invention adopts tree network to realize distributed frame; All time schedule controllers, by Fiber connection, can reduce the impact of electromagnetic interference (EMI).In whole system, all time schedule controllers are all identical, do not have dividing of primary and secondary.The all triggering input and output of each sequential node all adopt optical signal transmission, can directly connecting fiber use, without the need to conversion; High-precision sequential can be provided to trigger and clock signal for large-scale physics facility.
In embodiments of the present invention, the inner structure of time schedule controller 1 as shown in Figure 2, time schedule controller 1 comprises mainboard 10, the power module 11 be connected with mainboard 10, be arranged on the communication module 12 on mainboard 10 and sequence generation module 13, the first input/output board 14 and the second input/output board 15 be connected with mainboard 10; Power module 11 is for providing direct current supply for time schedule controller 1, and mainboard 10 is mainly used for realizing installing communication module 12 and sequence generation module 13, mainboard 10 has this auxiliary circuit needed for two modules and the interface being connected other modules.Communication module 12 is microprocessors, for realizing network communicating function, the instruction on Ethernet is passed to sequence generation module 13 by serial ports, and the state of sequence generation module 13 is issued over ethernet.Sequence generation module 13 is for realizing clock and triggering the generation exported; The light signal in the external world to be converted to electrical signal transfer to sequence generation module 13 or its electric signal is converted to light signal and exports by photoelectric switching circuit by the first input/output board 14 and the second input/output board 15.During work, power module 11 provides direct current supply for time schedule controller 1, and the instruction that Control timing sequence controller runs that is used for of ether transfers on network is passed to sequence generation module by communication module 12; Instruction comprises configuration and the start and stop operation of operational factor.And the running status of described sequence generation module is issued over ethernet, acceptable instruction comprises the configuration of module operational factor, starts and stops, and Query Running Status, and whether state mainly contains runs and operational mode.Sequence generation module 13 generated clock signal and trigger pip; First input/output board 14 and the second input/output board 15, by the light signal of outside, are specially triggering, clock, suddenly stop input signal.Be converted to electric signal and pass to described sequence generation module, or the electric signal that sequence generation module 13 exports be converted to light signal and export.
Each time schedule controller is inner by sequence generation module, and input/output module and communication module are formed jointly.Sequence generation module uses Programmable Logic Controller to realize, and does not run any software program, and all functions, by hardware implementing, improve the stability of sequential node.Input/output module, is responsible for fiber-optic signal input and output.Communication module is responsible for ethernet communication.Each node can simultaneously output multi-channel trigger pip, or multipath clock signal.The Time-delayed trigger that can realize adjustable pulse width exports, also can performance period adjustable clock signal export.A time schedule controller can trigger other time schedule controllers of expection connection, thus can pass through digital display real-time performance distributed frame.Time schedule controller connects Ethernet by communication module, just can all time schedule controller of Monitor and Control by a computing machine, configures its clock zone trigger parameter, and can control it and start, terminate to run.Sequential node also has an anxious stopping transportation enter, after receiving emergent stop signal, all triggerings can be stopped within a cycle of operation to export.What time schedule controller hardware device adopted is standard 19 inch rack 2U cabinet, is convenient to be arranged in rack.
As one embodiment of the present of invention, sequence generation module 13 can be a programmable logic device (PLD), as FPGA, CPLD.Sequence generation module 13 is for realizing clock and triggering the generation exported.The structure of sequence generation module 13 inside as shown in Figure 3; Sequence generation module 13 comprises clock generating module 131, serial communication module 132, controller 133, counter array 134, output control module 135 and bus 136; Serial communication module 132, controller 133 is all connected by bus 136 with counter array 134, and with Time Controller 133, by the control pair that is connected with them, they control; Output control module 135 is connected with counter array 134; Clock generating module 131 and output control module 135 is connected by control line with Time Controller 133.Instruction and time sequence parameter configures by serial communication module 132 and pass to controller 133 with outside communication module 12 communication by bus 136 by sequence generation module 13, the instruction of controller 133 are passed to the communication module 12 of outside by serial ports simultaneously.Controller 133 is for coordinating the operation of other modules.The clock that clock generating module 131 needs for generation of counter array 134.Output control module 135 can open or close the output of some passages under the control of controller 133.Counter array 134 produces required triggering and clock by counting the clock of clock generating module 131.During work, by serial communication module 132 and external communication; When receiving instruction, instruction and time sequence parameter configuration are passed to controller by serial communication module 132 by described bus by described communication module, the running status of controller 133 are passed to outside communication module by serial communication module 132 simultaneously; The operation of other modules coordinated by controller 133; Output control module 135 opens or closes the output of some passages under the control of controller 133; Clock generating module 131 produces the clock signal that counter array 134 needs; The clock that the counter array 134 pairs of clock generating module 131 produce counts, and trigger pip required for producing and clock signal.
As one embodiment of the present of invention, clock generating module 131 also comprises: trigger port, for receiving the trigger pip of outside input; Clock port, for receiving the clock signal of outside input, and suddenly stopping port, stopping control signal for the urgency receiving outside input.
The distributed time sequence trigger control system that the embodiment of the present invention provides has the following advantages: (1) present system is distributed frame, sequential node can be placed near the equipment of needs triggering, as same interior of equipment cabinet, reduce wiring difficulty and maintenance difficulties.(2) the present invention adopts tree structure network to connect, each time schedule controller hardware is identical, the output of each time schedule controller both can give the sequential node needing triggering and the equipment use of clock also can be connected other, do not need other equipment namely can realize networking, make networking more flexible.(3) output of sequential node of the present invention both can export triggering, also can output clock, adopted double counters to realize the adjustable pulse width triggered simultaneously.(4) duty of sequential node of the present invention can be monitored by Ethernet, and clock configures with triggering, and mode of operation can be configured by Ethernet.The operation of node is started or stoped by Ethernet.(5) input and output that the present invention is all are optical fiber input and output, export without the need to increasing isolation or photoelectric conversion device, can ensure that long-distance transmissions is reliable, without interruption under large-scale experimental device forceful electric power gas interference environment.(6) in the present invention, time schedule controller switches on power and can to use with Ethernet, and hardware uses 19 inch rack designs simultaneously, easy for installation.Hardware cost of the present invention is extremely low, if use the system of modular instrument exploitation said function, cost is approximately more than 20 times of the present invention.(7) generation of all sequential triggerings of the present invention is by programmable logic device (PLD) as FPGA produces, and does not have software to participate in, ensure that high precision and the reliability of timing.
In order to the distributed time sequence trigger control system that the further description embodiment of the present invention provides, now in conjunction with instantiation, details are as follows:
Power module 11 can adopt common (5V, 10A) switch power module to be that time schedule controller is powered.Other all modules connect by mainboard 10, provide necessary power supply and interface.Communication module 12 uses the CortexM4 processor module with Ethernet interface to realize.Processor module runs .NETMicroFramework program, for realizing network communicating function.Message on Ethernet is passed to sequence generation module 13 by serial ports by this inside modules program, and the message that sequence generation module 13 is sent by serial ports is passed to the computing machine of specifying by Ethernet.Sequence generation module 13 can be made up of, as automatic configuration circuit the peripheral circuit of a Cyclon3FPGA chip and its necessity.Sequence generation module 13 is installed on mainboard.The serial communication modular 132 of sequence generation module 13FPGA inside carries out School Affairs inspection by the message received, to the message sent can carry out calculation check and, and have the ability of buffering input and output message.Serial communication modular 132 is by bus 136 and other model calling.Controller 133 manages the duty of other modules, such as, the data of serial communication modular 132 are transferred to counter array 134, controls clock generating module 131 and output control module 135.Controller is sent to communication module 12 by serial communication module 132 the running status of oneself.There are 64 32 digit counters counter array 134 inside, and each passage has two 32 digit counters, under normal Counts pattern, realizes Time delay and pulse-width regulated by counting.Change mode of operation, make in passage counter works can also produce square wave under automatic heavily loaded pattern, export for clock.64 counters are one group with 32, and every 16 passages share a kind of mode of operation.The precision that clock zone triggers can reach 1 microsecond.Clock generating module 131 can use the clock of sequence generation module 13 self under the control of controller 133, or external clock input signal produces the clock signal of counter needs.The trigger pip of outside and emergent stop signal are passed to controller 133, controller 133 can according to the start and stop of these signal control counter arrays 134 simultaneously.Output control module 135 under the control of the controller can closed portion output signal.First input/output board 14 and the second input/output board 15 are connected to this interface on sequential node mainboard by winding displacement.Two pieces of input/output boards are slightly different, the first input/output board 14 have 3 road input signals, and be respectively clock input, trigger input, anxious stopping transportation enters.Two pieces of Dou You 16 road light output, each output channel of the corresponding sequence generation module 13 in each road, can output clock, or trigger pip.
As shown in Figure 4, the key of input/output board is light output circuit.The circuit theory diagrams of two output channels are shown in Fig. 4.What optical fiber exported employing is HFBR-1414 optical fiber output module.Two HFBR-1414 modules share a SN75451B two-way high speed big current peripheral drive.Use SN75451B to drive the benefit of HFBR-1414 to be that this chip speed is fast, only have the typical time delay of 18 nanoseconds, meet the requirement of high precision output clock and triggering.Simultaneously built-in High-current output pole, can the light emitting diode of Direct driver HFBR-1414 inside, simplifies circuit structure.We utilize SN75451B to achieve homophase output simultaneously, namely export as there being light when high level, just in time contrary with the typical circuit of HFBR-1414, and design is more reliable in order to make whole system run like this.When some node power-off or damage, light output can stop, and above-mentioned design avoids when exporting unglazed and causes triggering effective situation.
Those skilled in the art will readily understand; the foregoing is only preferred embodiment of the present invention; not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (3)
1. a distributed time sequence trigger control system, is characterized in that, comprises multiple time schedule controller and multiple time schedule controller is connected into the optical fiber of tree network; Each time schedule controller is used for providing clock signal and trigger pip;
Described time schedule controller comprises: mainboard, the power module be connected with mainboard, is arranged on the communication module on mainboard and sequence generation module, the first input/output board be connected with mainboard and the second input/output board;
Power module is used for providing direct current supply for described time schedule controller; Described communication module is used for the instruction being used for the operation of Control timing sequence controller of ether transfers on network to pass to sequence generation module, and the running status of described sequence generation module is issued over ethernet; Described sequence generation module is used for generated clock signal and trigger pip; Described first input/output board and described second input/output board are used for the light signal of outside being converted to electric signal and passing to described sequence generation module, or the electric signal that described sequence generation module exports are converted to light signal and export;
Described sequence generation module comprises: clock generating module, serial communication module, controller, counter array, output control module and bus;
Described serial communication module, described controller is all connected on the bus with described counter array and passes through bus transfer data; Described controller is connected respectively by control line with described serial communication module, described counter array, described clock generating module and described output control module and controls it;
During work, by serial communication module and external communication; When receiving instruction described serial communication module by instruction and time sequence parameter configuration by described bus transfer to controller, the running status of controller is transferred to outside communication module simultaneously; The operation of described other modules of controller coordinate; Described output control module opens or closes the output of some passages under the control of described controller; Described clock generating module produces the clock signal that described counter array needs; The clock of described counter array to described clock generating module counts, and produce required for trigger pip and clock signal.
2. distributed time sequence trigger control system as claimed in claim 1, is characterized in that, described time schedule controller also comprises Ethernet interface, for being connected with Ethernet.
3. distributed time sequence trigger control system as claimed in claim 1, is characterized in that, described clock generating module also comprises: trigger port, for receiving the trigger pip of outside input; Clock port, for receiving the clock signal of outside input, and suddenly stopping port, stopping control signal for the urgency receiving outside input.
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| CN103901339B (en) * | 2014-04-16 | 2016-08-31 | 上海航天电子通讯设备研究所 | Carrier rocket three selects the detection device and method of two firing circuit single channel reliabilities |
| CN104267702B (en) * | 2014-10-11 | 2017-05-31 | 哈尔滨工业大学 | Galatea type magnetic confinement of plasma device sequential control systems based on SOPC technologies |
| CN109932989B (en) * | 2017-12-15 | 2021-10-15 | 中国科学院大连化学物理研究所 | Interlocking method for monitoring internal sparking of klystron |
| CN112218002B (en) * | 2019-07-12 | 2023-04-07 | 浙江宇视科技有限公司 | Video stitching processor, display system and video stitching processing method |
| CN112882531B (en) * | 2021-01-18 | 2024-04-05 | 深圳市国微电子有限公司 | Time sequence bias pulling method, system and equipment based on double counter |
| CN116955258B (en) * | 2023-09-19 | 2023-11-28 | 成都立思方信息技术有限公司 | Flexibly-connectable trigger connector, signal acquisition control equipment and system |
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Granted publication date: 20160413 |