CN103474351B - NMOS transistor and its formation method and CMOS transistor containing NMOS transistor - Google Patents
NMOS transistor and its formation method and CMOS transistor containing NMOS transistor Download PDFInfo
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- CN103474351B CN103474351B CN201210185001.9A CN201210185001A CN103474351B CN 103474351 B CN103474351 B CN 103474351B CN 201210185001 A CN201210185001 A CN 201210185001A CN 103474351 B CN103474351 B CN 103474351B
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Abstract
The invention discloses an NMOS transistor and its formation method and a CMOS transistor containing the NMOS transistor. The NMOS transistor formation method comprises the following steps: a semiconductor substrate is provided; a silicon carbide layer is formed on the surface of the semiconductor substrate; a first groove is formed in the silicon carbide layer; the first groove is filled to form a channel structure; a first gate structure is formed on the surface of the channel structure; and a source/drain region is formed in the silicon carbide layer at two sides of the first gate structure. According to the NMOS transistor formation method, the silicon carbide layer is firstly formed on the surface of the semiconductor substrate, and then the silicon carbide layer is etched to form the first groove corresponding to the channel region of the NMOS transistor in the silicon carbide layer, and finally the first groove is filled to form the channel structure. By the above method for manufacturing the NMOS transistor, the problem that selective growth of silicon carbide is difficult when a groove corresponding to a source/drain region is filled with silicon carbide in the prior art can be avoided.
Description
Technical field
The present invention relates to technical field of semiconductors, should particularly to a kind of nmos pass transistor and forming method thereof and inclusion
The CMOS transistor of nmos pass transistor.
Background technology
It is known that stress can change energy gap and the carrier mobility of semi-conducting material.With semi-conducting material pressure
Inhibition effect（Piezoresistance Effect）Further investigation, industry gradually recognizes, it is possible to use stress increases MOS device
The carrier mobility of part, i.e. strained silicon technology（Strained Silicon）.
The U.S. Patent Publication Document of Publication No. US2007/0196992A1 one kind has germanium silicon and a carborundum source/drain
The strain silicon CMOS transistor in area, refer to Fig. 1, including：Semiconductor substrate 10, described Semiconductor substrate 10 is included for being formed
The region A of the nmos pass transistor and region B for forming PMOS transistor；The shallow trench that adjacent region A and region B is separated
Isolation structure 15；Positioned at the first grid structure 20 on described semiconductor substrate region A surface, described first grid structure 20 includes
Gate oxide 21 positioned at described semiconductor substrate region A surface, it is located at the gate electrode 22 on described gate oxide 21 surface, is located at
Described gate oxide 21 and the side wall 23 of gate electrode 22 sidewall surfaces, the quasiconductor lining positioned at described first grid structure 20 both sides
The first source/drain region 25 in bottom 10；Positioned at the second grid structure 30 of described semiconductor substrate region B surface, described second gate
Pole structure 30 includes gate oxide 31 positioned at described semiconductor substrate region B surface, is located at described gate oxide 31 surface
Gate electrode 32, the side wall 33 positioned at described gate oxide 31 and gate electrode 32 sidewall surfaces, positioned at described second grid structure 30
The second source/drain region 35 in the Semiconductor substrate 10 of both sides；The material of the first source/drain region of wherein said semiconductor substrate region A
Expect the carborundum for being formed in situ（SiC）, the material of the second source/drain region of described semiconductor substrate region B is formed in situ
Germanium silicon（SiGe）.
For PMOS transistor, the material filling described source/drain region 35 is germanium silicon, and its lattice paprmeter is more than quasiconductor
The lattice paprmeter of substrate, produces compression stress to the channel region between described source/drain region 35（Compressed Stress）, carry
The high mobility in hole.
For nmos pass transistor, the material filling described source/drain region 25 is carborundum, and its lattice paprmeter is less than and partly leads
The lattice paprmeter of body substrate, produces tensile stress to the channel region between described source/drain region 25（Tensile Stress）, improve
The mobility of electronics.
However, in the processing technology of CMOS tube in prior art, the formation process of nmos pass transistor is more difficult.
Content of the invention
The problem that the present invention solves is in the processing technology of CMOS tube in prior art, and the formation process of nmos pass transistor is relatively
For difficulty.
For solving the above problems, the invention provides following technical scheme：
A kind of forming method of nmos pass transistor, including：Semiconductor substrate is provided；Formed in described semiconductor substrate surface
Silicon carbide layer；Form the first groove in described silicon carbide layer；Fill described first groove, form channel structure；In described ditch
Road body structure surface forms first grid structure；Form source/drain region in the silicon carbide layer of described first grid structure both sides.
Preferably, the thickness of described silicon carbide layer is more than or equal to the thickness of described channel region.
Preferably, the thickness range of described silicon carbide layer is 200 angstroms -800 angstroms.
Preferably, in described silicon carbide layer, the atom percentage content scope of carbon is 1%-3%.
Preferably, the formation process of described silicon carbide layer is epitaxy technique or chemical vapor deposition method；Silicon source gas is
DCS(SiH2Cl2) or SiH4Or Si2H6；Carbon-source gas are C2H4Or CH3SiH3.
Preferably, the section shape of described first groove is Σ shape.
Preferably, described channel structure is stacked structure or silicon layer, the silicon of silicon layer or germanium-silicon layer or silicon layer and germanium-silicon layer
Germanium layer and the stacked structure of silicon layer.
Preferably, the formation process of described channel structure is selective epitaxial process.
A kind of nmos pass transistor, including：Semiconductor substrate；Silicon carbide layer positioned at described semiconductor substrate surface；It is located at
Described carborundum in the layer channel structure；First grid structure positioned at described channel structure surface；Positioned at described first grid
The carborundum in the layer source/drain region of structure both sides.
Preferably, the thickness of described silicon carbide layer is more than or equal to the thickness of described channel structure.
Preferably, the thickness range of described silicon carbide layer is 200 angstroms -800 angstroms.
Preferably, in described silicon carbide layer, the atom percentage content scope of carbon is 1%-3%.
Preferably, the formation process of described silicon carbide layer is epitaxy technique or chemical vapor deposition method；Silicon source gas is
DCS(SiH2Cl2) or SiH4Or Si2H6；Carbon-source gas are C2H4Or CH3SiH3.
Preferably, the section shape of described channel structure is Σ shape.
Preferably, described channel structure is stacked structure or silicon layer, the silicon of silicon layer or germanium-silicon layer or silicon layer and germanium-silicon layer
Germanium layer and the stacked structure of silicon layer.
Preferably, the formation process of described channel structure is selective epitaxial process.
A kind of CMOS transistor of the nmos pass transistor described in inclusion any of the above-described.
Compared with prior art, the present invention has advantages below：
Nmos pass transistor forming method provided by the present invention, forms silicon carbide layer using first in semiconductor substrate surface,
Then more described silicon carbide layer is performed etching, formed in described silicon carbide layer corresponding to the channel region with nmos pass transistor
First groove, more described first groove is filled with, the method forming channel structure makes nmos pass transistor, instead of existing
First in described Semiconductor substrate, form the groove corresponding with source/drain region in technology, then to the groove corresponding to source/drain region
Carry out carborundum filling, the method forming source/drain region, thus avoid in prior art to corresponding to source/drain region
When groove carries out carborundum filling, the problem of the selective growth more difficulty of carborundum.
Further, in nmos pass transistor forming method provided by the present invention, with channel region pair in described silicon carbide layer
The section shape of the first groove answered is Σ shape, and the section shape of the channel structure of the nmos pass transistor being formed also is Σ shape,
So that the section shape of the source/drain region in described nmos pass transistor is anti-Σ shape, and then enhance described nmos pass transistor
The tensile stress of middle channel region, improves the electron mobility of the channel region in described nmos pass transistor.
Brief description
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
Have technology description in required use accompanying drawing be briefly described it should be apparent that, drawings in the following description be only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, acceptable
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is the cross-sectional view of the CMOS structure that prior art is formed；
Fig. 2 is the schematic flow sheet of the forming method of the nmos pass transistor that the embodiment of the present invention one is provided；
Fig. 3-Fig. 7 is the profile of the forming method of the nmos pass transistor that the embodiment of the present invention one is provided；
Fig. 8 is the schematic flow sheet of the forming method of the CMOS transistor that the embodiment of the present invention two is provided；
Fig. 9-Figure 17 is the profile of the forming method of the CMOS transistor that the embodiment of the present invention two is provided.
Specific embodiment
Just as described in the background section, in CMOS tube processing technology of the prior art, the formation work of nmos pass transistor
Skill is more difficult.
Inventor's research finds, this is due in the formation process of nmos pass transistor in prior art, needing first partly leading
Form the groove corresponding with nmos pass transistor source/drain region in body substrate, then to corresponding to described and nmos pass transistor source/drain region
Groove carry out carborundum filling, form carborundum source/drain.Wherein, to described with nmos pass transistor source/drain region corresponding to
Groove when carrying out carborundum filling, need to carry out the selective growth of carborundum according to the shape of this groove, and carborundum
Selective growth is more difficult, thus lead to nmos pass transistor formation process more difficult.
In view of this, the invention provides a kind of forming method of nmos pass transistor, as shown in Fig. 2 including：Step
S101, provides Semiconductor substrate；Step S102, forms silicon carbide layer in described semiconductor substrate surface；Step S103, described
Form the first groove in silicon carbide layer；Step S104, fills described first groove, forms channel structure；Step S105, described
Channel structure surface forms first grid structure；Step S106, forms in the silicon carbide layer of described first grid structure both sides
Source/drain region.
As seen from the above, nmos pass transistor forming method provided by the present invention, using first in semiconductor substrate surface
Growth silicon carbide layer, then performs etching to described silicon carbide layer again, is formed and nmos pass transistor ditch in described silicon carbide layer
The first groove corresponding to road area, more described first groove is filled with, the method forming channel structure makes NMOS crystal
Pipe, instead of in prior art and first to form the groove corresponding with source/drain region in described Semiconductor substrate, then to described and
The corresponding groove in nmos pass transistor source/drain region carries out carborundum filling, and the method forming source/drain region, thus avoid existing
In technology when described first groove corresponding with nmos pass transistor source/drain region is carried out with carborundum filling, the choosing of carborundum
The more difficult problem of selecting property growth.
Understandable for enabling the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Elaborate detail in order to fully understand the present invention in the following description.But the present invention can with multiple not
It is same as alternate manner described here to implement, those skilled in the art can do class without prejudice in the case of intension of the present invention
Like popularization.Therefore the present invention is not embodied as being limited by following public.
Embodiment one：
The embodiment of the present invention provide firstly a kind of forming method of nmos pass transistor, refer to Fig. 3-Fig. 7, Fig. 3-Fig. 7
The profile of the forming method of the nmos pass transistor being provided by the embodiment of the present invention.
As shown in figure 3, providing Semiconductor substrate 100.
Described Semiconductor substrate 100 is for silicon substrate, silicon-Germanium substrate, silicon-on-insulator substrate, germanium substrate on insulator wherein
One kind.In the present embodiment, described Semiconductor substrate 100 is silicon substrate, and the crystal orientation of described silicon substrate is<110>Or<100>.
Those skilled in the art can select the type of described Semiconductor substrate 100 according to performance of semiconductor device to be formed, because
The type of this described Semiconductor substrate 100 should not too limit the scope of the invention.
As shown in figure 4, forming silicon carbide layer 110 on described Semiconductor substrate 100 surface.
In one embodiment, the technique forming described silicon carbide layer 110 specifically includes：In described Semiconductor substrate 100
Surface, forms silicon carbide layer 110 using epitaxy technique or chemical vapor deposition method.Wherein, silicon source gas is DCS (SiH2Cl2)
Or SiH4Or Si2H6；Carbon-source gas are C2H4Or CH3SiH3.
In another embodiment, the technique forming described silicon carbide layer 110 specifically includes：Semiconductor substrate 100 is provided
And silicon carbide substrates（Not shown）, the surface of described silicon carbide substrates is carried out with ion implanting, the ion of described injection be hydrogen from
Son or noble gas ion, the depth of described ion implanting is corresponding with the thickness of silicon carbide layer 110 to be formed；By described half
The surface that conductor substrate 100 surface and silicon carbide substrates inject ion is staggered relatively and apply pressure and make described Semiconductor substrate
100 and silicon carbide substrates bond；Described silicon carbide substrates, Semiconductor substrate 100 are made annealing treatment so that described
In silicon carbide substrates, the corresponding depth location of ion implanting ftractures, and described silicon carbide substrates are divided into two parts, and wherein one
Individual part is bonding with Semiconductor substrate 100, forms silicon carbide layer 110 on described Semiconductor substrate 100 surface.
In another embodiment, when described Semiconductor substrate 100 is silicon substrate or silicon-on-insulator substrate, formed described
The technique of silicon carbide layer 110 specifically includes：Carry out carbon ion implatation, described quasiconductor lining on described Semiconductor substrate 100 surface
The part near surface for the bottom 100 forms silicon carbide layer 110.
In the embodiment of the present invention, the thickness range of described silicon carbide layer 110 is 200 angstroms -800 angstroms.Wherein, described carborundum
The thickness of layer 110 is more than or equal to the thickness of the channel structure 130 being subsequently formed, so that described channel structure 130
The position of surrounding all has carborundum, and then improves the tensile stress of nmos pass transistor channel region.Wherein, described silicon carbide layer
In 110, the atom percentage content of carbon is 1% ~ 3%.It should be noted that the content of the carbon of described silicon carbide layer 110 differing heights
Can identical it is also possible to different.In embodiments of the present invention, the content of the carbon in described silicon carbide layer 110 is identical, thus dropping
Low process costs.
As shown in figure 5, forming the first groove 120 in described silicon carbide layer 110.
In described silicon carbide layer 110, the concrete technology of formation the first groove 120 is：On described silicon carbide layer 110 surface
Form mask layer, there is in described mask layer the opening exposing described silicon carbide layer 110 surface, then with described mask layer for covering
Film, performs etching to described silicon carbide layer 110, forms first groove 120 corresponding with channel region in nmos pass transistor.Its
In, described etching technics can be dry etch process or wet-etching technology or dry etching, wet method
The hybrid technique of etching.
In embodiments of the present invention, first reactive ion quarter is carried out for mask to described silicon carbide layer 110 with described mask layer
Erosion, forms the opening that profile graphics are rectangle（Not shown）, then using selective wet etching solution, described rectangle is opened
The silicon carbide layer 110 that mouth exposes carries out wet etching, forms the first groove 120.
The section shape of the first groove 120 described in the embodiment of the present invention is Σ shape, so that described nmos pass transistor
In be located at channel region both sides source/drain region section shape be anti-Σ shape.Because the carrier in nmos pass transistor is electronics, and
Tension is favorably improved the mobility of electronics, therefore, in the embodiment of the present invention, positioned at described nmos pass transistor source/drain region
Anti- Σ shape silicon carbide layer 110, contribute to strengthening the tension of channel region in described nmos pass transistor, thus improving described
The electron mobility of channel region in nmos pass transistor.
As shown in fig. 6, filling described first groove 120, form channel structure 130.
Using selective epitaxial process, described first groove 120 is filled with, forms channel structure 130.In the present invention
In embodiment, the material of described channel structure 130 can be monocrystal silicon, in order to improve the stress of nmos pass transistor channel region, institute
The material stating channel structure 130 can also be SiGe.
But, if simple silicon germanium epitaxial technique is carried out to described first groove 120, due to the lattice paprmeter of carbon and germanium
Difference is larger, the lattice mismatch between silicon carbide layer 110 and germanium-silicon layer can be led to larger, thus leading in described nmos pass transistor
The leakage current of channel region is larger.And when the thickness of described germanium-silicon layer is larger, described germanium-silicon layer is during epitaxial growth
A lot of defects can be produced.Again because the lattice paprmeter of silicon is between carbon and germanium, therefore, when the material of described channel structure 130
During for SiGe, during described first groove 120 is filled with, can be first in the surface shape of described first groove 120
Become silicon layer, then form germanium-silicon layer on the surface of described silicon layer again, thus forming silicon layer and the channel structure of germanium-silicon layer stacking
130, so on the one hand can alleviate and be had big difference due to the lattice paprmeter between carbon and germanium, and the nmos pass transistor raceway groove causing
The larger problem of area's leakage current, on the other hand can reduce the thickness of germanium-silicon layer in described channel structure 130, reduce outside germanium-silicon layer
Defect during epitaxial growth.
In addition, in follow-up manufacturing process, described channel structure 130 surface can form first grid structure further
140, and described first grid structure 140 includes gate electrode layer 141 and gate dielectric layer 142 two parts, wherein, described gate dielectric layer
142 material mostly is silicon, because the work function of silicon and SiGe is different, if directly forming first grid knot in SiGe layer surface
Structure 140, not only can reduce the quality of described gate dielectric layer 142, lead to described gate dielectric layer 142 easily breakdown, and need
Overcome the work function regulation problem of described first grid structure 140.
Therefore, during described first groove 120 is filled with, can also be using first in described first groove
120 surfaces form silicon layer, then form germanium-silicon layer in described silicon surface again, finally form silicon layer in described SiGe layer surface again
Fill method, on the one hand thus forming the channel structure 130 of silicon layer, germanium-silicon layer and silicon layer multiple-level stack, thus can improve
The quality of the described gate dielectric layer 142 being subsequently formed, on the other hand can reduce germanium-silicon layer in described channel structure 130 further
Thickness, reduce germanium-silicon layer epitaxial process in defect.
As shown in fig. 7, forming first grid structure 140 on described channel structure 130 surface.
Described first grid structure 140 includes the gate dielectric layer 142 positioned at described channel structure 130 surface, and is located at
The gate electrode layer 141 on described gate dielectric layer 142 surface.
The material of described gate dielectric layer 142 can be the high k dielectric material such as silicon oxide or hafnium oxide, described gate electrode layer
141 material can be DOPOS doped polycrystalline silicon, metal, metal silicide or other conductive materials.Described first grid structure 140
Sidewall structure 150 is also formed with the side wall of both sides, described sidewall structure 150 is silicon oxide layer, silicon nitride layer or described oxidation
Silicon layer and the multilayer lamination structure of silicon nitride layer composition.Because forming described first grid structure 140 and sidewall structure 150
Technique be well known to those skilled in the art, will not be described in detail herein.
It should be noted that in the concrete processing technology of described nmos pass transistor, source/drain region in described nmos pass transistor
The channel region in a and described nmos pass transistor of carborundum Edge Distance first grid structure 140 in epitaxially grown
Channel structure 130 bottom, from silicon carbide layer 110 bottom distance b, can be carried out according to the specific performance of described nmos pass transistor
Adjustment, thus strengthening the tensile stress of described nmos pass transistor channel region, and then improves the electronics of channel region in nmos pass transistor
Mobility.
Form source/drain region in the silicon carbide layer 110 of described first grid structure 140 both sides.
With described first grid structure 140 as mask, the silicon carbide layer 110 being pointed to described channel structure 130 both sides enters
Row ion implanting, forms the carborundum source/drain region of nmos pass transistor.
In sum, nmos pass transistor forming method provided by the present invention, is formed in semiconductor substrate surface using first
Silicon carbide layer, then performs etching to described silicon carbide layer again, is formed and nmos pass transistor channel region in described silicon carbide layer
The first corresponding groove, more described first groove is filled with, the method forming channel structure makes nmos pass transistor, replaces
First in described Semiconductor substrate, form the groove corresponding with nmos pass transistor source/drain region in prior art, then to institute
State the groove corresponding with nmos pass transistor source/drain region and carry out carborundum filling, the method forming source/drain region makes NMOS crystal
Pipe, thus avoiding in prior art when to carrying out carborundum filling with the groove corresponding to source/drain region, the selection of carborundum
Property the more difficult problem of growth.
Further, in nmos pass transistor forming method provided by the present invention, the described groove with corresponding to channel region
Section shape is Σ shape, and the section shape making the channel structure of formed nmos pass transistor is also Σ shape, so that described
The section shape of the source/drain region in nmos pass transistor is anti-Σ shape, and then enhances drawing of channel region in described nmos pass transistor
Stretch stress, improve the electron mobility of the channel region in described nmos pass transistor.
Present invention also offers a kind of nmos pass transistor being made using above-mentioned nmos pass transistor forming method, including：Half
Conductor substrate；Silicon carbide layer positioned at described semiconductor substrate surface；Positioned at described carborundum in the layer channel structure；Positioned at institute
State the first grid structure on channel structure surface；Carborundum in the layer source/drain region positioned at described first grid structure both sides.
Described Semiconductor substrate is silicon substrate, silicon-Germanium substrate, silicon-on-insulator substrate, germanium substrate on insulator therein
Kind.In the present embodiment, described Semiconductor substrate is silicon substrate, and the crystal orientation of described silicon substrate is<110>Or<100>.This area
Technical staff can select the type of described Semiconductor substrate according to performance of semiconductor device to be formed, therefore described partly lead
The type of body substrate 100 should not too limit the scope of the invention.
The thickness range of described silicon carbide layer is 200 angstroms -800 angstroms.Wherein, the thickness of described silicon carbide layer is more than or equal to
The thickness of the channel structure being subsequently formed, so that the position around described channel structure all has carborundum, and then
Improve the tensile stress of nmos pass transistor channel region.Wherein, in described silicon carbide layer, the atom percentage content of carbon is 1% ~ 3%.
It should be noted that the content of the carbon of described silicon carbide layer differing heights can identical it is also possible to different.In the embodiment of the present invention
In, the content of the carbon in described silicon carbide layer is identical, thus reducing process costs.
Channel structure described in the embodiment of the present invention be silicon layer or germanium-silicon layer or silicon layer and germanium-silicon layer stacked structure or
The stacked structure of silicon layer, germanium-silicon layer and silicon layer, and the section shape of described channel structure is Σ shape, so that described NMOS is brilliant
The section shape being located at the source/drain region of channel region both sides in body pipe is anti-Σ shape.Because the carrier in nmos pass transistor is electricity
Son, and tension is favorably improved the mobility of electronics, therefore, in the embodiment of the present invention, positioned at described nmos pass transistor source/drain
The silicon carbide layer of the anti-Σ shape of polar region, contributes to strengthening the tension of channel region in described nmos pass transistor, thus improving institute
State the electron mobility of channel region in nmos pass transistor.
Embodiment two
Embodiments provide a kind of CMOS transistor including the nmos pass transistor provided in embodiment one.As
Shown in Fig. 8, the forming method of described CMOS transistor includes：
Step S201：As shown in figure 9, providing Semiconductor substrate 200.
Step S202：As shown in Figure 10, form silicon carbide layer 210 in described semiconductor substrate surface.
In an embodiment of the present invention, the technique forming described silicon carbide layer 210 specifically includes：In described Semiconductor substrate
200 surfaces, form silicon carbide layer 210 using epitaxy technique or chemical vapor deposition method.Wherein, silicon source gas is DCS
(SiH2Cl2) or SiH4Or Si2H6；Carbon-source gas are C2H4Or CH3SiH3.
In another embodiment, the technique forming described silicon carbide layer 210 specifically includes：Semiconductor substrate 200 is provided
And silicon carbide substrates（Not shown）, the surface of described silicon carbide substrates is carried out with ion implanting, the ion of described injection be hydrogen from
Son or noble gas ion, the depth of described ion implanting is corresponding with the thickness of silicon carbide layer 210 to be formed；By described half
The surface that conductor substrate 200 surface and silicon carbide substrates inject ion is staggered relatively and apply pressure and make described Semiconductor substrate
200 and silicon carbide substrates bond；Described silicon carbide substrates, Semiconductor substrate 200 are made annealing treatment so that described
In silicon carbide substrates, the corresponding depth location of ion implanting ftractures, and described silicon carbide substrates are divided into two parts, and wherein one
Individual part is bonding with Semiconductor substrate 200, forms silicon carbide layer 210 on described Semiconductor substrate 200 surface.
In another embodiment, when described Semiconductor substrate 200 is silicon substrate or silicon-on-insulator substrate, formed described
The technique of silicon carbide layer 210 specifically includes：Carry out carbon ion implatation, described quasiconductor lining on described Semiconductor substrate 200 surface
The part near surface for the bottom 200 forms silicon carbide layer 110.
In the embodiment of the present invention, the thickness range of described silicon carbide layer 210 is 200 angstroms -800 angstroms.Wherein, described carborundum
The thickness of layer 210 is more than or equal to the thickness of the channel structure 214 being subsequently formed, so that described channel structure 214
The position of surrounding all has carborundum, and then improves the tensile stress of nmos pass transistor channel region.Wherein, described silicon carbide layer
In 210, the atom percentage content of carbon is 1% ~ 3%.It should be noted that the content of the carbon of described silicon carbide layer 210 differing heights
Can identical it is also possible to different.In embodiments of the present invention, the content of the carbon in described silicon carbide layer 210 is identical, thus reducing
Process costs.
Step S203：As shown in figure 11, form shallow trench isolation in described Semiconductor substrate 200 and silicon carbide layer 210
Structure 211, described fleet plough groove isolation structure 211 runs through described silicon carbide layer 210, and is embedded in described Semiconductor substrate 200,
Described Semiconductor substrate 200 and silicon carbide layer 210 are divided into region A for forming nmos pass transistor and are used for forming PMOS brilliant
Region B two parts of body pipe.The concrete formation process of described fleet plough groove isolation structure 211 is the known skill of those skilled in the art
Art, will not be described here.
Step S204：As shown in figure 12, remove the silicon carbide layer 210 on Semiconductor substrate 200 surface in described region B, and
Semiconductor substrate 200 surface in described region B forms additional substrate 212, to ensure the additional substrate in described region B
Silicon carbide layer 210 flush in 212 surfaces and described region A.
The technique removing the silicon carbide layer 210 on Semiconductor substrate 200 surface in described region B can be wet etching,
Can be dry etching, such as reactive ion etching.
The material of described additional substrate 212 can be monocrystal silicon or SiGe.But, if in described quasiconductor
Substrate 200 surface carries out simple silicon germanium epitaxial technique, due to the thickness of described germanium-silicon layer larger when, described germanium-silicon layer is in extension
A lot of defects can be produced during growth.Therefore, when the material of described additional substrate 212 is SiGe, can be first described
Semiconductor substrate 200 surface silicon epitaxial layers, then again in described silicon surface epitaxial silicon germanium layer, thus form silicon layer and germanium-silicon layer
The additional substrate 212 of stacking, thus reducing the thickness of germanium-silicon layer in described additional substrate 212, reduces SiGe layer epitaxially grown mistake
Defect in journey.
In addition, for the thickness reducing germanium-silicon layer in described additional substrate 212 further, reducing SiGe layer epitaxially grown mistake
Defect in journey, can also be in described Semiconductor substrate 200 surface silicon epitaxial layers, germanium-silicon layer and silicon layer successively, thus forming silicon
The additional substrate 212 of layer, germanium-silicon layer and silicon layer multiple-level stack.
It should be noted that when performing etching to the silicon carbide layer 210 in described region B, needing to state region A described
Interior silicon carbide layer 210 surface forms mask layer, to avoid the silicon carbide layer 210 in described region A being caused damage.
Step S205：As shown in figure 13, form the first groove 213 in the silicon carbide layer 210 in described region A.
The section shape of the first groove 213 described in the embodiment of the present invention is Σ shape, and its concrete formation process is：Described
Silicon carbide layer 210 surface forms mask layer, has the opening exposing described silicon carbide layer 210 surface, then in described mask layer
With described mask layer as mask, described silicon carbide layer 210 is performed etching, formed corresponding with channel region in nmos pass transistor
First groove 213.Wherein, described etching technics can for dry etch process or wet-etching technology or
Dry etching, the hybrid technique of wet etching.
It should be noted that removing the silicon carbide layer on Semiconductor substrate 200 surface in described region B in described step S204
The process forming the first groove 212 in 210 process and described step S205 in silicon carbide layer 210 in described region A is permissible
Same step is carried out, that is, first corresponding to nmos pass transistor source/drain region in described silicon carbide layer 210 surface with region A
Region forms mask layer, then again to the silicon carbide layer 210 on Semiconductor substrate 200 surface in described region B with institute will be formed
State carburization zone 210 in the first groove 213 to perform etching simultaneously, thus Semiconductor substrate 200 surface in the described region B of removal
While silicon carbide layer 210, form the first groove 213 in described region A silicon carbide layer 210.Wherein, in described silicon carbide layer
The purpose that the 210 surfaces region corresponding with nmos pass transistor source/drain region in the A of region forms mask layer is：In order to avoid going
Except the silicon carbide layer 210 on Semiconductor substrate 200 surface and being formed first in silicon carbide layer 210 in described region A in described region B
During groove 213, to cause with the carburization zone 210 corresponding to nmos pass transistor source/drain region in described region A damage.
Step S206：As shown in figure 14, fill described first groove 213, form channel structure 214.
Using selective epitaxial process, described first groove 213 is filled with, forms channel structure 214.In the present invention
In embodiment, described channel structure 214 can be monocrystalline silicon layer, in order to improve the stress of nmos pass transistor channel region, described ditch
The material of road structure 214 can also be SiGe.
But, if simple silicon germanium epitaxial technique is carried out to described first groove 213, due to the lattice paprmeter of carbon and germanium
Difference is larger, the lattice mismatch between silicon carbide layer 210 and germanium-silicon layer can be led to larger, thus leading in described nmos pass transistor
The leakage current of channel region is larger.And when the thickness of described germanium-silicon layer is larger, described germanium-silicon layer is during epitaxial growth
A lot of defects can be produced.Again because the lattice paprmeter of silicon is between carbon and germanium, therefore, when the material of described channel structure 214
During for SiGe, during described first groove 213 is filled with, can be first in the surface shape of described first groove 213
Become silicon layer, then form germanium-silicon layer on the surface of described silicon layer again, thus forming silicon layer and the channel structure of germanium-silicon layer stacking
214, so on the one hand can alleviate and be had big difference due to the lattice paprmeter between carbon and germanium, and the nmos pass transistor raceway groove causing
The larger problem of area's leakage current, on the other hand can reduce the thickness of germanium-silicon layer in described channel structure 214, reduce outside germanium-silicon layer
Defect during epitaxial growth.
In addition, in follow-up manufacturing process, described channel structure 214 surface can form first grid structure further
215, and described first grid structure 215 includes gate electrode layer and gate dielectric layer two parts, wherein, the material of described gate dielectric layer
It mostly is silicon, because the work function of silicon and SiGe is different, if directly forming first grid structure 215 in SiGe layer surface, no
The quality of described gate dielectric layer only can be reduced, lead to described gate dielectric layer easily breakdown, and need to overcome the described first grid
The work function regulation problem of pole structure 215.
Therefore, during described first groove 213 is filled with, can also be using first in described first groove
213 surfaces form silicon layer, then form germanium-silicon layer in described silicon surface again, finally form silicon layer in described SiGe layer surface again
Fill method, on the one hand thus forming the channel structure 214 of silicon layer, germanium-silicon layer and silicon layer multiple-level stack, thus can improve
The quality of the described gate dielectric layer being subsequently formed, on the other hand can reduce germanium-silicon layer in described channel structure 214 further
Thickness, reduces the defect in germanium-silicon layer epitaxial process.
Step S207：As shown in figure 15, form first grid structure 215 on described channel structure 214 surface.Described first
Grid structure 215 includes the gate dielectric layer positioned at described channel structure surface, and the grid electricity being located at described gate dielectric layer surface
Pole layer, and it is also formed with sidewall structure 216 on the side wall of described first grid structure 215 both sides.
The material of described gate dielectric layer can be the high k dielectric material such as silicon oxide or hafnium oxide, the material of described gate electrode layer
Material can be DOPOS doped polycrystalline silicon, metal, metal silicide or other conductive materials.The side of described first grid structure 215 both sides
Sidewall structure 216 is also formed with wall, described sidewall structure 216 is silicon oxide layer, silicon nitride layer or described silicon oxide layer and nitrogen
The multilayer lamination structure that both SiClx layers are constituted.Because the technique of the described first grid structure 215 of formation and sidewall structure 216 is
It is well known to those skilled in the art, will not be described in detail herein.
It should be noted that in the concrete processing technology of described nmos pass transistor, source/drain region in described nmos pass transistor
The channel region in a and described nmos pass transistor of carborundum Edge Distance first grid structure 215 in epitaxially grown
Channel structure 214 bottom, from silicon carbide layer 210 bottom distance b, can be carried out according to the specific performance of described nmos pass transistor
Adjustment, thus strengthening the tensile stress of described nmos pass transistor channel region, and then improves the electronics of channel region in nmos pass transistor
Mobility.
Step S208：Form source/drain region in the silicon carbide layer 210 of described first grid structure 215 both sides.With described
One grid structure 215 is mask, and the silicon carbide layer 210 being pointed to described channel structure 215 both sides carries out ion implanting, is formed
The carborundum source/drain region of nmos pass transistor.
Step S209：As shown in figure 16, second grid structure 217 is formed on the additional substrate 212 in described region B.
Described second grid structure 217 includes the gate dielectric layer positioned at described additional substrate 212 surface, and is located at described gate dielectric layer
The gate electrode layer on surface, and it is also formed with sidewall structure 218 on the side wall of described second grid structure 217 both sides.
Step S210：As shown in figure 17, shape in the additional substrate 212 of second grid structure 217 both sides in described region B
Become the second groove 219, and described second groove 219 is filled with, form the source/drain of PMOS transistor.
CMOS transistor forming method provided by the present invention, grows silicon carbide layer using first in semiconductor substrate surface,
Then more described silicon carbide layer is performed etching, formed in described silicon carbide layer with NMOS transistor in corresponding to channel region
The first groove, more described first groove is filled with, the method forming channel structure makes nmos pass transistor, instead of existing
Have in technology and first in described Semiconductor substrate, to form the groove corresponding with source/drain region, then to recessed corresponding to source/drain region
Groove carries out carborundum filling, and the method forming source/drain region makes nmos pass transistor, thus avoid in prior art to
When groove corresponding to source/drain region carries out carborundum filling, the problem of the selective growth more difficulty of carborundum, and then reduce
The technology difficulty that CMOS transistor makes.
Further, in CMOS transistor forming method provided by the present invention, described relative with nmos pass transistor channel region
The section shape of the first groove answered is Σ shape, and the section shape making the channel structure of formed nmos pass transistor is also Σ
Shape, so that the section shape of the source/drain region of nmos pass transistor is anti-Σ shape in described CMOS transistor, and then enhances institute
State the tensile stress of channel region in nmos pass transistor, improve the electron mobility of the channel region in described nmos pass transistor,
Improve the carrier mobility of described CMOS transistor eventually.
Although the present invention is open as above with preferred embodiment, it is not for limiting the present invention, any this area
Without departing from the spirit and scope of the present invention, the methods and techniques content that may be by the disclosure above is to this for technical staff
Bright technical scheme makes possible variation and modification, and therefore, every content without departing from technical solution of the present invention, according to the present invention
Technical spirit any simple modification, equivalent variations and modification that above example is made, belong to technical solution of the present invention
Protection domain.
Claims (15)
1. a kind of forming method of nmos pass transistor is it is characterised in that include：
Semiconductor substrate is provided；
Form silicon carbide layer in described semiconductor substrate surface；
Form the first groove in described silicon carbide layer, the section shape of described first groove is Σ shape；
Fill described first groove, form channel structure；
Form first grid structure on described channel structure surface；
Form source/drain region in the silicon carbide layer of described first grid structure both sides.
2. nmos pass transistor as claimed in claim 1 forming method it is characterised in that described silicon carbide layer thickness be more than or
Thickness equal to described channel region.
3. the forming method of nmos pass transistor as claimed in claim 2 is it is characterised in that the thickness range of described silicon carbide layer is
200 angstroms -800 angstroms.
4. nmos pass transistor as claimed in claim 1 forming method it is characterised in that in described silicon carbide layer carbon atom hundred
Dividing than content range is 1%-3%.
5. the forming method of nmos pass transistor as claimed in claim 1 is it is characterised in that the formation process of described silicon carbide layer is
Epitaxy technique or chemical vapor deposition method；Silicon source gas is DCS (SiH2Cl2) or SiH4Or Si2H6；Carbon-source gas are C2H4Or
CH3SiH3.
6. nmos pass transistor as claimed in claim 1 forming method it is characterised in that described channel structure be silicon layer, SiGe
Layer, the stacked structure of silicon layer and germanium-silicon layer, or the stacked structure of silicon layer, germanium-silicon layer and silicon layer.
7. the forming method of nmos pass transistor as claimed in claim 1 is it is characterised in that the formation process of described channel structure is
Selective epitaxial process.
8. a kind of nmos pass transistor is it is characterised in that include：
Semiconductor substrate；
Silicon carbide layer positioned at described semiconductor substrate surface；
Positioned at described carborundum in the layer channel structure, the section shape of described channel structure is Σ shape；
First grid structure positioned at described channel structure surface；
Carborundum in the layer source/drain region positioned at described first grid structure both sides.
9. nmos pass transistor as claimed in claim 8 is it is characterised in that the thickness of described silicon carbide layer is more than or equal to described ditch
The thickness of road structure.
10. nmos pass transistor as claimed in claim 8 is it is characterised in that the thickness range of described silicon carbide layer is 200 angstrom -800
Angstrom.
11. nmos pass transistors as claimed in claim 8 it is characterised in that in described silicon carbide layer carbon atom percentage content
Scope is 1%-3%.
12. nmos pass transistors as claimed in claim 8 are it is characterised in that the formation process of described silicon carbide layer is epitaxy technique
Or chemical vapor deposition method；Silicon source gas is DCS (SiH2Cl2) or SiH4Or Si2H6；Carbon-source gas are C2H4Or CH3SiH3.
13. nmos pass transistors as claimed in claim 8 it is characterised in that described channel structure be silicon layer, germanium-silicon layer, silicon layer and
The stacked structure of germanium-silicon layer, or the stacked structure of silicon layer, germanium-silicon layer and silicon layer.
14. nmos pass transistors as claimed in claim 8 are it is characterised in that the formation process of described channel structure is outside selectivity
Prolong technique.
A kind of 15. CMOS transistor including the nmos pass transistor described in any one of claim 8-14.
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| US20020149022A1 (en) * | 2000-07-13 | 2002-10-17 | Sei-Hyung Ryu | Silicon carbide inversion channel mosfets |
| CN101593701A (en) * | 2008-05-30 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | The manufacture method of strain NMOS device and stress CMOS device |
| CN101924107A (en) * | 2010-07-15 | 2010-12-22 | 电子科技大学 | Stress enhanced CMOS (Complementary Metal-Oxide-Semiconductor) transistor structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020149022A1 (en) * | 2000-07-13 | 2002-10-17 | Sei-Hyung Ryu | Silicon carbide inversion channel mosfets |
| CN101593701A (en) * | 2008-05-30 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | The manufacture method of strain NMOS device and stress CMOS device |
| CN101924107A (en) * | 2010-07-15 | 2010-12-22 | 电子科技大学 | Stress enhanced CMOS (Complementary Metal-Oxide-Semiconductor) transistor structure |
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