CN103456792A - Semiconductor element structure - Google Patents

Abstract

A semiconductor element structure comprises at least one annular transistor unit arranged in a substrate. The annular transistor unit comprises a solid grid layer, a doping layer and an annular grid layer, and is sequentially arranged in the substrate from inside to outside.

Description

Semiconductor device structure

technical field

The present invention relates to a semiconductor element structure, in particular to a semiconductor element structure using a ring-shaped transistor unit.

Background technique

With the advancement of technology and the increasing demand for multi-functionality of electronic products, it is necessary to integrate multiple circuits with different functions; relatively, the more multi-functional electronic products, the more power supply is required For the operation of electronic products, generally each function is provided with its own dedicated power supply system to provide the required power. However, due to cost and volume considerations, this method cannot be implemented.

For the problem of power supply, many different types of power converters have been proposed in the industry to generate sufficient power, such as DC-to-DC power converters or AC-to-DC power converters, to solve the aforementioned problems. However, in order to generate enough power, these power converters usually require multiple power transistors with strong current driving capability, that is, increasing the perimeter of the gate can only increase the current density, and increasing the perimeter area will relatively occupy a large amount of power. Therefore, in addition to the problem of bulky size, this power transistor also has multiple problems in circuit layout, such as current density, heat dissipation, on-resistance and current uniformity.

In view of this, the present invention addresses the shortcomings of the above-mentioned prior art, and proposes a semiconductor element structure to effectively overcome the above-mentioned problems.

Contents of the invention

The main purpose of the present invention is to provide a semiconductor element structure, which can increase the peripheral length of the transistor unit with a double-gate structure by making a solid and ring shape, thereby increasing the current density and greatly increasing the output power.

The secondary purpose of the present invention is to provide a semiconductor element structure, which can manufacture a large number of ring-shaped transistors on a substrate with a limited area, which can not only improve the overall power output, but also make the overall volume miniaturized, so as to meet the needs of light, thin and short products .

To achieve the above objectives, the present invention provides a semiconductor device structure, including a substrate and at least one ring-shaped transistor unit. The ring-shaped transistor unit includes a solid gate layer, a ring-shaped gate layer and a doped layer; the solid gate layer is arranged in the substrate, the ring-shaped gate layer is arranged around the solid gate layer, and the doped layer is located on the A double-gate transistor unit is formed between the solid gate layer and the ring-shaped gate layer. Among them, through the collocation of solid and ring structures, an interactive field effect can be generated between them, thereby improving the withstand voltage.

Wherein, the ring transistor unit is polygonal or triangular.

Wherein, the solid gate layer is a polygonal gate layer, and the annular gate layer is formed in a shape corresponding to the polygonal gate layer.

Wherein, the solid gate layer is a triangular gate layer, and the ring-shaped gate layer is formed in a shape corresponding to the triangular gate layer.

Wherein, the doped layer is a drain or a source.

Wherein, the ring transistor unit is a power transistor unit.

Wherein, when there are multiple ring-shaped transistor units, they are arranged at intervals in the substrate.

Wherein, the ring transistor unit further includes a plurality of sub-ring transistor units, which are triangular in shape and can be ringed to form a polygonal ring transistor unit or a triangular ring transistor unit.

Compared with the prior art, the present invention has the following advantages:

The present invention manufactures transistor units with a double-gate structure through solid and ring shapes, which can increase the perimeter of the edge, thereby increasing the current density. Through the interactive field effect between the ring shapes, the withstand voltage is greatly increased, and the Output Power. Furthermore, a large number of ring-shaped transistors can be fabricated on a limited-area substrate, which can not only increase the overall power output to meet the power requirements of multi-functional electronic products, but also reduce the overall volume to meet the needs of thin, light and small products.

Description of drawings

Fig. 1 is a structural diagram of the present invention.

Fig. 2 is a sectional view taken along line A-A' of Fig. 1 .

Fig. 3 is another structural diagram of the present invention.

FIG. 4A is a schematic diagram of a ring transistor unit using multiple polygons according to the present invention.

FIG. 4B is a schematic diagram of the present invention using a plurality of triangular ring transistor units.

FIG. 5 is a schematic diagram of forming a polygonal ring transistor unit by ringing a plurality of ring transistor units according to the present invention.

Explanation of reference numerals: 10—substrate; 12—annular transistor unit; 122—solid gate layer; 124—annular gate layer; 126—doped layer; 14—sub-annular transistor unit.

Detailed ways

Please refer to FIG. 1 and FIG. 2 together. FIG. 1 is a structural diagram of the present invention, and FIG. 2 is a cross-sectional view taken along the section line A-A' of FIG. 1 . The semiconductor device structure includes a substrate 10 and at least one ring transistor unit 12 . The ring transistor unit 12 includes a solid gate layer 122, a ring gate layer 124 and a doped layer 126; the solid gate layer 122 is arranged in the substrate 10, and the ring gate layer 124 is arranged around the solid gate A layer 122 and a doped layer 126 are located between the solid gate layer 122 and the ring-shaped gate layer 124 to form a double-gate transistor cell.

Wherein, the ring transistor unit 12 is a power transistor, and the doped layer 126 is a drain or a source. Since the area of the gate is proportional to the current, if the total circumference of the gate is long enough, the driving capability of the current can be effectively improved. In detail, in order to increase the perimeter length and width, an opening is provided on the substrate, and the solid gate layer 122 is deposited in the opening, and then the doped layer 126 is arranged according to the shape of the solid gate layer 122 On the outer side of the solid gate layer 122 , finally the ring-shaped gate layer 124 is arranged on the outer side of the doped layer 126 according to the shape of the doped layer 126 . If the annular transistor unit 12 is columnar, when the solid gate layer 122 receives a bias voltage, a corresponding channel is generated, and the channel width is the circumference calculated from the radius of the solid gate layer 122 . Similarly, when the ring-shaped gate layer 124 is subjected to a bias voltage, the width of the channel is the circumference of the ring-shaped gate layer 124 calculated by taking the average value of the inner and outer ring radii of the ring-shaped gate layer 124 as the radius. Through the design of the width of the solid gate layer 122 and the ring structure design of the ring gate layer 124 , the length of the total circumference can be increased, so that the current density can be greatly improved. Certainly, the structural design of the annular transistor unit 12 is different, and the way of calculating the total perimeter is also different. As shown in FIG. The shape of the gate layer is formed corresponding to the shape of the polygonal gate layer; or as shown in FIG. The shape of the gate layer 124 corresponds to the shape of the solid gate layer 122 in sequence, and the doped layer 126 and the ring-shaped gate layer 124 forming a triangle are arranged around it. No matter what the design of the ring-shaped transistor unit 12 is, it cannot depart from the purpose of the present invention to increase the total perimeter of the edge of the same region by using the ring-shaped gate 124 and the solid gate layer 122 . Wherein, the annular transistor unit 12 is a polygonal shape, such as a triangle, a regular pentagon or a regular hexagon, etc., and each vertex of the polygonal shape is modified as a fan or a parabolic curve, which can improve the discharge phenomenon of the annular transistor unit 12 . As is well known to those skilled in the art, if the doped layer 126 is the drain of the annular transistor unit 12, the doped layer located outside the annular gate layer 124 is the source; otherwise, if the doped layer 126 is the source of the annular transistor unit 12 , and the doped layer outside the annular gate layer 124 is the drain.

As shown in FIG. 4A, when there are multiple annular transistor units 12, and when the shape is polygonal, the present invention uses a plurality of double-gate annular transistor units 12, which are arranged in the substrate 10 at intervals, so that the The area occupied by the substrate. As shown in FIG. 4B, when there are multiple ring transistor units 12, and when the shape is triangular, these triangular ring transistor units 12 can be reversely dislocated in the substrate 10, so that a sufficient number of ring transistors The unit 12 is disposed in the substrate 10 with a limited area.

As shown in FIG. 5 again, the ring transistor unit 12 further includes a plurality of sub-ring transistor units 14, which are triangular in shape and can be ringed to form a polygonal ring transistor unit or a triangular ring transistor unit. The ring is formed to form a polygonal ring transistor unit for illustration, and six sub-ring transistor units 14 are used to form a polygon ring transistor unit, such as a regular hexagon, and the total perimeter of each sub-ring transistor unit 14 is designed according to requirements. After summing up the total perimeter of the six sub-ring transistor units 14, the total perimeter of the polygonal ring transistor unit in the same area can be greatly increased. This design method can also produce a large number of rings on the effective substrate 10 area. Transistor unit 12. Wherein, there is no need to deposit a doped layer (such as Field Oxide) between adjacent six sub-ring transistor units 14 , of course, a doping layer may also be deposited between adjacent six sub-ring transistor units 14 . Here, the design is not limited to ring transistor units of any shape, as long as the above-mentioned sub-ring transistor units 14 are adjacent to each other with or without doped layers, they all belong to the scope of the present invention.

In summary, the present invention manufactures a transistor unit with a double-gate structure through solid and ring shapes, which can increase the perimeter of the edge, thereby increasing the current density, and through the interactive field effect between the ring shapes, the withstand voltage is greatly improved. It can also increase the output power. Furthermore, a large number of ring-shaped transistors can be fabricated on a limited-area substrate, which can not only increase the overall power output to meet the power requirements of multi-functional electronic products, but also reduce the overall volume to meet the needs of thin, light and small products.

The above description of the present invention is illustrative rather than restrictive. Those skilled in the art understand that many modifications, changes or equivalents can be made to it within the spirit and scope of the claims, but they will all fall into within the protection scope of the present invention.

Claims (8)

1. A semiconductor element structure, characterized in that, comprising: A substrate and at least one ring transistor unit, the ring transistor unit includes: a solid gate layer, disposed in the substrate; a ring-shaped gate layer, which is arranged around the solid gate layer; and A doping layer is located between the solid gate layer and the annular gate layer. 2. The semiconductor device structure according to claim 1, wherein the ring-shaped transistor unit is polygonal or triangular. 3 . The semiconductor device structure according to claim 2 , wherein the solid gate layer is a polygonal gate layer, and the ring-shaped gate layer is formed in a shape corresponding to the polygonal gate layer. 4 . 4 . The semiconductor device structure according to claim 2 , wherein the solid gate layer is a triangular gate layer, and the ring-shaped gate layer is formed in a shape corresponding to the triangular gate layer. 5. The semiconductor device structure according to claim 1, wherein the doped layer is a drain or a source. 6. The semiconductor device structure according to claim 1, wherein the ring transistor unit is a power transistor unit. 7 . The semiconductor device structure according to claim 1 , wherein when there are multiple ring-shaped transistor units, they are arranged at intervals in the substrate. 8 . 8. The semiconductor element structure as claimed in claim 1, wherein the ring transistor unit further comprises a plurality of sub-ring transistor units, which are triangular in shape and ring to form a polygonal ring transistor unit or a Triangular ring transistor cell.

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