CN103402062A - CCD driving time sequence generation method and driving time sequence generation device thereof - Google Patents
CCD driving time sequence generation method and driving time sequence generation device thereof Download PDFInfo
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Abstract
A CCD driving time sequence generation method comprises a terminal device, a processing chip, a CCD drive circuit and a peripheral circuit. An operator inputs parameters into the processing chip through the terminal device; the processing chip controls the peripheral circuit to generate an impulse time sequence; the CCD drive circuit generates CCD drive signals; the parameters have three types which are times, level states and cycle indexes; when the processing chip receives input times, a rigid mathematical relation is kept among a plurality of times. The CCD driving time sequence generation method provided by the invention has the technical effect that different driving time sequences can be generated by depending on one set of hardware device; the invention further provides a device obtained according to the method; the method is simple and visual; a testing person is not required to master complex program language and compilation rules, so that the universality is high; the driving time sequence design and test requirements of any CCD chip can be met; the complexity of hardware equipment to be depended on is lower; the cost is low.
Description
Technical field
The present invention relates to a kind of CCD measuring technology, relate in particular to a kind of CCD and drive sequential generation method and drive the sequential generating apparatus.
Background technology
Development along with the CCD technology, large face battle array, long alignment, multispectral all kinds of imageing sensors occur in succession, and in every field, obtained increasing application, add engineering field and the systematic function of imageing sensor is required also more and more higher, this just makes the research of CCD Driving technique and the importance of technology that the CCD performance is estimated also more and more receives the industry concern.
As everyone knows, the most basic condition of work of ccd image sensor is the pulsed drive sequential relationship, so in various applications, launched one after another all kinds of ccd image sensors are driven the design studies work of sequential.for different applications, the structure of ccd image sensor, scale, function and pattern also are not quite similar, therefore present CCD kind is very various, this just causes the driving sequential of different types of ccd image sensor demand also not identical, it drives the also property of there are differences of sequential to even same ccd image sensor in the different application occasion, so, estimate the performance parameter of a certain ccd image sensor, just must be according to the requirement of device architecture and application conditions, design separately the driving sequence testing circuit of an assembly cover, thereby produce loaded down with trivial details workload and test circuit cost consumption.
for solving design of driving timing sequence, test job is very loaded down with trivial details, expend huge problem, those skilled in the art have also carried out relevant exploration, PI(Pulse Instrument as the U.S.) the PI7700 image series sensor testing system of company's production, this test macro has adopted a kind of special-purpose sequential generation language, it can produce the driving sequential of various ccd image sensors, but its range of application is very limited, trace it to its cause, mainly to compile and move because this test macro must adopt its proprietary design software, flexibility and portability are all very poor, and very high to tester's individual competency profiling, the tester must skillfully grasp design software and compiling rule thereof, and for example Japanese Sony Corporation, U.S. AD company for the design of driving timing sequence of ccd image sensor some special-purpose sequential generating chips, but these sequential generating chips also can only meet the sequential relationship requirement of the ccd image sensor of specifying model, do not possess versatility.
Summary of the invention
For the problem in background technology, the present invention proposes a kind of CCD and drive sequential generation method, depend on the CCD driving sequential generating apparatus that the method obtains, those skilled in the art can be by carrying out parameter setting simply and intuitively on terminal equipment, can obtain diversified CCD and drive sequential, thereby meet design of driving timing sequence and the test needs of various types of CCD chips, will design with test job and simplify; Concrete scheme of the present invention is:
A kind of CCD drives sequential generation method, comprising: for interactive terminal equipment, process chip, CCD drive circuit and for the peripheral circuit of signal transmission between terminal equipment, process chip and CCD drive circuit three; The common cover CCD that forms of described terminal equipment, process chip, CCD drive circuit and peripheral circuit drives the sequential generating apparatus; Operating personnel pass through predefined various control parameters in terminal equipment input processing chip, process chip generates corresponding pulse sequence signal according to different control parameter Control peripheral circuits, pulse sequence signal driver CCD drive circuit generates corresponding CCD and drives signal, thereby can complete the test to dissimilar CCD chip by once cover CCD, driving the sequential generating apparatus; The type of described control parameter has three kinds, i.e. time parameter, level state parameter and cycle-index parameter; In single CCD imaging cycle, the different disposal stage is corresponding a plurality of time-parameters respectively, and process chip, when receiving the time-parameters of input, guarantees between a plurality of time-parameters to remain certain rigidity mathematical relationship.
The basic principle of aforementioned schemes is: the inventor carrying out finding after a large amount of in-depth analyses existing CCD is driven to sequential, and all CCD drive sequential and can characterize with constructed sequential, the level relationship that goes out of the parameter of time, level and this three types of cycle-index; Below we analyze the parameter of this three types: it will be apparent to those skilled in the art that in single CCD imaging cycle, the operation that the CCD chip completes can tentatively be decomposed into the photosensitive area signal and derive operation and the read operation of charge packet signal;
Wherein, the photosensitive area signal is derived operation can be divided into " transit time-pulse period-excessive time " three phases chronologically, pulse period comprises again a plurality of individual pulse cycles, and individual pulse exists again high level lasting time and low duration in the cycle;
The read operation of charge packet signal can be divided into " row migration period-overscanning " two stages chronologically, the migration period of wherein going is comprised of a plurality of line periods again, single line period can be subdivided into again " transit time-pulse period-transit time ", and the pulse period in single line period also comprises a plurality of individual pulse cycles; Individual pulse exists again high level lasting time and low duration in the cycle;
From the narration of front, we can find out, the parameter that wherein relates to has nothing but following two kinds: the level state in the time span of each period and each period; Problem about cycle-index, the effect that cycle-index plays in fact is a centre parameter of single cycle time of contact and the institute time relationship between rhythmic total time, by the time by cycle-index and single cycle, multiplies each other and just can obtain rhythmic total time; And, for level state, only have high and low level two states, so CCD drives sequential and can only with the parameter of time, level and this three types of cycle-index, characterize fully.
Preamble has been set forth the multiple time, this wherein just relates to the correlation between these times, as total time and the relation between row migration period time and overscanning time, the photosensitive area signal of each subsegment and the mathematical relationship between single CCD imaging cycle total time, total cycle time and the relation between single cycle time and cycle-index, the read operation of charge packet signal, derives the total time of operation and the relation between transit time and PRT etc.; Although the correlation between each time is more, but between these times, all need to meet certain rigidity mathematical relationship, as the time sum of each subsegment, must equal the total time of single CCD imaging cycle, and they just add, subtract and simple multiplication relation, that that is to say, no matter how the time of subsegment changes, if can guarantee each subsegment and between its upper period, remain a kind of specific " with, poor " relation, just can regulate arbitrarily the subsegment time, thereby obtain the driving sequential of various patterns;
Thought from front, the inventor considers the adjusting right opening of the total time of the most the next subsegment time and upper to the designer, by the work of remaining the mathematical relationship of each subsegment and upper period, give process chip, process chip only need to simply add by fixing mathematical relationship, subtracts, multiplication just can meet the demands; This complexity that not only can make CCD drive the sequential generation system is significantly reduced, what is more important, in the design of driving timing sequence process, the tester can obtain diversified driving sequential by directly perceived, simple parameter being regulated, just revising, flexibility and the applicability of design have greatly been improved, only need a set of equipment just can meet design and testing requirement that dissimilar CCD drives sequential, and, the tester, without grasping special-purpose design language and programming rule, has reduced the difficulty of design.
from aforementioned analysis, being not difficult to find out, creationary root of the present invention comes from: the general character that the inventor has utilized all CCD to drive sequential (namely " can be used the time, the constructed sequential that goes out of the parameter of level and this three types of cycle-index, level relationship characterizes ") carry out the Principles of Regulation of design driven sequential generating apparatus, when giving the tester and regulating authority greatly, by the simple processing unit of function, guarantee the rigidity mathematical relationship between different time, finally obtained a kind of brand-new, low complex degree, the CCD of large flexibility drives sequential generation method, in the present invention, disclosed on the basis of previous designs thought, those skilled in the art only need drive CCD the refinements of various control parameters that will use in sequential, sort out to the parameter of time, level and this three types of cycle-index, just can realize that by a cover CCD, driving the sequential generating apparatus generates the purpose that different CCD drive sequential, this is also the maximum contribution place of the present invention to prior art.
For the ease of those skilled in the art, implement, the invention also discloses following a kind of concrete execution mode:
Described process chip is read control parameter setting module by imaging cycle parameter setting module, photosensitive area signal derivation control parameter setting module and charge packet signal and is formed; Wherein, the charge packet signal is read and is controlled the parameter setting module and by line period, shifted and controlled parameter setting module and overscanning and control the parameter setting module and form again;
Described imaging cycle parameter setting module is according to the input signal of the terminal equipment time span t to the single imaging cycle of ccd image sensor
0Set;
Described photosensitive area signal is derived control parameter setting module following parameter is set: 1) the photosensitive area signal is derived the total time t of operation
1, 2) and derive in operation the length t of the transit time between frame initial time and pulse period initial time
2, 3) and t
2Level state S in time period
T2, S
T2=1 o'clock is high level, S
T2=0 o'clock is low level, 4) derive in operation the time span t in single pulse cycle
3, 5) and derive in operation the cycle-index N in single pulse cycle
k, 6) and derive in operation low level pulse duration length t in the single pulse cycle
4, 7) and t
5Level state S in time period
T5, S
T5=1 o'clock is high level, S
T5=0 o'clock is low level;
t
5For the transit time between finish time pulse period and charge packet signal read operation initial time, t
5Numerical value by the photosensitive area signal, derive to control the parameter setting module and automatically calculate by following formula: t
5=t
1-t
2-(N
k* t
3);
Derive in operation, in the single pulse cycle, high level pulse duration length is designated as t
41, t
41By the photosensitive area signal, deriving control parameter setting module calculates automatically by following formula: t
41=t
3-t
4
Described line period shifts control parameter setting module following parameter is set: in A, charge packet signal read operation process, and the time span t of single line period
6, the cycle-index N of B, single line period
L, the initial time in C, single line period and the length t of the transit time between the pulse period initial time in single line period
7, D, t
7Level state S in time period
T7, S
T7=1 o'clock is high level, S
T7=0 o'clock is low level, the time span t in the single pulse cycle in E, single line period
8, the cycle-index N in the single pulse cycle in F, single line period
p, the low level pulse duration length t in the cycle of the single pulse in G, single line period
9, H, t
10Level state S in time period
T10, S
T10=1 o'clock is high level, S
T10=0 o'clock is low level;
t
10For the transit time between the previous row initial time in finish time pulse period and next line cycle in the cycle, t
10Numerical value by line period, shift to control the parameter setting module and automatically calculate by following formula: t
10=t
6-t
7-(N
p* t
8);
Single pulse in single line period in the cycle high level pulse duration length be designated as t
91, t
91By line period, shifting control parameter setting module calculates automatically by following formula: t
91=t
8-t
9
Described overscanning is controlled the parameter setting module and according to following formula, is automatically calculated the time t of overscan operation
11: t
11=t
0-t
1-(N
L* t
6); When the cycle-index of line period reaches N
LSet point after, continuing is t to the CCD chip as time span
11Overscan operation;
In addition, process chip also guarantees between aforementioned a plurality of parameter to meet following mathematical relationship:
t
0＝t
1+(t
6×N
L)+t
11、t
1＝t
2+(t
3×N
k)+t
5、t
6＝t
7+(t
8×N
p)+t
10；
Aforesaid t
0, t
1, t
2, S
T2, t
3, N
k, t
4, S
T5, t
6, N
L, t
7, S
T7, t
8, N
p, t
9, S
T10Amount to 16 test parameters, by the tester, by terminal equipment, inputed in process chip, process chip generates corresponding pulse sequence signal according to test parameter Control peripheral circuit, and the CCD drive circuit generates corresponding CCD according to the pulse sequence signal and drives signal; Flexible by to the test parameter, can obtain multiple driving sequential, meets the test request of dissimilar CCD chip.
In addition, the invention also discloses a kind of CCD based on aforementioned schemes and drive the sequential generating apparatus, its structure is: described CCD drives the sequential generating apparatus and is comprised of terminal equipment, process chip, CCD drive circuit and peripheral circuit; Between terminal equipment and process chip, by peripheral circuit, communicate to connect, between process chip and CCD drive circuit, by peripheral circuit, communicate to connect;
Terminal equipment is for the human-computer dialogue between tester and process chip;
Peripheral circuit is according to the order production burst clock signal of process chip, and the CCD drive circuit generates corresponding CCD according to the pulse sequence signal and drives signal the operation of driven CCD chip.
Based on aforesaid method and apparatus, the present invention has also proposed following preferred version for the hardware unit that wherein relates to:
Preferably, described terminal equipment is guidance panel, desktop computer or panel computer.When adopting the board-like terminal equipment of operating surface, also terminal equipment, process chip, CCD drive circuit and peripheral circuit overall package can be made, to improve CCD, drive integrated level and the portability of sequential generating apparatus.
Preferably, the physical support of described peripheral circuit adopts the PCB circuit board.
Preferably, described process chip adopts fpga chip.Why adopting fpga chip, is in order effectively to utilize hardware resource of the prior art, and except fpga chip, those skilled in the art also can design independent process chip according to aforementioned schemes.
Useful technique effect of the present invention is: a kind of CCD driving sequential generation method that can generate the different driving sequential once the cover hardware unit that only relies on is provided, and the device that obtains of method thus, the method is simple, directly perceived, do not need the tester to grasp complicated program language and compiling rule, highly versatile, can meet design of driving timing sequence, the test needs of any CCD chip, the hardware device complexity that relies on is lower, with low cost.
The accompanying drawing explanation
Fig. 1, CCD imaging cycle period exploded view;
In Fig. 2, CCD imaging cycle, the photosensitive area signal is derived the period exploded view in operating process;
Period exploded view in Fig. 3, CCD imaging cycle in charge packet signal read operation process;
Fig. 4, system principle schematic diagram of the present invention (in figure, module shown in mark W is peripheral circuit);
Fig. 5,512 * 512 yuan of frame transfer Visible-light CCD emulation timing waveforms;
A section waveform enlarged drawing in Fig. 6, Fig. 5;
B section waveform enlarged drawing in Fig. 7, Fig. 5;
C section waveform enlarged drawing in Fig. 8, Fig. 5.
Embodiment
A kind of CCD drives sequential generation method, it is characterized in that: comprising: for interactive terminal equipment, process chip, CCD drive circuit and for the peripheral circuit of signal transmission between terminal equipment, process chip and CCD drive circuit three; The common cover CCD that forms of described terminal equipment, process chip, CCD drive circuit and peripheral circuit drives the sequential generating apparatus; Operating personnel pass through predefined various control parameters in terminal equipment input processing chip, process chip generates corresponding pulse sequence signal according to different control parameter Control peripheral circuits, pulse sequence signal driver CCD drive circuit generates corresponding CCD and drives signal, thereby can complete the test to dissimilar CCD chip by once cover CCD, driving the sequential generating apparatus; The type of described control parameter has three kinds, i.e. time parameter, level state parameter and cycle-index parameter; In single CCD imaging cycle, the different disposal stage is corresponding a plurality of time-parameters respectively, and process chip, when receiving the time-parameters of input, guarantees between a plurality of time-parameters to remain certain rigidity mathematical relationship.
Further, described process chip is derived and is controlled parameter setting module 2 and charge packet signal and read and control parameter setting module 3 and form by imaging cycle parameter setting module 1, photosensitive area signal; Wherein, the charge packet signal is read and is controlled parameter setting module 3 and by line period, shifted and controlled parameter setting module 4 and overscanning and control parameter setting module 5 and form again;
Described imaging cycle parameter setting module 1 is according to the input signal of the terminal equipment time span t to the single imaging cycle of ccd image sensor
0Set;
Described photosensitive area signal is derived 2 pairs of following parameters of control parameter setting module and set: 1) the photosensitive area signal is derived the total time t of operation
1, 2) and derive in operation the length t of the transit time between frame initial time and pulse period initial time
2, 3) and t
2Level state S in time period
T2, S
T2=1 o'clock is high level, S
T2=0 o'clock is low level, 4) derive in operation the time span t in single pulse cycle
3, 5) and derive in operation the cycle-index N in single pulse cycle
k, 6) and derive in operation low level pulse duration length t in the single pulse cycle
4, 7) and t
5Level state S in time period
T5, S
T5=1 o'clock is high level, S
T5=0 o'clock is low level;
t
5For the transit time between finish time pulse period and charge packet signal read operation initial time, t
5Numerical value by the photosensitive area signal, derive to control parameter setting module 2 and automatically calculate by following formula: t
5=t
1-t
2-(N
k* t
3);
Derive in operation, in the single pulse cycle, high level pulse duration length is designated as t
41, t
41By the photosensitive area signal, deriving control parameter setting module 2 calculates automatically by following formula: t
41=t
3-t
4
Described line period shifts 4 pairs of following parameters of control parameter setting module and sets: in A, charge packet signal read operation process, and the time span t of single line period
6, the cycle-index N of B, single line period
L, the initial time in C, single line period and the length t of the transit time between the pulse period initial time in single line period
7, D, t
7Level state S in time period
T7, S
T7=1 o'clock is high level, S
T7=0 o'clock is low level, the time span t in the single pulse cycle in E, single line period
8, the cycle-index N in the single pulse cycle in F, single line period
p, the low level pulse duration length t in the cycle of the single pulse in G, single line period
9, H, t
10Level state S in time period
T10, S
T10=1 o'clock is high level, S
T10=0 o'clock is low level;
t
10For the transit time between the previous row initial time in finish time pulse period and next line cycle in the cycle, t
10Numerical value by line period, shift to control parameter setting module 4 and automatically calculate by following formula: t
10=t
6-t
7-(N
p* t
8);
Single pulse in single line period in the cycle high level pulse duration length be designated as t
91, t
91By line period, shifting control parameter setting module 4 calculates automatically by following formula: t
91=t
8-t
9
Described overscanning is controlled parameter setting module 5 and according to following formula, is automatically calculated the time t of overscan operation
11: t
11=t
0-t
1-(N
L* t
6); When the cycle-index of line period reaches N
LSet point after, continuing is t to the CCD chip as time span
11Overscan operation;
In addition, process chip also guarantees between aforementioned a plurality of parameter to meet following mathematical relationship:
t
0＝t
1+(t
6×N
L)+t
11、t
1＝t
2+(t
3×N
k)+t
5、t
6＝t
7+(t
8×N
p)+t
10；
Aforesaid t
0, t
1, t
2, S
T2, t
3, N
k, t
4, S
T5, t
6, N
L, t
7, S
T7, t
8, N
p, t
9, S
T10Amount to 16 test parameters, by the tester, by terminal equipment, inputed in process chip, process chip generates corresponding pulse sequence signal according to test parameter Control peripheral circuit, and the CCD drive circuit generates corresponding CCD according to the pulse sequence signal and drives signal; Flexible by to the test parameter, can obtain multiple driving sequential, meets the test request of dissimilar CCD chip.
Further, described terminal equipment is guidance panel, desktop computer or panel computer.
Further, the physical support of described peripheral circuit adopts the PCB circuit board.
Further, described process chip adopts fpga chip.
A kind of CCD based on aforementioned schemes drives the sequential generating apparatus, it is characterized in that: described CCD drives the sequential generating apparatus and is comprised of terminal equipment I, process chip II, CCD drive circuit III and peripheral circuit; Between terminal equipment I and process chip II, by peripheral circuit, communicate to connect, between process chip II and CCD drive circuit III, by peripheral circuit, communicate to connect;
The terminal equipment I is for the human-computer dialogue between tester and process chip II;
Peripheral circuit is according to the order production burst clock signal of process chip II, and CCD drive circuit III generates corresponding CCD according to the pulse sequence signal and drives signal the operation of driven CCD chip.
Further, described terminal equipment is guidance panel, desktop computer or panel computer.
Further, the physical support of described peripheral circuit adopts the PCB circuit board.
Further, described process chip adopts fpga chip.
Although the present invention only provides a kind of embodiment, but from the introduction of this paper and the shown CCD imaging process of each exploded view (being Fig. 1,2,3), finding out, the various control parameters that in this embodiment, listed 16 time-parameters, level state parameter and cycle-index parameter related in the imaging process to CCD chip of the prior art have carried out exhaustive.
Embodiment:
Below as an example of the timing Design of 512 * 512 yuan of comparatively complicated frame transfer Visible-light CCDs of sequential example, the solution of the present invention is described: sequential Parameter design table sees the following form:
According to upper table, CCD is tested, the emulation timing waveform that obtains is as shown in Fig. 5,6,7,8.
Claims (9)
1. a CCD drives sequential generation method, it is characterized in that: comprising: for interactive terminal equipment, process chip, CCD drive circuit and for the peripheral circuit of signal transmission between terminal equipment, process chip and CCD drive circuit three; The common cover CCD that forms of described terminal equipment, process chip, CCD drive circuit and peripheral circuit drives the sequential generating apparatus; Operating personnel pass through predefined various control parameters in terminal equipment input processing chip, process chip generates corresponding pulse sequence signal according to different control parameter Control peripheral circuits, pulse sequence signal driver CCD drive circuit generates corresponding CCD and drives signal, thereby can complete the test to dissimilar CCD chip by once cover CCD, driving the sequential generating apparatus; The type of described control parameter has three kinds, i.e. time parameter, level state parameter and cycle-index parameter; In single CCD imaging cycle, the different disposal stage is corresponding a plurality of time-parameters respectively, and process chip, when receiving the time-parameters of input, guarantees between a plurality of time-parameters to remain certain rigidity mathematical relationship.
2. CCD according to claim 1 drives sequential generation method, it is characterized in that: described process chip is read control parameter setting module (3) by imaging cycle parameter setting module (1), photosensitive area signal derivation control parameter setting module (2) and charge packet signal and is formed; Wherein, the charge packet signal is read and is controlled parameter setting module (3) and by line period, shifted and controlled parameter setting module (4) and overscanning control parameter setting module (5) forms again;
Described imaging cycle parameter setting module (1) is according to the input signal of the terminal equipment time span t to the single imaging cycle of ccd image sensor
0Set;
Described photosensitive area signal is derived control parameter setting module (2) following parameter is set: 1) the photosensitive area signal is derived the total time t of operation
1, 2) and derive in operation the length t of the transit time between frame initial time and pulse period initial time
2, 3) and t
2Level state S in time period
T2, S
T2=1 o'clock is high level, S
T2=0 o'clock is low level, 4) derive in operation the time span t in single pulse cycle
3, 5) and derive in operation the cycle-index N in single pulse cycle
k, 6) and derive in operation low level pulse duration length t in the single pulse cycle
4, 7) and t
5Level state S in time period
T5, S
T5=1 o'clock is high level, S
T5=0 o'clock is low level;
t
5For the transit time between finish time pulse period and charge packet signal read operation initial time, t
5Numerical value by the photosensitive area signal, derive to control parameter setting module (2) and automatically calculate by following formula: t
5=t
1-t
2-(N
k* t
3);
Derive in operation, in the single pulse cycle, high level pulse duration length is designated as t
41, t
41By the photosensitive area signal, deriving control parameter setting module (2) calculates automatically by following formula: t
41=t
3-t
4
Described line period shifts control parameter setting module (4) following parameter is set: in A, charge packet signal read operation process, and the time span t of single line period
6, the cycle-index N of B, single line period
L, the initial time in C, single line period and the length t of the transit time between the pulse period initial time in single line period
7, D, t
7Level state S in time period
T7, S
T7=1 o'clock is high level, S
T7=0 o'clock is low level, the time span t in the single pulse cycle in E, single line period
8, the cycle-index N in the single pulse cycle in F, single line period
p, the low level pulse duration length t in the cycle of the single pulse in G, single line period
9, H, t
10Level state S in time period
T10, S
T10=1 o'clock is high level, S
T10=0 o'clock is low level;
t
10For the transit time between the previous row initial time in finish time pulse period and next line cycle in the cycle, t
10Numerical value by line period, shift to control parameter setting module (4) and automatically calculate by following formula: t
10=t
6-t
7-(N
p* t
8);
Single pulse in single line period in the cycle high level pulse duration length be designated as t
91, t
91By line period, shifting control parameter setting module (4) calculates automatically by following formula: t
91=t
8-t
9
Described overscanning is controlled parameter setting module (5) and according to following formula, is automatically calculated the time t of overscan operation
11: t
11=t
0-t
1-(N
L* t
6); When the cycle-index of line period reaches N
LSet point after, continuing is t to the CCD chip as time span
11Overscan operation;
In addition, process chip also guarantees between aforementioned a plurality of parameter to meet following mathematical relationship:
t
0＝t
1+(t
6×N
L)+t
11、t
1＝t
2+(t
3×N
k)+t
5、t
6＝t
7+(t
8×N
p)+t
10；
Aforesaid t
0, t
1, t
2, S
T2, t
3, N
k, t
4, S
T5, t
6, N
L, t
7, S
T7, t
8, N
p, t
9, S
T10Amount to 16 test parameters, by the tester, by terminal equipment, inputed in process chip, process chip generates corresponding pulse sequence signal according to test parameter Control peripheral circuit, and the CCD drive circuit generates corresponding CCD according to the pulse sequence signal and drives signal; Flexible by to the test parameter, can obtain multiple driving sequential, meets the test request of dissimilar CCD chip.
3. CCD according to claim 1 drives sequential generation method, and it is characterized in that: described terminal equipment is guidance panel, desktop computer or panel computer.
4. CCD according to claim 1 drives sequential generation method, it is characterized in that: the physical support of described peripheral circuit adopts the PCB circuit board.
5. CCD according to claim 1 drives sequential generation method, it is characterized in that: described process chip adopts fpga chip.
6. the CCD based on claim 1 scheme drives the sequential generating apparatus, it is characterized in that: described CCD drives the sequential generating apparatus and is comprised of terminal equipment (I), process chip (II), CCD drive circuit (III) and peripheral circuit; Between terminal equipment (I) and process chip (II), by peripheral circuit, communicate to connect, between process chip (II) and CCD drive circuit (III), by peripheral circuit, communicate to connect;
Terminal equipment (I) is for the human-computer dialogue between tester and process chip (II);
Peripheral circuit is according to the order production burst clock signal of process chip (II), and CCD drive circuit (III) generates corresponding CCD according to the pulse sequence signal and drives signal the operation of driven CCD chip.
7. CCD according to claim 6 drives the sequential generating apparatus, and it is characterized in that: described terminal equipment is guidance panel, desktop computer or panel computer.
8. CCD according to claim 6 drives the sequential generating apparatus, it is characterized in that: the physical support of described peripheral circuit adopts the PCB circuit board.
9. CCD according to claim 6 drives the sequential generating apparatus, it is characterized in that: described process chip adopts fpga chip.
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|---|---|---|---|
| CN201310353387.4A CN103402062B (en) | 2013-09-02 | 2013-09-02 | CCD driver' s timing generation method and driver' s timing generating apparatus thereof |
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|---|---|---|---|
| CN201310353387.4A CN103402062B (en) | 2013-09-02 | 2013-09-02 | CCD driver' s timing generation method and driver' s timing generating apparatus thereof |
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Cited By (3)
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| CN103837781A (en) * | 2014-03-24 | 2014-06-04 | 中国电子科技集团公司第四十四研究所 | CCD detecting device |
| CN104780327A (en) * | 2014-01-14 | 2015-07-15 | 爱思开海力士有限公司 | Apparatus and method for generating timing signals based on processor, and CMOS image sensor using the same |
| CN103826074B (en) * | 2014-03-24 | 2017-01-25 | 中国电子科技集团公司第四十四研究所 | Vertical time sequence drive circuit for charge coupled device (CCD) |
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| JP4110309B2 (en) * | 1999-04-02 | 2008-07-02 | 富士フイルム株式会社 | CCD drive unit |
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| CN102508141A (en) * | 2011-10-26 | 2012-06-20 | 西安电子科技大学 | Measurement system of performance parameters of charge coupled device (CCD) chip |
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| CN1635780A (en) * | 2003-12-31 | 2005-07-06 | 中国科学院西安光学精密机械研究所 | Linear array CCD light integral time self-adaptive control method and device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104780327A (en) * | 2014-01-14 | 2015-07-15 | 爱思开海力士有限公司 | Apparatus and method for generating timing signals based on processor, and CMOS image sensor using the same |
| CN103837781A (en) * | 2014-03-24 | 2014-06-04 | 中国电子科技集团公司第四十四研究所 | CCD detecting device |
| CN103837781B (en) * | 2014-03-24 | 2016-03-23 | 中国电子科技集团公司第四十四研究所 | CCD proving installation |
| CN103826074B (en) * | 2014-03-24 | 2017-01-25 | 中国电子科技集团公司第四十四研究所 | Vertical time sequence drive circuit for charge coupled device (CCD) |
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| CN103402062B (en) | 2016-06-01 |
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