CN103368721A - Computing method for transparent clock in time-triggered Ethernet - Google Patents
Computing method for transparent clock in time-triggered Ethernet Download PDFInfo
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- CN103368721A CN103368721A CN2013103102356A CN201310310235A CN103368721A CN 103368721 A CN103368721 A CN 103368721A CN 2013103102356 A CN2013103102356 A CN 2013103102356A CN 201310310235 A CN201310310235 A CN 201310310235A CN 103368721 A CN103368721 A CN 103368721A
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Abstract
The invention provides a computing method for a transparent clock in time-triggered Ethernet to solve the problem that an existing computing method enables a network not to reach high synchronization precision. The transparent clock is a transmission time delay of a PCF frame used for clock synchronization in the time-triggered Ethernet from a beginning device to an assigned device of a transmission access. Frequency synchronization of a network device is achieved by the adoption of a classification master-slave synchronization mode. A device in the center of the time-triggered Ethernet is selected as much as possible to serve as a main root device, a device connected with the main root device in the network is a primary slave device, the primary slave device carries out the frequency synchronization on the main root device, a device connected with the primary slave device is called as a secondary slave device (in essence, the primary slave device is a primary device of the secondary slave device), the second slave device carries out the frequency synchronization on the primary slave device, and the frequency synchronization of the whole network is achieved successively. The transparent clock is equal to the sum of link time delays of all two adjacent devices of the PCF frame from the beginning device to the assigned device of the transmission access plus the sum of residence time of PCF frames of various devices between the beginning device to the assigned device, and both residence time of the beginning device and residence time of the assigned device are zero.
Description
Technical field:
The present invention is relevant with the computational methods of the transparent clock of time triggering Ethernet.
Background technology:
AS6802 triggers the design that Ethernet (TTE) proposes for the time, and this scheme has provided a roughly thinking that realizes real-time network.The equipment that time triggers in the Ethernet (TTE) is comprised of TTE switch and end system, each equipment can be carried out and solidify function (permanence function), a very important parameter is arranged: transparent clock (transparent clock:TC) in solidifying function.
The concept that transparent clock is also arranged among this external IEEE1588 v2, and the transparent clock concept derives from IEEE1588 v2 among the AS6802.
The calculating of transparent clock has had influence on the synchronous effect of time triggering Ethernet (TTE) to a great extent, improves one's methods so be necessary to study design and the proposition of transparent clock.TCP/IP five layer models are application layer, transport layer, network layer, data link layer, physical layer from putting in place down.And the realization of transparent clock is will utilize the MAC layer to do auxiliary calculate and realize in application layer among the IEEE1588 v2.
Fig. 2 shows is that clock skew among the IEEE1588 v2 is measured and the network delay measurement.Main equipment is at t
1Constantly send the Sync frame, from equipment at t
2Constantly received this frame.Main equipment after sending the Sync frame, and then send comprise Sync frame delivery time the Follow_Up frame to from equipment, after equipment receives this frame, just known t
1And t
2Constantly.Constantly send the Delay_Req frame to main equipment at t3, and and t
4Constantly receive this frame, the Delay_Resp frame is exactly will be with t
4Constantly send to from equipment, at this moment known t from equipment
1, t
2, t
3, t
4Constantly.Can obtain clock skew clk_offset and the chain-circuit time delay link_delay of master-slave equipment.
clk_offset=[（t
1+t
4）-（t
2+t
3）]/2
link_delay=[（t
4-t
1）-（t
3-t
2）]/2
Fig. 3 shows is that link delay among the IEEE1588 v2 is measured.Equipment 1 is at t
1Send the Pdelay_Req frame to equipment 2, at t
2Equipment 2 receives the Pdelay_Req frame from equipment 1 constantly; At t
3Equipment 2 sends to equipment 1 and comprises the moment t that equipment 2 receives the Pdelay_Req frame constantly
2The Pdelay_Resp frame to equipment 1, at t
4Equipment 1 has received the Pdelay_Resp frame constantly; Equipment 2 sends the follow-up supervention of Pdelay_Resp frame and send and comprise Pdelay_Resp frame delivery time t
3The Pdelay_Resp_Follow_Up frame reach equipment 1, equipment 1 has been known t thus
1, t
2, t
3, t
4Four moment.Equipment 1 arrives the delay link_delay expression formula of equipment 2,
link_delay=[（t
4-t
1）-（t
3-t
2）]/2
Equipment 1 is network equipments adjacent in the network and that have physical link directly to link to each other with equipment 2, and said process is exactly in the time delay of measuring this physical link.
The calculating of the transparent clock of prior art mainly relies on application layer software, so t
3The moment and t
2Difference constantly just has very large uncertainty, and this uncertainty can make the inaccessible synchronization accuracy requirement of network.For example, the accuracy error of the local clock of equipment 1 and equipment 2 place equipment is 0.2 ‰, because the uncertainty of CPU state has caused t
3The moment and t
2The uncertainty of the difference is constantly supposed t
3The moment and t
2Difference constantly be 1ms then during this period of time the time difference of equipment 1 and equipment 2 be 200ns; Linkage length is 10m, and the propagation rate of frame is 2/3 light velocity, and then transmission delay is 50ns.Bring formula link_delay=[(t into
4-t
1)-(t
3-t
2)]/2, the phenomenon for negative can appear postponing if equipment 1 local clock is slower than equipment 2 local clocks, and obviously infeasible; If equipment 1 local clock is faster than equipment 2 local clocks then the retardation ratio actual delay that equipment 1 is measured is about 100ns.Must pull-in frequency synchronization mechanism (namely allowing their clock speed be consistent) for fear of the generation of this phenomenon, and do not provide detailed Frequency Synchronization scheme and performing step among the IEEE1588 v2.
Prior art needs hardware to do auxiliary (physical circuit MAC layer realize) to do time mark in addition, and comes specific implementation synchronous by upper layer software (applications).The Sync frame, the Delay_Req frame, the Pdelay_Req frame, the sending and receiving of Pdelay_Resp frame constantly all will be done time mark.
Summary of the invention:
The objective of the invention is to propose a kind of the MAC layer can simple realization Frequency Synchronization, the time that computational accuracy is high is triggered the computational methods of the transparent clock in the Ethernet.
The present invention is achieved in that
Time is triggered the computational methods of transparent clock in the Ethernet, transparent clock is to trigger the PCF frame that is used for clock synchronous in the Ethernet arrives the designated equipment transmission from beginning equipment time delay the time, the PCF frame has a transparent clock territory, this frame is every all can be added to the residence time in this equipment the transparent clock territory through an equipment, in the process that sends, also chain-circuit time delay can be added to the transparent clock territory, the PCF frame is just calculated by the transparent clock territory of this frame fully from the time delay that an equipment arrives the designated equipment transmission like this, the value in transparent clock territory is transparent clock, and computational methods are as follows:
Adopt the synchronous mode of HMS hierarchical master-slave device frequency to realize the Frequency Synchronization of the network equipment: the equipment that select time triggers Ethernet transmission link topological structure center is the root main equipment, being attached thereto the equipment that connects in the network transmission link is that the first order is from equipment, the first order is carried out Frequency Synchronization from equipment to the root main equipment, be called the second level from equipment with the first order from the equipment of equipment connection, the first order is in fact that the second level is from the main equipment of equipment from equipment, Frequency Synchronization is carried out from equipment to the first order from equipment in the second level, the like realize the Frequency Synchronization of whole transmission link
Transparent clock=PCF frame from the beginning equipment of transmission channel to designated equipment the residence time sum of chain-circuit time delay sum+beginning equipment each the equipment PCF frame in the middle of the designated equipment of all adjacent two equipment, the residence time of beginning equipment and designated equipment is 0
Residence time be exactly equipment receive the PCF frame the time be carved into the moment that sends this PCF frame, the value of residence time deducts the moment value of this PCF frame of reception for the moment value that sends the PCF frame.
The method of master-slave equipment Frequency Synchronization at different levels is as follows:
Main equipment is every F
0The individual crystal oscillator cycle sends a PCF
FreqFrame is given from equipment, should receive adjacent two PCF from device statistics
FreqThe crystal oscillator number of cycles F of local clock between the frame
1, then compare F
0And F
1Size, frequency is according to F
0And F
1Size do corresponding adjustment; If F
0＜F
1Then should be from the equipment local clock every F
0/ (F
1-F
0) the individual crystal oscillator cycle counts less a clock cycle and can realize Frequency Synchronization, if F
0F
1Then local clock is every F
1/ (F
0-F
1) the individual crystal oscillator cycle, how clock cycle of counting can be realized Frequency Synchronization, if F
0=F
1Clock frequency does not adjust, and frequency has adjusted later 2
nThe output of (n 〉=2) frequency-dividing clock is as the time reference of this grade master-slave equipment.
The chain-circuit time delay method of measurement of adjacent two equipment is as follows:
The second equipment is at t
2Constantly receive from the first equipment at t
1This frame is returned to the first equipment behind the Peer_Sync_TC frame that constantly sends at once, the first equipment receives the Peer_Sync_TC frame that returns from the second equipment constantly at t3, and such the first equipment just can calculate the chain-circuit time delay link_delay of Peer_Sync_TC frame from the first equipment to the second equipment 2 soon at the MAC layer:
link_delay=(t
3-t
1)/2
So just obtained the chain-circuit time delay of adjacent two equipment rooms.
The present invention is the kinetic measurement that realizes transparent clock at the MAC layer, be characterized in can the cycle the test link time delay, under the prerequisite that guarantees the transparent clock certainty of measurement, greatly improved the maintainability of system and the time of having reduced is triggered the complexity of Ethernet (TTE) clock synchronous.The present invention has following characteristics:
(1), proposed a kind ofly to trigger the new method of kinetic measurement transparent clock in the Ethernet (TTE) in the time, the method realizes at the MAC layer fully.
(2), proposed a kind ofly to trigger in the Ethernet (TTE) the periodic measurement master-salve clock difference on the frequency synchronous method of line frequency of going forward side by side in the time.
(3), provided the master-salve clock collocation method of equipment in time triggering Ethernet (TTE) the Frequency Synchronization process.
Beneficial effect of the present invention is as follows:
(1), realizes the chain-circuit time delay of kinetic measurement LA Management Room at the MAC layer.Can measure equipment time of running near real delay parameter, when adopt different communication links or when communication link length is changed without the manual configuration linkage length.
Reason: time-delay can not be measured the chain-circuit time delay of PCF frame on communication link accurately when according to the linkage length configuration link, reconfigures again length time delays cumbersome and different physical links when changing link and all is not quite similar.Therefore, the equipment that triggers in the Ethernet (TTE) for the time disposes also non-easy thing of delay parameter.If the periodic form that sends the PCF frame of employing measures then the problems referred to above can both solve, when link changes, respective change will occur in the propagation delay time of PCF frame from an equipment to another equipment, like this measurement result really and network configuration become simpler.
(2), through clock frequency synchronously after, the impact that the transparent clock that Measuring Time triggers Ethernet (TTE) device transmission PCF frame is brought by local clock difference separately is very little.
Reason: the local clock that local clock advances the middle respective switch of the synchronously rear time triggering Ethernet of overfrequency (TTE) and end system all aligns to master clock.Can think that their clock does not have difference, so the measurement of the chain-circuit time delay of PCF frame and the residence time in an equipment is more accurate.
Description of drawings:
Fig. 1 is the physical link latency measurement figure of neighbouring device.
Fig. 2 is the delay request-responder drawing among prior art IEEE 1588 v2.
Fig. 3 is the reciprocity delay mechanism figure among prior art IEEE 1588 v2.
Fig. 4 is the frequency departure figure of neighbouring device local clock.
Fig. 5 is the clock frequency synchronization scenario block diagram of realizing at the MAC layer of the present invention.
Fig. 6 is not for containing the network diagram of redundant link (arrive designated equipment and contain many paths).
Fig. 7 is the network diagram that contains redundant link.
Fig. 8 triggers each device frequency Error Graph in the Ethernet time, from network master clock more away from the device frequency synchronism deviation larger.
Embodiment:
As shown in Figure 1, at t
1Equipment 1 sends Peer_Sync_TC frame, t constantly
2Constantly equipment 2 has received this frame and " bounce-back " time equipment 1 at once, t
3Equipment 1 is received this frame constantly.Can calculate equipment 1 to the chain-circuit time delay link_delay of equipment 2.
link_delay=(t
3-t
1)/2
The delay of measuring with top method has error, and main cause is that there is deviation in the local clock of two equipment.The below will discuss Frequency Synchronization, to reduce the deviation of above-mentioned time delay.
As shown in Figure 4, the equipment 1 periodic PCF that sends
FreqFrame is to equipment 2.At T
1Constantly send PCF
FreqFrame, the moment of equipment 2 this moment is t
1, and at moment t
1' receive this frame; At T
2Constantly send PCF
FreqFrame, the moment of equipment 2 this moment is t
2, and at moment t
2' receive this frame.Because the frequency departure f of equipment 2 and equipment 1 local clock
OffsetSatisfy following relationship,
f
offset=（f
2-f
1）/f
1=[（t
2-?t
1）-（T
2-T
1）]/（t
2-?t
1）
Can know t by analysis
1'-t
1=t
2'-t
2Be t
2'-t
1'=t
2– t
1Thereby
f
offset=（f
2-f
1）/f
1=[（t
2’-?t
1’）-（T
2-T
1）]/（t
2’-?t
1’）
When the MAC layer is realized Frequency Synchronization, PCF
FreqThe cycle that frame sends is arranged to 1/2
x(x is positive integer) second, when x=8, send a PCF every 125ms
FreqFrame.The frequency of supposing selected clock is f this clock per second f cycle of vibration then, if a frequency deviation of clock Δ f, then this clock per second vibrates f ± Δ f cycle.If PCF
FreqThe transmission cycle of frame be 125ms then frequency be that the clock of f ± Δ f is many (or few) vibration f/8 cycles of Δ of the clock of f than frequency.Be that the 125ms internal reference clock oscillation cycle is f/8, receive PCF
FreqFrame from the clock oscillation cycle be (f ± Δ f)/8.
In gigabit (or 10,000,000,000) Ethernet, with a frequency with the crystal oscillator acquisition 1GHz of built-in PLL frequency multiplier, be 1ns each cycle of oscillation, has 10 in the 1s
9Individual cycle of oscillation; If there is 0.02 ‰ deviation in crystal oscillator, then 1s interior cycle of oscillation of number maximum deviation is 2*10
4Individual.125ms interior cycle of oscillation of number maximum deviation is 2500, if just many 2500, then have 125002500 cycle of oscillation in 125ms, if fruit has just been lacked 2500, then have 124997500 cycle of oscillation in 125ms.Therefore receive adjacent two PCF from clock
FreqImage duration, number N cycle of oscillation of local clock can locally preserve, and can think through 125ms when from clock oscillation N cycle.
Frequency synchronization method of the present invention is as follows:
As shown in Figure 5, as the equipment 1 of master clock every F
0The individual crystal oscillator cycle sends a PCF
FreqFrame is given as the equipment 2 from clock, receives adjacent two PCF from the clock statistics
FreqThe crystal oscillator number of cycles F of local clock between the frame
1Then compare F
0And F
1Size.The frequency adjustment member will be according to F
0And F
1Size do corresponding adjustment; If F
0＜F
1Then calculate from the clock local clock every F
0/ (F
1-F
0) clock cycle can be realized Frequency Synchronization in individual crystal oscillator cycle inhibition one (counting less), if F
0F
1Then calculate from the clock local clock every F
1/ (F
0-F
1) the individual crystal oscillator cycle, how clock cycle of counting can be realized Frequency Synchronization, if F
0=F
1Clock frequency does not adjust.Frequency has adjusted later 2
nThe output of (n 〉=2) frequency-dividing clock triggers the time reference of equipment in the Ethernet (TTE) as the time.
Time is triggered the configuration of Ethernet (TTE) master-salve clock:
The clock that select time triggers Ethernet (TTE) center is that master clock carries out Frequency Synchronization.Fig. 6 selects equipment 1 to be the master clock of whole network, and Fig. 7 selects equipment 1 to be the master clock of whole network.Other clock frequencies in the network are synchronous to master clock frequency.When the time triggers in Ethernet (TTE) topology when from an equipment to another one equipment many paths being arranged configuration network and will pay special attention to, among Fig. 7 in the topological structure equipment 4 can not carry out Frequency Synchronization to the clock of equipment 2, equipment 5, equipment 6 and equipment 7 to equipment 3 Frequency Synchronization.Illustrate: equipment 2, equipment 3 and equipment 8 are take equipment 1 as the Frequency Synchronization benchmark among Fig. 6, and equipment 4, equipment 5, equipment 6 and equipment 7 are take equipment 2 as the Frequency Synchronization benchmark, and equipment 9 and equipment 10 are take equipment 3 as the Frequency Synchronization benchmark; Equipment 2, equipment 3, equipment 5, equipment 6 and equipment 7 are take equipment 1 as the Frequency Synchronization benchmark among Fig. 7, and equipment 4 is take equipment 3 as the Frequency Synchronization benchmark.
Error analysis:
If there is 0.02 ‰ deviation in the 1GHz clock.Fast then every vibration once is 10 if vibrate
9/ 1000020000 ≈ 0.9999800004ns; If vibration partially slowly then every vibration once is 10
9/ 999980000 ≈ 1.0000200004ns.Receiving adjacent two PCF from clock
FreqDuring frame and the error of master clock mostly be most 1 cycle of oscillation about 1ns, from the time trigger in the Ethernet (TTE) master clock more away from error larger, as shown in Figure 8.
Claims (3)
1. the time is triggered the computational methods of transparent clock in the Ethernet, it is characterized in that transparent clock is to trigger the PCF frame that is used for clock synchronous in the Ethernet arrives the designated equipment transmission from the beginning equipment of transmission channel time delay the time, the PCF frame has a transparent clock territory, this frame is every all can be added to the residence time in this equipment the transparent clock territory through an equipment, in the process that sends, also chain-circuit time delay can be added to the transparent clock territory, the PCF frame is just calculated by the transparent clock territory of this frame fully from the time delay that an equipment arrives the designated equipment transmission like this, the value in transparent clock territory is transparent clock, and computational methods are as follows:
Adopt the synchronous mode of HMS hierarchical master-slave device frequency to realize the Frequency Synchronization of the network equipment: the equipment that select time triggers Ethernet transmission link topological structure center is the root main equipment, being attached thereto the equipment that connects in the network transmission link is that the first order is from equipment, the first order is carried out Frequency Synchronization from equipment to the root main equipment, be called the second level from equipment with the first order from the equipment of equipment connection, the first order is in fact that the second level is from the main equipment of equipment from equipment, Frequency Synchronization is carried out from equipment to the first order from equipment in the second level, the like realize the Frequency Synchronization of whole transmission link
Transparent clock=PCF frame from the beginning equipment of transmission channel to designated equipment the residence time sum of chain-circuit time delay sum+beginning equipment each the equipment PCF frame in the middle of the designated equipment of all adjacent two equipment, the residence time of beginning equipment and designated equipment is 0,
Residence time be exactly equipment receive the PCF frame the time be carved into the moment that sends this PCF frame, the value of residence time deducts the moment value of this PCF frame of reception for the moment value that sends the PCF frame.
2. the time according to claim 1 is triggered the computational methods of transparent clock in the Ethernet, it is characterized in that the method for master-slave equipment Frequency Synchronization at different levels is as follows:
Main equipment is every F
0The individual crystal oscillator cycle sends a PCF
FreqFrame is given from equipment, should receive adjacent two PCF from device statistics
FreqThe crystal oscillator number of cycles F of local clock between the frame
1, then compare F
0And F
1Size, frequency is according to F
0And F
1Size do corresponding adjustment; If F
0＜F
1Then should be from the equipment local clock every F
0/ (F
1-F
0) the individual crystal oscillator cycle counts less a clock cycle and can realize Frequency Synchronization, if F
0F
1Then local clock is every F
1/ (F
0-F
1) the individual crystal oscillator cycle, how clock cycle of counting can be realized Frequency Synchronization, if F
0=F
1Clock frequency does not adjust, and frequency has adjusted later 2
nThe output of (n 〉=2) frequency-dividing clock is as the time reference of this grade master-slave equipment.
3. the time according to claim 1 is triggered the computational methods of transparent clock in the Ethernet, it is characterized in that the chain-circuit time delay method of measurement of adjacent two equipment is as follows:
The second equipment is at t
2Constantly receive from the first equipment at t
1This frame is returned to the first equipment behind the Peer_Sync_TC frame that constantly sends, the first equipment is at t at once
3Constantly receive the Peer_Sync_TC frame that returns from the second equipment, such the first equipment just can calculate the chain-circuit time delay link_delay of Peer_Sync_TC frame from the first equipment to the second equipment 2 soon at the MAC layer:
link_delay=(t
3-t
1)/2
So just obtained the chain-circuit time delay of adjacent two equipment rooms.
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