CN103345936A - Write-in circuits and read-out circuits of arbitrary-K-value DRAM and eight-value DRAM - Google Patents

Abstract

The invention relates to write-in circuits and read-out circuits of an arbitrary-K-value DRAM and an eight-value DRAM. The write-in circuits and the read-out circuits have same structure characteristics, and the write-in circuits are each designed to provide a multi-value signal increased by delta than write-in circuit input; an output waveform of a memory cell is considered to be smaller than an input waveform or be of an unequal step shape, the read-out circuits are each designed for correction, and an irregular multi-value signal is converted into a regular (equal step) multi-value signal. The write-in circuits and the read-out circuits both have good quantified shaping effects; when a change of a Cj voltage is not greater than an upper new threshold or a lower new threshold, original multi-value information can be easily recovered, so the write-in circuits and the read-out circuits have anti-jamming capability and multi-value information recovery capability. The write-in circuits and the read-out circuits are mainly applied to the fields of VLSI and other digital IC technologies, such as an FPGA, a CPLD, a semi-custom or a full-custom ASIC, a memorizer and the like.

Description

Write circuit and read circuit of arbitrary K value and 8-value DRAM

technical field

The present invention is directed to a divisional application with application number: 201110097206.7, and belongs to the field of digital integrated circuits, specifically a writing circuit and a reading circuit of an arbitrary K value and 8-value DRAM.

Background technique

With the rapid development of MOS integrated circuit technology, the integration scale is getting larger and higher, and VLSI (Very Large Scale Integration) has some shortcomings: ① First, on the VLSI substrate, the wiring takes up more than 70% of the silicon Chip area; in programmable logic devices (such as FPGA and CPLD), there are also a large number of programmable internal wiring (including programmable connection switches, such as fuse switches, anti-fuse switches, floating gate programming components, etc.), To connect each logic function block or input/output to complete a specific function circuit, wiring (including programming connection switches) accounts for a large cost of materials. Reducing the proportion of wiring costs becomes a very important issue. ② From the perspective of information transmission, the use of multi-valued signals can reduce the number of connections; for each connection to transmit digital information, binary signals carry the lowest amount of information, and multi-valued signals carry more information than binary signals. ③ From the perspective of information storage, the use of multi-valued signals can increase the density of information storage, especially the use of MOS transistor gate capacitance to store information (used in dynamic random access memory DRAM), because the same capacitor stores more information than binary Large, multi-valued DRAM can greatly increase information storage density than binary DRAM. At present, the development of multi-valued devices has been widely carried out. Toshiba and Sandisk have cooperated with 70nm CMOS technology and 2bit/unit multi-valued technology to realize a storage capacity of 8Gbit on a 146mm ² chip; Toshiba and SanDisk of the United States have published a 16gbit NAND flash memory implemented with 43nm process and 2bit/cell multi-value technology. The 8Gbit product developed by Samsung adopts 63nm CMOS technology and 2bit/unit multi-value technology. The successful development and commercialization of 4-value memory is an important step in multi-value research, but it is necessary to control or change the switching threshold V _tn of the tube. The method of changing the threshold is to use multi-level ion implantation technology in the semiconductor manufacturing process, or control the floating gate The threshold is controlled by methods such as the amount of electrons stored in the electrode. The development of DRAM with more than 4 values has not been found to be successful.

Semiconductor memory can be divided into read-only memory ROM and random access memory RAM. RAM is divided into two types: bipolar type and MOS type. Bipolar RAM has a high working speed, but its manufacturing process is complicated, its power consumption is high, and its integration level is low. It is mainly used in high-speed working occasions. MOS-type RAM is divided into static random access memory SRAM and dynamic random access memory DRAM (Dynamic Random Access Memory) two. The principle of DRAM storing information is based on the charge storage effect of the gate capacitance of the MOS transistor. Since the capacity of the gate storage capacitor is very small (usually only a few picofarads), and the leakage current cannot be absolutely equal to zero, the charge storage time is limited; in order to replenish the missing charge in time to avoid the loss of the stored signal, it must be timed Supplementing charge to the gate storage capacitor is usually called refresh or regeneration, and the necessary refresh control circuit must be supplemented when DRAM works. DRAM is composed of a large rectangular array of memory cells, supporting logic circuits for reading and writing to the array, and refresh circuits to maintain the integrity of stored data. The simplest available single-transistor dynamic memory cell in DRAM. The memory cells are arranged in a matrix structure by rows and columns, and are decoded by two decoding circuits. X-direction decoding is called row decoding, and its output line is called word line, which selects all memory cells in a row in the memory matrix. Y-direction decoding is also called column decoding, and its output lines are called bit lines. Because each readout of the single-transistor dynamic memory cell is a destructive readout, the storage capacitor provides charges to the capacitor C _B on the bit line, so that the charge of the storage capacitor is reduced and needs to be restored immediately. A sensitivity recovery/ The sense amplifier, after using the sensitivity restoration/sense amplifier, completes the restoration of the original stored data of the memory cell while reading out the data each time. Generally, DRAM is designed as a word length of n bits (that is, a word has n bits, such as 4 bits, 8 bits or N bits), and when the address decoder decodes each word line output is valid, there are n (such as 4 , 8 or N) memory cells are selected at the same time, so that these selected memory cells are read and written through the read/write control circuit, and the DRAM read and write control circuit controls the input and output of data information. External control signals to the memory include read signal _RD , write signal _WR , chip select signal _CS and so on. The number of input and output data of DRAM is 1 bit, 2 bits, 4 bits or N bits. In addition to multi-bit input and output, in order to improve integration and reduce the number of device pins, large-capacity DRAM often adopts 1-bit input, 1-bit output, and address time-sharing input, and there are corresponding input buffers and output buffers. and output latches, etc.

Existing technology and existing problems:

1. For the multi-value signal stored in the storage capacitor of DRAM, it is difficult to read the data (binary data is determined by the presence or absence of the charge of the storage capacitor, and it is easy to read; multi-value signal readout It is necessary to distinguish the magnitude, and multi-valued signals may be attenuated and deformed during transmission. Conventional amplifiers are prone to serious distortion of multi-valued signals, and the input and output of equal-step multi-valued signals in DRAM specifications cannot be obtained. Conventional sense amplifier methods cannot Read multi-valued signal, can not realize the storage unit circuit of arbitrary K value and 8-value DRAM, have not yet found to have the successful development of the DRAM of more than 4 values.For overcoming this difficulty, can not simply consider multi-valued storage unit by traditional method, must Consider simultaneously the multi-value write circuit and the multi-value read circuit that cooperate with multi-value storage unit.To word length 4, 8 or N data, then corresponding write circuit and read-out circuit have 4, 8 One or N. The write-in circuit and the read-out circuit are based on the premise that the equal ladder multi-value input and output signals of the DRAM are required to be obtained, and the multi-value DRAM storage unit circuit, the write-in circuit and the read-out circuit should be according to a general inventive concept To design these three kinds of circuits, these three kinds of circuits are closely related, but when practical, the quantities of the three kinds of circuits are different (the whole of a kind of circuit cannot be formed), and designing according to a general inventive concept can overcome the problem of reading out stored in the capacitor. Difficulties with multivalued signal data.

2. In the realization of multi-valued circuits, the existing technology to control the threshold of MOS transistors has great disadvantages: ① the amplitude of the control threshold is limited (because the ion implantation concentration is limited), and the resolution of opening is low; and the amplitude of the control threshold in the process is often Changing the performance of the MOS tube, for example, the reduction of the threshold voltage will lead to a sharp increase in the cut-off current, and the adjustment of the threshold voltage will affect the performance and stability of the tube, and a stable V _tn is very important. For multi-valued memory, the amount of electrons injected into the floating gate is continuously changing and needs to be controlled very finely, and the voltage levels of each threshold cannot reach a quasi-stable state. Therefore, the current practical voltage-type multi-valued circuits are not larger than 4-valued circuits, and the application of more-valued circuits is difficult. ② Only the amplitude of the threshold value can be controlled, and the turn-on nature of the MOS tube cannot be changed (such as changing ≥t conduction to <t conduction), and the multi-valued logic gate must have two kinds of MOS tubes with turn-on properties to make the structure of the combination circuit the simplest , For example, the circuit structures of multi-valued NOT gate, multi-valued right shift gate and multi-valued follower should be exactly the same, but the threshold voltage and its opening properties are different. However, the current technology that only controls the threshold amplitude makes the structure of the above-mentioned multi-value gate very different and complex, which affects its realization. ③ It is necessary to add an additional process of ion implantation, and the threshold can only be controlled in the semiconductor manufacturing process, which not only increases the complexity of the process, but also cannot be controlled by the user later, or the threshold cannot be programmed by the user.

K-value DRAM (K>2) is commonly referred to as multi-value DRAM, but in designing storage unit circuits, writing and reading circuits, the circuit structure is often related to K, and at this time write the K value (called K-value DRAM, etc.) It is more convenient, and some content introductions, non-structural descriptions, or nouns that have nothing to do with K values can often use customary names (such as multi-valued signals, multi-valued gates).

Contents of the invention

The purpose of the invention is to disclose a writing circuit and a reading circuit of any K value and 8-value DRAM.

Above-mentioned purpose realizes by following technical scheme:

1. the write-in circuit of a kind of arbitrary K value DRAM of the present invention is realized like this: this write-in circuit as shown in Figure 4, in the write-in circuit of described K value DRAM, establish K=3,4, 5,...; K-1=L threshold-variable PMOS transistors _Qak are adopted, k=1, 2, 3,..., L, and the gate of the transistor _Qak is connected to the input of the writing circuit via a variable threshold circuit D _inj , the new threshold value of variable-threshold PMOS transistor Qak _k is ta _k , the voltage drop between the source and drain is 0 when the transistor Qak _k is turned on; the source of the transistor Qak _k is connected to the power supply V _dd , and the voltage ratio of V _dd is selected The maximum logic levels V _Dinj (L) and V _Douj (L) of the write circuit input and read circuit output are high Δ, Δ is the downward DC level shift between the input and output of the voltage follower F; using L-1 Diode _Dan , n=2, 3,..., L, the conduction voltage of the diode _Dan is V _Don ; the positive pole and the negative pole of _Dan are connected to the drain of the threshold-variable PMOS transistor Qa _n-1 and the transistor Qa respectively The drain of _n ; the drain of the tube Qa _L is grounded through the constant current source _Ij , and the drain of the tube Qa _L is connected to the constant current source I _j to keep the current flowing through the conduction diode at the same fixed value, and the drain of the tube Qa _L Pole forms the output G _wrij of the write circuit, and the output G _wrij of the write circuit is connected to the write bit line input of the memory cell circuit; ta _k is selected as the adjacent logic level V _Dinj of the K value signal of the write circuit input D _inj ( The average value of k) and V _Dinj (k-1) (V _Dinj (k)+V _Dinj (k-1))/2, that is, ta _k is the middle of V _Dinj (k) and V _Dinj (k-1) value, V _Dinj (k)>V _Dinj (k-1); the K value signal of the input circuit D _inj is the same as the K value signal of the output D _{outj of} the readout circuit and the K value signal of the norm of DRAM input and output are the same The difference between adjacent logic levels of input D _inj is equal, the difference of adjacent logic levels of output D _outj is equal, and the step voltages of input D _inj and output D _out j are the same, and the step voltage is V _Don , that is Satisfy V _Dinj (m)-V _Dinj (m-1)=V _Doutj (m)-V _Doutj (m-1)=V _Don , m=1, 2, 3,..., L, V _Dinj (m) and V _Doutj (m) are respectively the logic level of the input of the write circuit and the output logic value of the readout circuit; the output G _wrij of the write circuit is Δ higher than the K value signal input by the write circuit except for 0 level, The 0 level is still 0, and the K value writing circuit is also called the K value writing boosting circuit.

2. the readout circuit of a kind of arbitrary K value DRAM of the present invention is realized like this: readout circuit as shown in Figure 5, the readout circuit of this arbitrary K value DRAM is according to the described arbitrary K value DRAM of above-mentioned 1 Write in the same structural feature of the circuit and form, in the readout circuit of described K value DRAM, set K=3,4,5,...; Adopt K-1=L variable threshold type PMOS transistor Qb _k , k=1, 2, 3,..., L, the gate of tube Qb _k is connected to the input G _rdij of the readout circuit through the variable threshold circuit, the new threshold value of variable threshold PMOS tube Qb _k is tb _k , tube Qb When _k is turned on, the voltage drop between the source and the drain is 0; G _rdij is connected to the output of the read bit line of the memory cell circuit, the source of the tube Qb _k is connected to the power supply V _dc , and the voltage of V _dc is selected to be equal to the input and read of the write circuit The maximum logic levels V _Dinj (L) and V _Douj (L) output by the output circuit (that is, V _dc = V _Dinj (L) = V _Douj (L)); use L-1 diodes Db _n , n=2, 3, ..., L, the turn-on voltage of the diode Db _n is V _Don ; the anode and cathode of Db _n are respectively connected to the drain of the threshold-variable PMOS transistor Qb _n-1 and the drain of the transistor Qb _n ; the threshold-variable PMOS The drain of the tube Qb _L is grounded through the constant current source _Ij , and the drain of the tube Qb _L is connected to the constant current source I _j so that the current flowing through the conduction diode remains at the same fixed value, and a readout circuit is formed at the drain of the tube Qb _L The output D _outj of; choose tb _{k to} be the average value ( _{V Grdij (} k)+ _{V Grdij} (k-1))/2, that is, tb _k is the intermediate value of V _Grdij (k) and V _Grdij (k-1), V _Grdij (k)>V _Grdij (k-1); the readout circuit outputs D _outj The characteristics of the signal written into the circuit input D _inj and the standard K value signal of the DRAM input and output are the same: the difference between the adjacent logic levels of the input D _inj is equal, and the adjacent logic levels of the output D _outj The differences are equal, and the step voltages of input D _inj and output D _outj are the same, and the step voltage is V _Don , that is, V _Dinj (m)-V _Dinj (m-1)=V _Doutj (m)-V _Doutj (m -1)=V _Don , m=1, 2, 3,..., L, V _Dinj (m) and V _Doutj (m) are the logic levels of the input of the writing circuit and the output logic value of the reading circuit of m respectively ; The input G _rdij of the readout circuit is an irregular K value signal from the output of the storage unit circuit, and the irregular K value signal is compared to the standard equal steps of the input and output of the DRAM, the input of the write circuit, and the output of the readout circuit The K value signal is inconsistency in the logic level amplitude; the output D _outj of the readout circuit is a standardized K value signal of equal steps, that is, the readout circuit converts the non-standard K value signal input G _rdij into a standardized K value signal of equal steps output D _outj , and the K value readout circuit is also called the K value readout correction circuit.

Note: the storage unit circuit of a kind of arbitrary K value DRAM of the present invention is realized like this: As shown in Figure 1, the storage unit circuit of described K value DRAM is made up of voltage follower F, the gate storage capacitance C of F _j and two CMOS transmission gates G ₁ and G ₂ , the capacitor C _j is used to store the K value signal, the voltage follower F includes NMOS transistor Q _m1 and NPN transistor Q _m2 , the gate of transistor Q _m1 is connected to one end of capacitor C _j C _mij , that is, C _mij is the input of voltage follower F, the other end of C _j is grounded, the source of tube Q _m1 takes over the gate of Q _m2 and resistor R _m1 , the other end of R _m1 is grounded, and the emitter of tube Q _m2 The electrode F _olij is grounded through the constant current source I _j , the emitter of Q _m2 is connected to the constant current source I _j so that the emitter load of the tube Q _m2 is a constant current source, the emitter F _olij of the tube Q _m2 is the output of F, and the tube Q _m1 Both the drain and the collector of the tube Q _m2 are connected to the power supply V _dd , and the voltage of V _dd is selected to be Δ higher than the maximum value of the K value logic level of the write circuit input and the read circuit output, and Δ is the input of the voltage follower F Downward DC level shift between outputs; the input of the transmission gate G ₁ is connected to the write bit line G _wrij , the output of the transmission gate G ₁ is connected to the input C _mij of F, the control input of the transmission gate G ₁ is connected to the write pulse w _ri , and the transmission The input of the gate _G2 is connected to the output F _olij of F, the output of the transmission gate _G2 is connected to the read bit line G _rdij , the control input of the transmission gate _G2 is connected to the read pulse r _di , the write pulse w _ri and the read pulse r _di From the control circuit of DRAM; when the write pulse w _ri comes, the transmission gate G ₁ is turned on, and the K value signal of the write bit line G _wrij is transmitted to the storage capacitor C _j , and the capacitor C _j receives the K value of the write bit line G _wrij Value signal, the K value signal of capacitor C _j is the K value signal of F input C _mij ; when the write pulse w _ri arrives in the future, the transmission gate _G1 will be cut off, the storage capacitor C _j and the outside world will be DC open circuit, and the capacitor C _j will store The K value signal remains unchanged, that is, it has a memory function; when the read pulse r _di comes, the transmission gate _G2 is turned on, and the K value signal of the F output F _olij is transmitted to the read bit line G _rdij ; the write bit line G _wrij and the read bit line G _rdij are the input and output of the storage unit circuit respectively; the input and output of the storage unit circuit are respectively connected to the output of the write circuit and the input of the read circuit; the K value signal output by F must be corresponding to the F input signal K value signal, F input and output information are the same, that is, F output has no information loss, and F output has no information loss. The K value signal stored by C _j is an increased K value signal, and the increased K value signal is except for 0 level. A signal Δ higher than the K value signal input by the write circuit, where the 0 level is still 0; the increased K value signal stored by C _j is the output from the write circuit, that is, the write circuit that provides the C _j storage signal The output is also an increased K value signal; the increased K value signal stored by C _j is transmitted through F To the read bit line G _rdij , an irregular K value signal is formed on G _rdij , that is, the output of the storage unit circuit is an irregular K value signal, and the irregular K value signal is compared with the DRAM input and output and the write circuit The K-value signals of the standard equal steps of the input and readout circuit output are inconsistent in logic level amplitude; the input signal of the readout circuit is an irregular K-value signal from the output _Grdij of the storage unit circuit, and the output of the readout circuit is for storage The unit circuit outputs a standardized equal-step K value signal obtained by correcting the non-standard K value signal, and the corrected standardized equal-step K value signal is used as a corrected readout of the information stored in the memory unit circuit.

In the K-value DRAM storage unit circuit, the constant current source _Ij can be replaced by a resistor _Rj .

The present invention also has the following technical characteristics:

(1) According to the write-in circuit of a kind of arbitrary K-value DRAM described in above-mentioned 1, get K=8, draw the write-in circuit of 8-value DRAM, as shown in Figure 2, wherein adopt 7 variable-threshold type PMOS transistors Qak _k , k=1, 2, 3, ..., 7, the gate of the transistor Qak _k is connected to the input D _inj of the writing circuit via the variable threshold circuit, the new threshold value of the threshold variable PMOS transistor Qak _k is ta _k , When the tube _Qak is turned on, the voltage drop between the source and the drain is 0; the source of the tube _Qak is connected to the power supply V _dd , and the voltage of V _dd is selected to be higher than the maximum logic level V _Dinj ( 7) and V _Douj (7) high Δ, Δ is the downward DC level shift between the input and output of the voltage follower F; adopt 6 diodes Dan, _n =2, 3, ..., 7, diode _Dan The conduction voltage of V Don is V _Don ; the positive pole and negative pole of Da _n are respectively connected to the drain of variable threshold PMOS transistor Qa _n-1 and the drain of transistor Qa _n ; the drain of transistor Qa ₇ is grounded through constant current source I _j , the drain of the tube Qa ₇ is connected to the constant current source I _j to keep the current flowing through the conduction diode at the same fixed value, the output G _wrij of the writing circuit is formed on the drain of the tube Qa ₇ , and the output G _wrij of the writing circuit is connected to The write bit line input of the memory cell circuit; selecting ta _{k is} the average value (V Dinj (k) of adjacent logic levels V _Dinj (k) and V _Dinj (k-1) of the 8-value signal of the write circuit input D _inj )+V _Dinj (k-1))/2, that is, select ta _k as the intermediate value of V _Dinj (k) and V _Dinj (k-1), V _Dinj (k)＞V _Dinj (k-1); write The characteristics of the 8-value signal of the input circuit input D _inj and the output D _{outj of} the readout circuit and the standard equal-level 8-value signal of the DRAM input and output are the same: the difference of each adjacent logic level of the input D _inj is equal, and the output D The differences between the adjacent logic levels of _outj are equal, and the step voltages of the input D _inj and the output D _outj are the same, and the step voltage is V _Don , that is, V _Dinj (m)-V _Dinj (m-1)=V _Doutj ( m)-V _Doutj (m-1)=V _Don , m=1, 2, 3,..., 7, V _Dinj (m) and V _Doutj (m) are respectively the input logic of the write circuit and the output logic of the read circuit The value is the logic level of m; the write circuit output G _wrij is Δ higher than the 8-value signal input by the write circuit except for the 0 level, and the 0 level is still 0. The 8-value write circuit is also called 8-value write into the booster circuit.

(2) Get K=8 in the readout circuit of arbitrary K value DRAM according to above-mentioned 2, draw the readout circuit of 8-value DRAM, as shown in Figure 3, the readout circuit of this 8-value DRAM is according to above-mentioned (1) Formed by the same structural feature of the write-in circuit of the 8-value DRAM, wherein 7 threshold-variable PMOS transistors Qb _k are adopted, k=1, 2, 3, ..., 7, the Qb _k transistor The gate is connected to the input G _rdij of the readout circuit through the variable threshold circuit, and the new threshold value of the variable threshold PMOS transistor Qb _k is tb _k ; when the transistor Qb _k is turned on, the voltage drop between the source and the drain is 0; G _rdij is connected to The read bit line output of the memory cell circuit, the source of the tube Qb _k is connected to the power supply V _dc , and the voltage of V _dc is selected to be equal to the maximum logic level V _Dinj (7) and V _Douj (7) of the write circuit input and the read circuit output ); adopt 6 diodes Db _n , n=2, 3, ..., 7, the conduction voltage of diode Db _n is V _Don ; the anode and cathode of Db _n are respectively connected to the drain of variable threshold PMOS transistor Qb _n-1 electrode and the drain of the tube Qb _n ; the drain of the variable-threshold PMOS transistor Qb ₇ is grounded through the constant current source I _j , and the drain of the tube Qb ₇ is connected to the constant current source I _j to keep the current flowing through the conduction diode at the same constant value, forms the output D _outj of the readout circuit at the drain of the tube Qb ₇ ; selects tb _k to be the adjacent logic levels _{V Grdij (} k) and V _Grdij (k-1 ) (V _Grdij (k)+V _Grdij (k-1))/2, that is, select tb _k as the middle value of V _Grdij (k) and V _Grdij (k-1), V _Grdij (k)＞ V _Grdij (k-1); the characteristics of the 8-valued signal of the signal of the output D _outj of the readout circuit and the standards of the input D _inj of the write circuit and the input and output of the DRAM are the same: each adjacent logic circuit of the input D _inj The differences of the levels are equal, the difference between the adjacent logic levels of the output D _outj is equal, and the step voltages of the input D _inj and the output D _outj are the same, and the step voltage is V _Don , which satisfies V _Dinj (m)-V _Dinj (m- 1)=V _Doutj (m)-V _Doutj (m-1)=V _Don , m=1, 2, 3,..., 7, V _Dinj (m) and V _Doutj (m) are the inputs of the write circuit respectively And readout circuit output logical value is the logic level of m; Readout circuit input G _rdij is the non-standard 8-value signal from memory unit circuit output, and described non-standard 8-value signal is exactly contrasting DRAM input and output and writing The 8-value signal of the standard equal ladder of the circuit input and the output of the readout circuit is inconsistent with the logic level amplitude; the output D _outj of the readout circuit is a standard 8-value signal of the equal ladder, that is, the readout circuit will not standardize the 8-value signal The signal G _rdij is converted into a standard equal-level 8-value signal D _outj , and the 8-value readout circuit is also called an 8-value readout correction circuit.

Note: The 8-value storage unit circuit corresponding to the write-in circuit and read-out circuit of the 8-value DRAM is obtained as follows; take K=8 in the storage unit circuit of any K-value DRAM, and select the voltage ratio of the power supply V _dd to the write-in circuit The output logic value of the input and readout circuit is 7, the logic level is high Δ, and Δ is the downward DC level offset between the input and output of F, and the storage unit circuit of the 8-value DRAM is obtained, as shown in Figure 1, the 8 The value DRAM storage unit circuit is composed of a voltage follower F, a gate storage capacitor C _j of F, and two CMOS transmission gates _G1 and _G2 . The capacitor C _j is used to store 8-value signals. The voltage follower F includes an NMOS transistor Q _m1 and NPN tube Q _m2 , the gate of tube Q _m1 is connected to one end C _mij of capacitor C _j , that is, C _mij is the input of voltage follower F, the other end of C _j is grounded, and the source of tube Q _m1 is connected to the gate of Q _m2 electrode and resistance R _m1 , the other end of R _m1 is grounded, the emitter F _olij of tube Q _m2 is grounded through constant current source I _j , and the emitter of Q _m2 is connected to constant current source I _j so that the emitter load of tube Q _m2 is constant current The source, the emitter F _olij of the tube Q _m2 is the output of F, the drain of the tube Q _m1 and the collector of the tube Q _m2 are both connected to the power supply V _dd ; the input of the transmission gate G ₁ is connected to the write bit line G _wrij , and the transmission gate G ₁ The output of the transmission gate G 1 is connected to the input C _mij of F, the control input of the transmission gate G ₁ is connected to the write pulse w _ri , the input of the transmission gate G ₂ is connected to the output F _olij of F, the output of the transmission gate G ₂ is connected to the read bit line G _rdij , and the transmission The control input of the gate _G2 is connected to the read pulse r _di , the write pulse w _ri and the read pulse r _di come from the control circuit of the DRAM; when the write pulse w _ri comes, the transfer gate G ₁ is turned on, and the write bit line The 8-value signal of G _wrij is transmitted to the storage capacitor C _j , and the capacitor C _j receives the 8-value signal of G _wrij , and the 8-value signal of capacitor C _j is the 8-value signal of F input C _mij ; when the write pulse w _ri arrives in the future, The transmission gate G ₁ is cut off, the storage capacitor C _j is open to the outside world, and the 8-value signal stored in the capacitor C _j remains unchanged, that is, it has a memory function; when the readout pulse r _di comes, the transmission gate G ₂ is turned on, and the The 8-value signal of F output F _olij is transmitted to the read bit line G _rdij ; the write bit line G _wrij and the read bit line G _rdij are the input and output of the storage unit circuit respectively; the input and output of the storage unit circuit are respectively connected to the output of the write circuit and the input of the readout circuit; the 8-value signal output by the voltage follower F must be an 8-value signal corresponding to the F input, and the F input and output information are the same, that is, there is no information loss at the F output, and no information loss at the F output requires C _j to be stored The 8-value signal is an increased 8-value signal, and the increased 8-value signal is a signal that is Δ higher than the 8-value signal input by the write circuit except for the 0 level, wherein the 0 level is still 0; the input of the storage unit circuit signal is the output from the write circuit, and the write circuit output is provided to the storage The signal input by the unit circuit is an increased 8-value signal; the increased 8-value signal is transmitted to the read bit line G _rdij is an irregular 8-value signal, that is, the output of the storage unit circuit is an irregular 8-value signal. The standard 8-value signal is the standard 8-value signal that compares the DRAM input and output with the write circuit input and read circuit output. The logic level amplitude is inconsistent; the read circuit input signal is not standardized from the memory unit circuit output. 8-value signal, the output of the readout circuit is a standardized 8-value signal obtained by correcting the non-standard 8-value signal output by the storage unit circuit, and the standardized 8-valued signal obtained by the correction is used as a pair of storage Corrective readout of information stored in the unit circuit.

The concrete content of the present invention is described as follows:

(A) Advantages of the memory cell circuit, write circuit and read circuit of the present invention. ①Advantages of the storage unit circuit: the circuit structure is simple and the cost is extremely low. Because K>2, each capacitor C _j stores K value information is larger than the amount of information stored in binary information. Obviously, the larger the K, the more information the storage unit stores, and C _j is the gate capacitance of the MOS transistor, and the cost is extremely low , in addition, the storage unit circuit is only composed of _G1 , _G2 and F, and the circuit structure is simple, which is very beneficial to multi-valued DRAM; generally, it is required that the amount of information stored in DRAM is as large as possible, that is, the number of storage unit circuits is required to be as large as possible , it is required that the amount of information stored by each capacitor C _j is as much as possible, and the circuit structure is required to be simple so that the area occupied by the silicon chip is as small as possible. The memory cell circuit of the present invention meets this requirement; 2. The advantage of the readout circuit: it has a good quantization Shaping function, that is, it has the ability to restore the original multi-valued information, which is used for anti-jamming and refreshing. The output D _outj curve obtained by inputting G _rdij with a sine wave continuous signal and passing through the readout circuit is a discontinuous (corrected to a standard equal-step) multi-valued signal, which shows that the readout circuit has a good similarity to 4 rounding and 5 rounding Quantization shaping effect, when the input G _rdij voltage rises or falls (such as leakage and interference effects) does not exceed the upper and lower thresholds, the output D _outj is still the multi-valued information of the standard equal steps (restoring the original information), that is, it has the restoring original Multi-valued information capability, this capability is used to improve anti-interference performance and refresh; ③Advantages of writing into the circuit: it has a good quantization and shaping effect (similar to the quantization effect of rounding to 5), and obtains a stable increase in multiples that meets the requirements value information; the output G _wrij curve obtained after the sine wave continuous signal input D _inj is written into the circuit is discontinuous multi-valued information (increased multi-valued information), when the input D _inj voltage rises or falls (such as interference effects) When the upper and lower new thresholds are not exceeded, the output G _wrij still restores the original (increased) multi-value information, that is, it has the ability to restore the original increased multi-value information, and this ability can also be used for anti-jamming and refreshing. Restoring the original multi-valued information and refreshing are both for information. DRAM has a large storage capacity and a small area of silicon wafers, so it must be required: the number of memory cell circuits is large, and the number of write circuits and read circuits is as small as possible; their numbers are not equal. Multi-valued DRAM storage units (including conventional binary DRAM storage units) are arranged in a matrix structure by rows and columns, and the row decoding output line, that is, the word line (row selection line) selects all of the rows (one word line) in the storage matrix. storage unit. For the word length of n bits (such as 4 bits, 8 bits or N bits), when the row address decoder decodes that the output of each word line is valid, there are n (such as 4, 8 or N) memory cells simultaneously Selected (through the CMOS transmission gate of this unit, the multi-valued information stored in it is connected with the outside, and information exchange is carried out), n root write bit lines and read bit lines are respectively connected to a memory cell on the selected bit, at each A write circuit is connected to the root write bit line, and a read circuit is connected to each read bit line, so that these selected memory cells can be read and written by the read/write control circuit through the read circuit and the write circuit. . The multi-value storage unit circuit, the multi-value read circuit and the multi-value write circuit are very important components. The storage unit circuit of any K value and 8-value DRAM maintains a very simple structure, and only the write and read circuit structure varies with K The value size is different, and the advantages are quite significant. In addition to multi-bit input and output, in order to improve integration and reduce the number of device pins, large-capacity DRAM often adopts 1-bit input, 1-bit output and address time-sharing input. At this time, the memory cells are still arranged in rows and columns. In a matrix structure, the data serial input and serial output tasks are completed by the DRAM input buffer, output buffer (note: DRAM input and output refers to DRAM data input and output), address input buffer part and control circuit part, and sometimes even Addresses can also be entered serially. If the storage unit circuit, write circuit and readout circuit are classified as a whole circuit, it is extremely expensive and impractical. In practical storage unit circuits, the number of write circuits and readout circuits is very different. ; The storage unit circuit, the write circuit and the read circuit are different in quantity and space, and they are three closely related circuits that are uniformly designed according to a general inventive concept according to information characteristics.

(B) Three types of circuits focus on information features, that is, memory cell circuits, write circuits and read circuits focus on information: information storage, information writing and information reading. There is no information loss requirement for the information stored in the storage unit circuit: what the write circuit sends to the storage unit circuit is increased multi-value information. Requirements for outputting non-standard multi-valued information by the storage unit circuit: the readout circuit corrects the non-standard multi-valued information into a standardized multi-valued information output with equal steps. The storage unit circuit also focuses on information features. The storage unit circuit has three information features: multi-value information storage, multi-value information reception and multi-value information sending: ①Information reception: multi-value information written on the bit line G _wrij is transmitted to the storage capacitor C _j , so that capacitor C _j can receive multi-valued information C _mij ; ② information storage: when G ₁ is cut off, capacitor C _j and the external DC resistance are almost infinite, and capacitor C _j can store multi-valued signals very well; ③ information sending: transmission The gate G ₂ is turned on, and the multi-value information output by the voltage follower F is transmitted to the read bit line G _rdij . The storage unit circuit, the writing circuit and the reading circuit have the same important information characteristics: the information characteristics of the input of the storage unit circuit and the output of the writing circuit are consistent, and they are all multi-valued information that is increased; the output of the storage unit circuit and the input of the reading circuit The information characteristics of the information are consistent, and they are all non-standard multi-valued information; the information characteristics of the input circuit input and the output of the read circuit are consistent, and they are all standardized multi-valued information with equal steps (Note: the multi-valued information with equal steps in this specification It is consistent with the information characteristics of the DRAM input and output, and the DRAM input and output is the DRAM data input and output).

(C) According to a general inventive conception, two kinds of closely related write-in circuits and read-out circuits are uniformly designed. The structural features of the read-out circuit of any K-value DRAM and the write-in circuit of any K-value DRAM are the same, as shown in Fig. 4 and Fig. 5, or comparing Fig. 2 and Fig. 3, it can be seen immediately that the structural features of the write-in circuit and the read-out circuit are the same (the variable-threshold PMOS transistors and diodes of the two circuits have the same number of tubes, and the connection mode between the tubes same, etc.), but with different parameters and different functions.

According to any K-value DRAM storage unit, the same information characteristics of the write and read circuits, a general idea used in the design is expressed as follows:

The input and output of DRAM is a standardized multi-valued signal. If the conventional thinking is followed, the capacitor C _j directly receives the standardized multi-valued signal input by the DRAM and saves it, that is, the capacitor C _j stores a standardized multi-valued signal, and the _stored standard The multi-valued signal of the voltage follower F passes through the voltage follower F, and there will be a loss of information at the output of F, so the conventional thinking is not available. Now change the idea of design, in order to ensure that the output of F does not lose information, the input of F must be different from the information characteristics of the specification, and the multi-valued signal with increased height can be used to transmit to the capacitor C _j (namely, the input of F). The requirements of the multi-valued signal are met: it can not only ensure that the F output will not lose information, but also ensure that the non-standard multi-valued signal of the F output can be corrected into a standardized multi-valued signal, which can be read out as information correction, so that from From the outside, the readout is still a correct multi-value signal, indicating that the readout circuit can read a standardized multi-value signal with the same characteristics as the DRAM input and output, that is, the readout circuit corrects the non-standard multi-value signal to a standardized multi-value signal Signal; It can be seen that, according to the above-mentioned information characteristics, and the requirement that the input circuit input and the output circuit of the readout circuit are multi-valued signals designed to design the write circuit and the readout circuit, then the difficulty in reading is overcome.

Description of drawings

Fig. 1. is the storage cell circuit diagram of a kind of arbitrary K value and 8-value DRAM relevant to the present invention;

Fig. 2. is the writing circuit diagram of a kind of 8-value DRAM of the present invention;

Fig. 3. is the readout circuit diagram of a kind of 8-value DRAM of the present invention;

Fig. 4. is the writing circuit diagram of a kind of K value DRAM of the present invention;

Fig. 5. is the readout circuit diagram of a kind of K value DRAM of the present invention;

Fig. 6. is the first kind of PMOS tube variable threshold circuit diagram and the variable threshold type PMOS tube symbol diagram related to the present invention;

Fig. 7. is the second kind of PMOS tube variable threshold circuit diagram and the variable threshold type PMOS tube symbol diagram related to the present invention;

Fig. 8. replaces the first kind of PMOS transistor variable threshold circuit diagram and variable threshold type PMOS transistor symbol diagram with V _dc replacing V _dd in Fig. 6;

Fig. 9. is the second kind of PMOS transistor variable threshold circuit diagram and the variable threshold type PMOS transistor symbol diagram with V _dc instead of V _dd in Fig. 7;

Figure 10 is a circuit diagram and symbol diagram of an existing multi-output precision mirror constant current source;

Fig. 11 is the storage unit circuit of the writing circuit and reading circuit and the related 8-value DRAM of the present invention, w _ri , r _di , D _inj , G _wrij , C _mij , F under the sequential action of w _ri and r _di Waveform diagrams of _olij , G _rdij and D _outj separated up and down successively;

Fig. 12. is the oscillogram of the writing circuit input _Dinj and the readout circuit _output Doutj of the 8-value DRAM of the present invention under the action of _wri and rdi _in sequence;

Fig. 13. is the oscillogram of input D _inj and output G _wrij of the writing circuit of 8-value DRAM of the present invention under the effect of w _ri ;

Fig. 14. is the oscillogram of input G _rdij and output D _outj of the readout circuit of 8-value DRAM of the present invention under the effect of r _di ;

Fig. 15. is the input C _mij and the output F _olij of the voltage follower F of the storage unit circuit of 8-value DRAM of the present invention and the waveform diagram when there is w _ri effect;

Fig. 16 is the storage unit circuit of the writing circuit and reading circuit of the present invention and the related 8-value DRAM, D _inj , G _wrij , C _mij , F _olij , G _rdij and D under the sequential action of w _ri and r _di Waveform diagram of up and down of _outj ;

Fig. 17 is the writing circuit of the 8-value DRAM of the present invention. When w _ri = 0, the transmission gate G ₁ is cut off and the writing circuit input D _inj is changed to a sine wave, the writing circuit input D _inj and the writing circuit output G _wrij Waveform diagram;

Fig. 18. is the readout circuit of the 8-value DRAM of the present invention when _rdi =0 transmission gate _G2 is cut off and when the readout circuit input _Grdij is changed to a sine wave, the readout circuit input _Grdij and the readout circuit output _Doutj Waveform diagram;

Figure 19. Circuit and symbol diagram for commonly used CMOS transmission gates.

Detailed ways

The present invention is specifically described further below:

Embodiment 1: Description of the circuit information function of the storage unit.

The storage unit circuit has three information functions of multi-valued information storage, multi-valued information reception and multi-valued information sending: ①Information reception: It can be seen from Figure 1 that when the write pulse w _ri arrives, the transmission gate _G1 is turned on, and the The multi-valued information of the write bit line G _wrij is transmitted to the storage capacitor C _j , so that the capacitor C _j receives the multi-valued information C _mij ; the reception of the capacitor C _j is a charging and discharging process, and whether charging or discharging depends on the original stored information of the capacitor C _j and For the received information, the charging and discharging time constant is related to the capacitance of C _j , and C _j is usually only a few picofarads and cannot be larger; ②Information storage: when the write pulse w _ri arrives in the future, the transmission gate G 1 will be cut off, and the transmission gate G ₁ will be cut off by It can be seen from Figure 1 that the storage capacitor _Cj is only connected to the gate of the NMOS transistor _Qm1 and the output of the CMOS transmission gate _G1 , the gate input resistance of the transistor _Qm1 is close to an open circuit, and _G1 is also close to an open circuit when it is cut off. At this time, the capacitance The resistance between C _j and the external DC is almost infinite, and multi-valued signals can be well stored with capacitor C _j ; ③Information sending: It can be seen from Figure 1 that when the readout pulse r _di arrives, the transmission gate G ₂ is turned on, and the The multi-valued information output by the voltage follower F is transmitted to the read bit line G _rdij , even if the capacitor C _j has a weak leakage and F is not perfect, which affects the multi-valued information output by F and transmitted to the read bit line G _rdij , but the read circuit is still Ability to correct multi-valued information to the correct specification.

Note: When the transmission gate _G1 is cut off, it is theoretically required that C _j and the outside world be a DC open circuit, that is, the DC resistance is infinite. In fact, C _j and the outside world are high resistance (almost no DC path), and there is still a weak leakage current in reality, C _j The stored multi-valued signal can only be kept for a certain period of time, so all DRAMs need to add a refresh circuit to restore the original stored information by regular refreshing.

The voltage follower F in the storage unit circuit is very important, but if the F input information is used improperly, the actual F output will lose multi-valued information, and the cost of storing multi-valued information with the capacitor C _j (F input) is extremely low. Conventional DRAM uses capacitor C _j to store binary information. The information content of binary information is the lowest, and the information content of multi-valued information is higher than that of binary information. Of course, it is more cost-effective to store multi-valued information with capacitor C _j than to store binary information. The reasons for the loss of multi-valued information at the output of F are described as follows: If the capacitor C _j is connected to the input of an ideal voltage follower _FA , the voltage amplification factor of the ideal voltage follower _FA is always 1, and there is no DC offset, then F The output voltage of _A is exactly the same as the voltage of capacitor C _j , that is, the output of F _A is exactly the same as the multi-valued information stored in capacitor C _j . In reality, there is no ideal voltage follower, the voltage magnification of the actual voltage follower (F in the present invention) is less than 1, and there is a DC offset Δ, when the voltage on the capacitor C _j is less than Δ (such as logic value 1, Its logic level = V _Don < Δ), the F output is 0, that is, the logic value of the stored signal of C _j is not 0, but the logic value of the F output signal is 0; in order to overcome the shortcoming of DC offset and avoid the loss of F output information , what the writing circuit provides to the storage unit circuit is a multi-valued signal with an increase in Δ, and the multi-valued signal with an increase in Δ after passing through F will output a non-standard multi-valued signal, and further use the readout circuit to correct this to a standard, etc. Ladder multivalued signal. Considering that the ladder voltage of the input D _inj and the output D _outj are the same, the ladder voltage is equal to the conduction voltage V _Don of the diode, and the maximum logic level of the input D _inj and the output D _outj is equal to L times of V _Don (LV _Don ), so the power supply The voltage V _dd is Δ higher than the above maximum logic level, Δ is easily calculated or measured from F, and C _j is usually only a few picofarads.

The CMOS transmission gate in the storage unit circuit is shown in Figure 19, that is, Figure 19 is the circuit and symbol diagram of a common CMOS transmission gate. The CMOS transmission gate is composed of a P-channel and an N-channel enhancement MOSFET (ie NMOS transistor Q _G1 and PMOS The transistor Q _G2 ) is connected in parallel, and the CMOS transmission gate itself has a CMOS inverter (that is, the NMOS transistor Q _G4 and the PMOS transistor Q _G3 ). The CMOS transmission gate circuit is simple, can transmit signals in both directions, and is often used as an analog switch.

Embodiment 2: Proof that the writing circuit of arbitrary K value and 8-value DRAM satisfies design requirements.

The writing circuit of DRAM with arbitrary K value is shown in Figure 4, which needs to be proved to meet the design requirements: when the logic value of the writing circuit input D _inj is 0, 1, 2, 3, 4, ..., L-2, L-1, When L, the logic value of the write circuit output G _wrij is still sequentially 0, 1, 2, 3, 4, ..., L-2, L-1, L; but the logic value of G _wrij corresponds to the logic level V _Gwrij (n ) is higher than the logic level V _Dinj (n) corresponding to the logic value of D _inj by Δ(n=1～L) except the 0 level, and the 0 level is still 0, that is, V _Gwrij (0)=V _Dinj (0)= 0V, V _Gwrij (1) = V _Dinj (1) + Δ, V _Gwrij (2) = V _Dinj (2) + Δ, ..., V _Gwrij (L-1) = V _Dinj (L-1) + Δ , V _Gwrij (L) = V _Dinj (L) + Δ, V _Dinj (k) > V _Dinj (k-1); ta _k is the adjacent logic level V _Dinj (k) and V _Dinj input by the write circuit The intermediate value of (k-1), satisfying V _Dinj (k-1)<ta _k <V _Dinj (k), k=1, 2, 3, 4,..., L-2, L-1, L, That is, satisfy the inequality 0<ta ₁ <V _Dinj (1)<ta ₂ <V _Dinj (2)<ta ₃ <V _Dinj (3)<ta ₄ <...<ta _L-2 <V _Dinj (L-2) <ta _L-1 <V _Dinj (L-1)<ta _L <V _Dinj (L); because the conduction voltage of the tube Qa _k is 0V (or nearly 0V), the conduction voltage of the tube Qa _k is the conduction voltage of the tube Qa _k When the voltage drop between the source and the drain, the conduction current of the tube _Qak takes a smaller value (such as 30μA), that is, the current of the constant current source I _j takes a smaller value (such as 30μA), record V _Dinj and V _Gwrij are the voltages (instantaneous values) of the input D _inj and output G _wrij of the writing circuit, and the diode conduction voltage V _Don is equal to the step voltage of the K value signal input to V _Dinj , that is, V _Don is equal to the adjacent logic voltages of V _Dinj The flat difference V _Dinj (m)-V _Dinj (m-1), so V _Dinj (m)=mV _Don , the power supply voltage V _dd is more than the input of the writing circuit and the K value of the output of the reading circuit logic level The maximum value is higher by Δ, that is, V _dd =V _Doutj (L)+Δ=V _Dinj (L)+Δ=LV _Don +Δ.

The input-output relationship of the writing circuit is proved as follows: according to the above inequality 0<ta ₁ <V _Dinj (1)<ta ₂ <V _Dinj (2)<ta ₃ <V _Dinj (3)<ta ₄ <...<ta _{L -2} <V _Dinj (L-2)<ta _L-1 <V _Dinj (L-1)<ta _L <V _Dinj (L), it can be seen from Figure 4: ①When D _inj input 0 level, V _Dinj (0)<ta ₁ , all transistors Qa ₁ to Qa _L are cut off, the write circuit output voltage V _Gwrij ＝V _Dinj (0)＝0V, ②When D _inj input 1 level, ta ₁ <V _Dinj (1) <ta ₂ , the tube Qa ₁ is turned on, the tubes Qa ₂ ~Qa _L are off, (L-1) diodes Da ₂ ~Da _L are turned on, V _Gwrij =V _dd -(L-1)V _Don =LV _Don + Δ-(L-1)V _Don ＝V _Don +Δ＝V _Dinj (1)+Δ, ③When D _inj input 2 levels, ta ₂ <V _Dinj (2)<ta ₃ , tubes Qa ₁ and Qa ₂ turn on, the tubes Qa ₃ ~Qa _L are cut off, (L-2) diodes Da ₃ ~Da _L are turned on, V _Gwrij =V _dd -(L-2)V _Don =LV _Don +Δ-(L-2) V _Don ＝2V _Don +Δ＝V _Dinj (2)+Δ, ④When D _inj input 3 levels, ta ₃ <V _Dinj (3)<ta ₄ , tubes Qa ₁ ～Qa ₃ are turned on, tubes Qa ₄ ～ Qa _L is off, (L-3) diodes Da ₄ ~Da _L are on, V _Gwrij =V _dd -(L-3)V _Don =LV _Don +Δ-(L-3)V _Don =3V _Don +Δ ＝V _Dinj (3)+Δ,...⑤ When D _inj input L-2 level, ta _L-2 <V _Dinj (L-2)<ta _L-1 , tubes Qa ₁ ~Qa _L-2 are turned on , tube Qa _L-1 and Qa _L are cut off, two diodes Da _L-1 and Da _L are turned on, V _Gwrij =V _dd -2V _Don =LV _Don +Δ-2V _Don =(L-2)V _Don +Δ =V _Dinj (L-2)+Δ, ⑥When D _inj input L-1 level, ta _L-1 <V _Dinj (L-1)<ta _L , tubes Qa ₁ ~Qa _L-1 are turned on, tubes Qa _L is off, one diode Da _L is on, V _Gwrij ＝V _dd -V _Don ＝LV _Don +Δ-V _Don ＝(L-1)V _Don +Δ＝V _{D inj} (L-1)+Δ, ⑦When D _inj input L level, ta _L <V _Dinj (L), tubes Qa ₁ ~Qa _L conduction, V _Gwrij ＝V _dd ＝LV _Don +Δ＝LV _Don + Δ=V _Dinj (L)+Δ. Therefore, the output G _wrij of the write circuit is Δ higher than the K value signal input by the write circuit except for the 0 level, and the 0 level is still 0, and the output G _wrij is an increased K value signal, which overcomes the problem in the memory cell circuit There is a shortage of DC level offset Δ between the input and output of the voltage follower F. The Pspice computer simulation waveform in the accompanying drawing also confirms its correctness. The diode used is a silicon diode, and the conduction current takes a smaller value, that is, the current of the constant current source I _j takes a smaller value, and Δ is easily calculated or measured by F. In practice, Δ can also take a slightly larger value, and the resulting output G _wrij is an increased signal with a slightly larger Δ, and the increased signal with a slightly larger Δ is passed through F to obtain a non-standard K value signal input by the actual G _rdij , but it does not This is because the readout circuit can convert any non-standard non-equal-level K-value signal G _rdij into _a standardized equal-level K-value signal D _outj . The standard K value signal (corresponding to a slightly larger Δ) can be designed.

Take K=8 in the write-in circuit of any K-value DRAM, then the write-in circuit of 8-value DRAM is obtained, as shown in Figure 2, and the same method proves that the write-in circuit of 8-value DRAM meets the design requirements. Figure 10 is a circuit diagram and symbol diagram of an existing multi-output precision mirror current source (constant current source). In order to reduce power consumption and improve performance, etc., the current of the constant current source I _j takes a smaller value.

Embodiment 3: Proof that the readout circuit of any K value and 8-value DRAM satisfies the design requirements.

The readout circuit of any K-value DRAM is shown in Figure 5, which needs to be proved to meet the design requirements: when the logic value of the input G _rdij of the readout circuit is 0, 1, 2, 3, 4, ..., L-2, L-1 , L, the logic value of the input D _outj of the readout circuit is still sequentially 0, 1, 2, 3, 4, ..., L-2, L-1, L; G _rdij , D _inj and D _outj logic values correspond The logic levels are V _Grdij (n), V _Dinj (n) and V _Doutj (n) (n=0~L), where the input G _rdij is a non-standard K value signal, and the output D _outj is required to be a standard equal ladder K value signal of V _Doutj (0)=V _Dinj (0)=0V, V _Doutj (1)=V _Dinj (1)=V _Don , V _Doutj (2)=V _Dinj (2)=2V _Don , V _Doutj (3)=V _Dinj (3)=3V _Don , ... V _Doutj (L-2)=V _Dinj (L-2)=(L-2)V _Don , V _Doutj (L-1)=V _Dinj (L-1)=(L-1)V _Don , V _Doutj (L)=V _Dinj (L)=LV _Don ; tb _k is the adjacent logic level V of the non-standard K value signal of input G _rdij The intermediate value of _Grdij (k) and V _Grdij (k-1), satisfying V _Grdij (k-1)<tb _k <V _Grdij (k), k=1, 2, 3, 4,..., L-2 _{. _ _ _ _ _ _ _ Grdij} (L-2)<tb _L-1 <V _Grdij (L-1)<tb _L <V _Grdij (L); consider that the turn-on voltage of tube Qb _k is 0V (or nearly 0V), and the turn-on voltage of tube Qb _k It is the voltage drop between the source and the drain when the tube Qb _k is turned on, the conduction current of the tube Qb _k takes a smaller value (such as 30μA), that is, the current of the constant current source I _j takes a smaller value (such as 30μA), Note that V _Grdij and V _Doutj are the voltages (instantaneous values) of the input G _rdij and output D _outj of the readout circuit, and the diode conduction voltage V _Don is equal to the step voltage of the standard K value signal of the output D _outj , that is, V _Don is equal to Output the difference V _Doutj (m)-V _Doutj (m-1) of each adjacent logic level of D _outj , so V _Doutj (m)=mV _Don , power supply voltage V _dc , etc. are written into the input of the circuit and read out the circuit output maximum logic level V _Dinj ( L) and V _Doutj (L), V _dc = V _Doutj (L) = LV _Don .

The input-output relationship of the readout circuit is proved as follows: according to the above inequality 0<tb ₁ <V _Grdij (1)<tb ₂ <V _Grdij (2)<tb ₃ <V _Grdij (3)<tb ₄ <...tb _{L- 2} <V _Grdij (L-2)<tb _L-1 <V _Grdij (L-1)<tb _L <V _Grdij (L), it can be seen from Figure 5: ①When G _rdij input 0 level, V _Grdij ( 0)=0V, V _Grdij (0)<tb ₁ , all tubes Qb ₁ to Qb _L are cut off, and the output voltage V _Doutj of the readout circuit is 0V, ②When G _rdij inputs 1 level, tb ₁ <V _Grdij ( 1)<tb ₂ , tube Qb ₁ is turned on, tubes Qb ₂ ~Qb _L are off, (L-1) diodes Db ₂ ~Db _L are turned on, V _Doutj =V _dc -(L-1)V _Don =LV _Don -(L-1)V _Don ＝V _Don ＝V _Doutj (1), ③When G _rdij input 2 levels, tb ₂ <V _Grdij (2)<tb ₃ , tubes Qb ₁ and Qb ₂ are turned on, tube Qb ₃ ～Qb _L is off, (L-2) diodes Db ₃ ～Db _L are on, V _Doutj =V _dc -(L-2)V _Don ＝LV _Don -(L-2)V _Don ＝2V _Don ＝ V _Doutj (2), ④ When G _rdij is input with 3 levels, tb ₃ <V _Grdij (3)<tb ₄ is satisfied, then tubes Qb ₁ ~ Qb ₃ are turned on, tubes Qb ₄ ~ Qb _L are cut off, there is (L- 3) Diodes Db ₄ ˜Db _L are turned on, V _Doutj =V _dc -(L-3)V _Don =LV _Don +Δ-(L-3)V _Don =3V _Don =V _Doutj (3),... …⑤When G _rdij input L-2 level, tb _L-2 <V _Grdij (L-2)<tb _L-1 , tubes Qb ₁ ~ Qb _L-2 are turned on, and tubes Qb _L-1 and Qb _L are cut off , 2 diodes Db _L-1 and Db _L conduct, V _Doutj ＝V _dc -2V _Don ＝LV _Don -2V _Don ＝(L-2)V _Don ＝V _Doutj (L-2), ⑥When G _rdij input At L-1 level, tb _L-1 <V _Grdij (L-1)<tb _L , tubes Qb ₁ to Qb _L-1 are on, tube Qb _L is off, one diode Db _L is on, V _Doutj =V _dc -V _Don ＝LV _Don -V _Don ＝(L-1)V _Don =V _Doutj (L-1), ⑦When G _rdij inputs L level, tb _L <V _Grdij (L), tubes Qb ₁ ~Qb _L are turned on, V _Doutj ＝V _dc ＝LV _Don ＝V _Doutj (L) . It can be concluded that although the input G _wrij of the readout circuit is a non-standard K-value signal, the output D _outj of the read-out circuit is a standard equal-step K-value signal, that is, the readout circuit converts the non-standard K-value signal G _rdij is the standard equal-step K value signal D _outj . The Pspice computer simulation waveform in the attached figure also proves its correctness, and the continuous waveform (Fig. 18) can be converted into the equal-step K value signal D _outj . The diode used is a silicon diode, and the conduction current takes a smaller value.

Take K=8 in the readout circuit of any K-value DRAM, then the readout circuit of the 8-value DRAM is obtained, as shown in Figure 3, and the same method proves that the readout circuit of the 8-value DRAM meets the design requirements. Figure 10 is a circuit diagram and symbol diagram of an existing multi-output precision mirror current source (constant current source). In order to reduce power consumption and improve performance, etc., the current of the constant current source I _j takes a smaller value.

Embodiment 4: Description of PMOS transistor variable threshold circuit (referred to as variable threshold circuit).

The first PMOS transistor variable threshold circuit (referred to as the first variable threshold circuit) is shown in the left dotted box in Figure 6, which is composed of NMOS transistor _Q3 , PMOS transistor _Q4 and resistor _R3 , and the gate of transistor _Q3 is connected to the input voltage V _x , the gate of tube Q ₄ is connected to the reference voltage V _ref , the drain of tube Q ₃ is the output V _out1 of the circuit, and the output V _out1 is controlled by the PMOS tube Q _T1 ; changing the reference voltage V _ref makes the new threshold of Q _T1 Change (zoom in, zoom out, change turn-on properties and improve turn-on resolution); the tube Q _T1 connected to the PMOS tube variable threshold circuit is called variable threshold PMOS tube. Suppose V _dd ＞V _d ≥V _tn +|V _tp |, V _dd -V _d ≥|V _tp |+V _tn , record V _extn1 ＝V _ref +V _tn +|V _tp |, V _ref is the reference voltage, The threshold voltages of the NMOS and PMOS transistors are V _tn >0 and V _tp <0 respectively. The gate-to-source potential differences of tubes _Q3 and _Q4 are V _gs3 and V _gs4 respectively, because the two sources of _Q3 and _Q4 are connected, and the drain of _Q3 is connected to the power supply V _dd through resistor _R3 , Q The drain of ₄ is grounded, and only when the difference between the two gate voltages of _Q3 and _Q4 V _g3 -V _g4 ≥ _{V tn} + |V _tp |, transistors _Q3 and _Q4 are turned on at the same time, otherwise they are turned off at the same time. Since V _g3 ＝V _x , V _g4 ＝V _ref , it follows that: ①When V _x -V _ref ＝V _g3 -V _g4 ≥V _tn +|V _tp |, that is, the input voltage V _x ≥V _ref +V When _tn +|V _tp |=V _extn1 , tubes _Q3 and _Q4 are turned on, and the voltage V _out1 on resistor _R3 is very low, making Q _T1 turn on; ②When V _x <V _extn1 , _Q3 and Q4 Q ₄ is cut off, V _out1 = V _dd , so that Q _T1 is cut off; it shows that after the variable threshold circuit circuit, Q _T1 is turned on when V _x ≥ V _extn1 , or the new threshold t of the variable threshold PMOS transistor Q _T1 The magnitude becomes V _extn1 , that is, t=V _extn1 , and the reference voltage V _ref is changed to change t and turn-on properties (Q _T1 turns on when V _x ≥ t). Because V _dd ≥ V _ref ≥ 0, the minimum value of t=V _extn1 is V _tn + |V _tp |, the first type of PMOS transistor variable threshold circuit cannot realize the new threshold value of t less than V _tn + |V _tp |, the smaller t needs to be realized with the second PMOS tube variable threshold circuit.

The second PMOS transistor variable threshold circuit (abbreviated as the second variable threshold circuit) is shown in the left dashed box in Figure 7, and its structure is composed of the first PMOS transistor variable threshold circuit (including NMOS transistor _Q3 , PMOS transistor _Q4 and resistor R ₃ ) plus a CMOS inverter (including PMOS transistor Q ₅ and NMOS transistor Q ₆ ), wherein the gate of transistor Q ₄ is connected to the input voltage V _x , the gate of transistor Q 3 is connected to the reference voltage V ref , and the gate of transistor Q ₃ is connected to the reference voltage V _ref , and the gate of transistor Q The drain of ₃ is connected to the input of the CMOS inverter (the gates of the tube _Q5 and the tube _Q6 ), and the output of the CMOS inverter (the drains of the tube _Q5 and the tube _Q6 ) is the output V _out0 of the circuit, and the output V _out0 Receive control PMOS tube Q _T0 ; change the reference voltage V _ref to change the new threshold of Q _T0 (enlarge, shrink, change the opening property and improve the opening resolution); the tube Q _T0 connected to the PMOS tube variable threshold circuit is called variable threshold type PMOS tube. Let V _dd ＞V _d ≥V _tn +|V _tp |, V _dd -V _d ≥|V _tp |+V _tn , record V _extn0 ＝V _ref -V _tn -|V _tp |, NMOS and PMOS tube change threshold The voltages are V _tn >0 and V _tp <0, respectively. The gate-to-source potential differences of transistors _Q3 and _Q4 are V _gs3 and V _gs4 respectively. For the same reasons as above, only when the difference between the two gate voltages of _Q3 and _Q4 is V _g3 -V _g4 ≥V _tn + |V _tp When |, tubes _Q3 and _Q4 are turned on at the same time, otherwise V _g3 -V _g4 <V _tn + |V _tp |, tubes _Q3 and _Q4 are turned off at the same time. Since V _g3 ＝V _ref , V _g4 ＝V _x , it can be concluded that: ① When V _ref -V _x ＝V _g3 -V _g4 <V _tn +|V _tp |, tubes Q ₃ and Q ₄ are cut off, that is, the input When the voltage V _x >V _ref -V _tn -|V _tp |=V _extn0 , the transistors _Q3 and _Q4 are cut off, the drain of the transistor _Q3 (that is, the input of the CMOS inverter) is _Vdd , so the transistor _Q5 is cut off And the tube Q ₆ is turned on, and the CMOS inverter outputs V _out0 =V _d , so that Q _T0 is turned on; ②When V _x ≥ V _extn0 , Q ₃ and Q ₄ are turned on, and the drain of the tube Q ₃ (that is, CMOS Inverter input) is very low, so the tube _Q6 is turned off and the tube _Q5 is turned on, and the CMOS inverter outputs V _out0 =V _dd , so that Q _T0 is turned off. It shows that after the variable threshold circuit, Q _T0 is turned on when V _x ≥ V _extn0 , that is, t=V _extn0 . Where t=V _extn0 =V _ref -V _tn -|V _tp | can be less than V _tn + |V _tp |, indicating that the new threshold t of the variable threshold PMOS transistor Q _T0 becomes V _extn0 , that is, t=V _extn0 . Change the reference voltage V _ref to change t and turn-on properties (Q _T0 turns on when V _x ≥ t). Because V _dd ≥ V _ref ≥ 0, the minimum value of the new threshold t is 0, and the maximum value is V _dd -V _tn - |V _tp |.

Change the reference voltage V _ref to change t, the first PMOS transistor variable threshold circuit Figure 6 (t=V _extn1 =V _ref +V _tn +|V _tp |) cannot achieve a new threshold t smaller than V _tn +|V _tp | , the second PMOS transistor variable threshold circuit in Figure 7 (t=V _extn0 =V _ref -V _tn -|V _tp |) cannot achieve a new threshold t greater than V _dd -V _tn -|V _tp |, and two types of PMOS tube variable threshold circuit is used together. Change V _dd in Figure 6 and Figure 7 to V _dc , then Figure 8 and Figure 9 can be obtained respectively. Figure 8 cannot achieve a new threshold t smaller than V _tn + |V _tp |, and Figure 9 cannot achieve a new threshold t greater than V _dc - The new threshold t of V _tn -|V _tp | is also often used in conjunction with these two PMOS transistor variable threshold circuits. _R3 in Figure 6 and Figure 7 (including Figure 8 and Figure 9) can be replaced by a constant current source _I3 (the current flows to the drain of _Q3 ).

In order to obtain a sequence of different reference voltages V _ref (because the sequence variable threshold PMOS transistors have their own new thresholds ta _k or tb _k , it is necessary to use different reference voltages V _ref to obtain the required new thresholds according to two PMOS transistor variable threshold circuits) It can be realized by connecting a voltage divider circuit with multiple resistors connected in series between the DC power supply and the ground (according to the usual method), or it can be realized by connecting a voltage divider circuit in series with multiple diodes (or field effect diodes) connected in series between the DC power supply and the ground ( Among them, a resistor can be connected in series according to the needs of the situation), and the connection method of the anode and cathode of multiple diodes is the same as that of common batteries in series, such as k diodes D ₁ ~ D _k , the anode of D ₁ is connected to the DC power supply, and the cathode of D ₁ is connected to D ₂ positive pole, D ₂ negative pole connected to D ₃ positive pole, ..., D _k-2 negative pole connected to D _k-1 positive pole, D _k-1 negative pole connected to D _k positive pole, D _k negative pole connected to ground (or grounded through R) to achieve, because The reference voltage V _ref of different sequences is all output to the gate of the MOS transistor, and the output DC current is almost 0, so it is very convenient to implement. The current source I described in the present invention is shown in FIG. 10, which is a commonly used grounded multi-output precision mirror current source.

Embodiment 5: Description of the Pspice computer simulation waveform diagrams 11-16 of FIGS. 1-3.

The write pulse w _ri and the read pulse r _di come from the control circuit of DRAM (considering the word line output W _i of the address decoder, read/write control, chip selection, refresh, etc.), under the action of r _di and w _ri , carry out Pspice computer simulation on Figures 1~3, and get various analog waveforms as shown in Figures 11~16, Note: w _ri , r _di , D _inj , G _wrij , C _mij , F _olij , G _rdij and D The 8 waveforms of _outj are respectively written as V(wri), V(rdi), V(Dinj), V(Gwrij), V(Cmij), V(Folij), V(Grdij) under the abscissa of each figure, The 8 forms of V(Doutj) with V, that is, the brackets behind V are respectively written as w _ri , r _di , D _inj , G _wrij , C _mij , F _olij , G _rdij and D _outj (the subscripts are changed to It is a normal font that is not subscripted, namely wri, rdi, Dinj, Gwrij, Cmij, Folij, Grdij and Doutj, this is the representation of the Pspice simulation diagram), all the following waveforms are written in a similar manner below the abscissa, and no longer Describe them one by one. Fig. 11 is the storage unit circuit of the 8-value DRAM of the present invention, the sequence of D _inj , G _wrij , C _mij , F _olij , G _rdij and D _outj of the write circuit and the read circuit under the sequential action of w _ri and r _di Discrete waveform diagrams, according to the order from top to bottom in Figure 11 are w _ri , r _di , D _inj , G _wrij , C _mij , F _olij , G _rdij and D _outj 8 waveforms, and Figure 12 is in w _ri and r _di , the two waveforms of D _inj and D _outj , the height of w _ri and r _di is reduced by ten times in the figure, and placed at the bottom of the figure (r _di is at the bottom of the figure, w _ri is at the bottom of the figure r _di above), it can be seen from Figure 12 that the input D _inj curve of the DRAM write circuit and the output D _outj curve of the read circuit are multi-valued signals with equal steps, and the logic voltage of D _inj and D _outj of the same logic value Ping is equal to meet the requirements, D _outj is changed when r _di (see the bottom of the figure) comes. Figure 13 shows the two waveforms of the input D _inj and output G _wrij of the 8-value DRAM write circuit under the action of w _ri (see the bottom of the figure). It can be seen from Figure 13 that the input D _inj curve is equal to the ladder Multi-valued signal (relative to the lower curve), the output G _wrij curve is an increased multi-valued signal (relative to the upper non-equal ladder curve), the logic level of the same logic value D _inj and G _wrij (except 0 voltage (except equal) are unequal, thereby overcoming the disadvantage of a downward DC level shift Δ between the input and output of the voltage follower F in the storage unit circuit. Figure 14 is the two waveforms of the input G _rdij and output D _outj of the 8-value DRAM readout circuit under the action of r _di (see the bottom of the figure). It can be seen from Figure 14 that the input G _rdij curve has a smaller step (relatively lower curve, different from the D _inj ladder) multi-valued signal, the logic levels of D _inj and G _rdij of the same logic value are not equal, and the output D _outj curve (relatively higher curve) is the same as The multi-valued signal with the same step in D _inj , that is, the readout circuit converts the non-standard multi-valued signal G _rdij into a multi-valued signal D _outj with a standard equal step, thereby overcoming the voltage of the voltage follower F in the storage unit circuit Insufficient magnification of less than 1. Figure 15 is the two waveforms of the input C _mij and output F _olij of the voltage follower F of the 8-value DRAM storage unit circuit under the action of w _ri (see the bottom of the figure). It can be seen from Figure 15 that the input C _mij The curve is an increased multi-valued signal (relative to the upper curve, non-equal ladder), and the output F _olij curve (relative to the lower curve) has a downward level shift to the input C _mij curve, and the amplitude is reduced, indicating that the memory cell circuit The medium voltage follower F has a downward level shift and a voltage amplification factor less than 1. Fig. 16 is the storage unit circuit of the 8-value DRAM of the present invention, the writing circuit and the reading circuit under the actions of w _ri and r _di (r _di is at the bottom of the figure, and w _ri is on the top of r _di ) sequentially act on D _inj and G The waveform diagrams of _wrij , C _mij , F _olij , G _rdij and D _outj that are not separated up and down are equivalent to the combination of the six curves in Fig. 13, Fig. 14 and Fig. 15.

Example 6: Illustration of the Pspice computer simulated waveforms of Figures 17 and 18.

The main Pspice simulation waveform has been completed in Embodiment 5. Now consider the situation when the write circuit and the readout circuit are respectively input as sine waves, as a reference for further understanding the advantages of the write and readout circuits. Note: This Pspice simulation In order to distinguish from the above-mentioned simulation, the writing circuit input D _inj and the reading circuit output D _outj when inputting a sine wave are respectively replaced with symbols IND _i and OUTD _i (respectively are still in the writing circuit input D _inj and the reading circuit output D _outj two points, that is, the symbols are different, and the input and output points of each representation are the same, and they are still called the input circuit input D _inj and the output circuit output D _outj when explaining), so the input circuit input D _inj and the output circuit in 17 The lower side of the Pspice analog waveform diagram abscissa of the readout circuit output D _outj in Fig. 18 is respectively written as V (INDi) and V (OUTDi), and the lower side of the Pspice analog waveform diagram abscissa of G _wrij and G _rdij is the same as the foregoing and still sequentially Written as V(Gwrij), V(Grdij). Fig. 17 is the oscillogram of the input D _{inj and the output G wrij when} w _ri = 0 transmission gate G ₁ is cut off and the input D _inj is a sine wave in the writing circuit of the 8-value DRAM of the present invention, as seen from Fig. 17 , the sine wave The output G _wrij curve obtained after the wave continuous signal input D _inj curve is written into the circuit is a discontinuous multi-valued signal (but has the effect of increasing), indicating that the write circuit has a good quantization and shaping effect (similar to the rounding of 4 and 5 Quantization function), when the input D _inj voltage rises or falls without crossing the upper and lower thresholds, the output G _wrij can still restore the original multi-valued information, that is, it has the ability to restore the original multi-valued information, and this ability can also be used for refreshing. Fig. 18 is a waveform diagram of the input G rdij and the output D _outj of the readout circuit of the 8-value DRAM of the present invention when r _di = 0 and the transmission gate G ₂ is cut off and the input G _{rdij is a sine wave} . It can be seen from Figure 18 that the output D _outj curve obtained after the sine wave continuous signal input G _rdij curve passes through the readout circuit is a discontinuous (corrected to equal steps) multi-valued signal, indicating that the readout circuit has a good quantization and shaping effect (similar to the quantization effect of rounding to 5), when the input G _rdij voltage rises or falls without crossing the upper and lower thresholds, the output D _outj can still restore the original multi-valued information, that is, it has the ability to restore the original multi-valued information, and this ability is also Available for refresh. In order to improve the anti-jamming performance, increase the ability to restore the original multi-valued information, and reduce the refresh task, the value of the storage capacitor of the storage unit can be appropriately increased. In addition, the input of the readout circuit is also the gate of the MOS transistor, which also has the function of information storage. In order to improve the anti-interference performance, increase the ability to restore the original multi-valued information, and reduce the refresh task, the gate input capacitance is also slightly larger.

Embodiment 7: Description of selecting values of ta _k and tb _k .

It is theoretically proved that the above (1) and (2) only need to satisfy the following inequalities: prove that (1) only needs to satisfy 0<ta ₁ <V _Dinj (1)<ta ₂ <V _Dinj (2)<ta ₃ <V _Dinj (3)＜ta ₄ ＜...＜ta _L-2 ＜V _Dinj (L-2)＜ta _L-1 ＜V _Dinj (L-1)＜ta _L ＜V _Dinj (L), prove (2) It is only required to satisfy 0<tb ₁ <V _Grdij (1)<tb ₂ <V _Grdij (2)<tb ₃ <V _Grdij (3)<tb ₄ <...<tb _L-2 <V _Grdij (L-2) ＜tb _L-1 ＜V _Grdij (L-1)＜tb _L ＜V _Grdij (L); It can be seen from the proof process that theoretically the new threshold can take any value between adjacent logic levels, in fact, one. According to the requirements of anti-interference, it is better to get close to or equal to the average value of adjacent logic levels, the present invention is based on the design of anti-interference requirements; The average value of the allowable discharge charge is more, but taking into account the anti-interference requirements, it can only deviate from the average value appropriately, and cannot deviate greatly from the average value; 3. When the input voltage is equal to the new threshold value, the output is between adjacent logic levels The transition zone, the size of the transition zone depends on the opening resolution of the new threshold (mathematically 'when the input ≥ the new threshold, the tube is turned on', it is only ideal, and actually does not contain =), the opening resolution is better Yes, but not up to the ideal requirements in mathematics.

Embodiment 8: Explanation of using resistor R _j instead of constant current source I _j .

'Constant current source I _j is taken as resistance R _j ', that is, "in the K-value DRAM storage unit circuit described in (4), constant current source I _j is taken as resistance R _j ", referring to the K-value DRAM storage unit circuit In 'Replace constant current source _Ij with resistor _Rj ', that is, one end of resistor _Rj is connected to emitter F _olij , and the other end of resistor _Rj is grounded, so that tube _Qm2 and resistor _Rj form an emitter follower. Because the emitter F _olij is grounded through the constant current source _Ij , that is, one end of the constant current source _Ij is connected to the emitter F _olij , and the other end of the constant current source _Ij is grounded. At this time, the tube Q _m2 and the constant current source _Ij form an emitter follower In other words, it is to change "the emitter F _olij of the tube Q _m2 is grounded through the constant current source I _j " to "the emitter F _olij of the tube Q _m2 is grounded through the resistor R _j ", the former uses the constant current source I _j and Q _m2 The emitter current of Q m2 is constant, and the emitter current of Q _m2 is not constant if the latter uses resistor R _j , but both (connected to I _j and connected to R _j ) are commonly used emitter follower structures. Note: The source of tube Q _m1 is connected to resistor R _m1 (the other end of R _m1 is grounded), which constitutes a source follower (common drain amplifier circuit). Source follower and emitter follower are commonly used circuits. Similar to emitter follower (transistor common collector amplifier circuit), field effect tube source follower (common drain amplifier circuit) has no voltage amplification function, and its voltage The gain is less than 1, the output voltage is in the same phase as the input voltage, the input resistance is high, and the output resistance is low, which can be used for impedance transformation. The input resistance of the source follower is extremely high, suitable for connecting to the storage capacitor C _j (small drain electrode), the input resistance of the emitter follower is low, not suitable for connecting to the storage capacitor C _j (large leakage), but the output of the source follower The resistance is higher than the output resistance of the emitter follower, and the load capacity is relatively poor. To increase the load capacity, the output of the source follower can be connected to the input of the emitter follower, and the output of the emitter can be used as the output of the voltage follower. The output load capacity is greatly enhanced.

Claims (4)

1. a write circuit of arbitrary K value DRAM is characterized in that: in the write circuit of described K value DRAM, establish K=3,4,5,...; Adopt K-1=L variable threshold Type PMOS transistor Qa _k , k=1, 2, 3,..., L, the gate of transistor Qak _k is connected to the input D _inj of the writing circuit through the variable threshold circuit, and the new threshold value of the variable threshold type PMOS transistor _Qak is ta _k , when the tube _Qak is turned on, the voltage drop between the source and the drain is 0; the source of the tube _Qak is connected to the power supply V _dd , and the voltage of V _dd is selected to be higher than the maximum logic level of the write circuit input and the read circuit output V _Dinj (L) and V _Douj (L) are high Δ, Δ is the downward DC level offset between the input and output of the voltage follower F; L-1 diodes Da _n are used, n=2, 3,..., L , the turn-on voltage of the diode _Dan is V _Don ; the anode and cathode of _Dan are respectively connected to the drain of the threshold-variable PMOS transistor Qa _n-1 and the drain of the transistor Qa _n ; the drain of the transistor Qa _L is subjected to constant current The source I _j is grounded, the drain of the tube Qa _L is connected to the constant current source I _j so that the current flowing through the conduction diode remains at the same fixed value, and the output G _wrij of the writing circuit is formed on the drain of the tube Qa _L , and the writing circuit outputs _{G wrij} is connected to the write bit line _input of the memory cell circuit; choosing ta _{k is} the average value ( V _Dinj (k)+V _Dinj (k-1))/2, that is, ta _k is the intermediate value of V _Dinj (k) and V _Dinj (k-1), V _Dinj (k)＞V _Dinj (k-1 ); the characteristics of the K value signal of the K value signal of the input circuit D _inj and the standard K value signal of the read circuit output D _outj and DRAM input and output are the same: the difference of each adjacent logic level of the input D _inj is equal , the difference between adjacent logic levels of the output D _outj is equal, and the step voltages of the input D _inj and the output D _outj are the same, and the step voltage is V _Don , that is, V _Dinj (m)-V _Dinj (m-1)= V _Doutj (m)-V _Doutj (m-1)=V _Don , m=1, 2, 3,..., L, V _Dinj (m) and V _Doutj (m) are the input and readout of the write circuit respectively The output logic value of the circuit is a logic level of m; the output G _wrij of the write circuit is higher than the K value signal input by the write circuit by Δ except for the 0 level, and the 0 level is still 0. The K value write circuit is also called Write the boost circuit for the K value. 2. A readout circuit of any K-value DRAM formed according to the same structural feature of the write-in circuit of any K-value DRAM according to claim 1, is characterized in that: in the readout circuit of described K-value DRAM , assuming K=3, 4, 5, ...; K-1 = L variable-threshold PMOS transistors Qb _k , k = 1, 2, 3, ..., L, the gate of the transistor Qb _k is variable threshold The circuit is connected to the input G _rdij of the readout circuit, the new threshold value of the variable threshold PMOS transistor Qb _k is tb _k , and the voltage drop between the source and the drain is 0 when the transistor Qb _k is turned on; G _rdij is connected to the readout of the memory cell circuit Bit line output, the source of the tube Qb _k is connected to the power supply V _dc , and the voltage of V _dc is selected to be equal to the maximum logic level V _Dinj (L) and V _Douj (L) of the write circuit input and read circuit output; adopt L- 1 diode Db _n , n=2, 3, ..., L, the turn-on voltage of diode Db _n is V _Don ; the anode and cathode of Db _n are respectively connected to the drain and the drain of threshold-variable PMOS transistor Qb _n-1 The drain of Qb _n ; the drain of variable-threshold PMOS transistor Qb _L is grounded through constant current source I _j , and the drain of tube Qb _L is connected to constant current source I _j so that the current flowing through the conduction diode remains at the same fixed value. The drain of the tube Qb _L forms the output D _outj of the readout circuit; select tb _k as the average of the adjacent logic levels V _Grdij (k) and V _Grdij (k-1) of the K-value signal input to the readout circuit _Grdij Value (V _Grdij (k)+V _Grdij (k-1))/2, that is, tb _k is the intermediate value of V _Grdij (k) and V _Grdij (k-1), V _Grdij (k)＞V _Grdij (k -1); The characteristics of the signal of the readout circuit output D _outj and the K value signal of the standard equal ladder of the write circuit input D _inj and DRAM input and output are the same: the difference of each adjacent logic level of the input D _inj is equal , the difference between adjacent logic levels of the output D _outj is equal, and the step voltages of the input D _inj and the output D _outj are the same, and the step voltage is V _Don , that is, V _Dinj (m)-V _Dinj (m-1)= V _Doutj (m)-V _Doutj (m-1)=V _Don , m=1, 2, 3,..., L, V _Dinj (m) and V _Doutj (m) are the input and readout of the write circuit respectively The circuit output logic value is the logic level of m; the readout circuit input G _rdij is the non-standard K value signal from the storage unit circuit output, and the non-standard K value signal is exactly to compare the DRAM input and output with the write circuit input and The standard equal-step K value signal output by the readout circuit is inconsistent with the logic level and amplitude; the output D _outj of the readout circuit is a standardized equal-step K value signal, that is, the readout circuit inputs the non-standard K value signal into G _{r dij} is converted into a standard equal-step K value signal output D _outj , and the K value readout circuit is also called a K value readout correction circuit. 3. the write-in circuit of a kind of arbitrary K value DRAM according to claim 1, is characterized in that: get K=8, draws the write-in circuit of 8-value DRAM, wherein adopts 7 variable-threshold type PMOS transistors _Qak , k=1, 2, 3,..., 7, the gate of the tube Qak _k is connected to the input D _inj of the writing circuit through the variable threshold circuit, the new threshold value of the variable threshold PMOS transistor Qa _k is ta _k , and the tube Qa k When _k is turned on, the voltage drop between the source and the drain is 0; the source of the tube Qa _k is connected to the power supply V _dd , and the voltage of V _dd is selected to be higher than the maximum logic level V _Dinj of the write circuit input and the read circuit output (7) and V _Douj (7) high Δ, Δ is the downward DC level offset between the input and output of the voltage follower F; using 6 diodes _Dan , n=2, 3,..., 7, the conduction of the diode _Dan The on-voltage is V _Don ; the positive pole and the negative pole of Da _n are respectively connected to the drain of the variable-threshold PMOS transistor Qa _n-1 and the drain of the pipe Qa _n ; the drain of the pipe Qa ₇ is grounded through the constant current source _Ij , and the pipe The drain of Qa ₇ is connected to the constant current source _Ij to keep the current flowing through the conduction diode at the same fixed value, and the output G _wrij of the writing circuit is formed at the drain of Qa ₇ , and the output G _wrij of the writing circuit is connected to the storage unit _{The write bit line input of the circuit; select ta k as the average value (V Dinj ( k ) +} V _Dinj (k-1))/2, that is, select ta _k as the intermediate value of V _Dinj (k) and V _Dinj (k-1), V _Dinj (k)>V _Dinj (k-1); write into the circuit The characteristics of the 8-value signal input D _inj and the output D _outj of the readout circuit and the 8-value signal of the standard equal ladder of the DRAM input and output are the same: the difference of each adjacent logic level of the input D _inj is equal, and the output D _outj each The difference between adjacent logic levels is equal, and the step voltages of input D _inj and output D _outj are the same, and the step voltage is V _Don , that is, V _Dinj (m)-V _Dinj (m-1)=V _Doutj (m) -V _Doutj (m-1)=V _Don , m=1, 2, 3,..., 7, V _Dinj (m) and V _Doutj (m) are respectively the logic values of the input of the write circuit and the output of the read circuit The logic level of m; the write circuit output G _wrij is Δ higher than the 8-value signal input by the write circuit except for the 0 level, and the 0 level is still 0. The 8-value write circuit is also called 8-value write increase circuit. 4. a kind of readout circuit of the arbitrary K value DRAM that a kind of according to the same structural feature of the write circuit of arbitrary K value DRAM described in claim 1 forms according to claim 2, is characterized in that: get K=8 , to obtain the readout circuit of 8-value DRAM, wherein seven variable-threshold PMOS transistors Qb _k are used, k=1, 2, 3, ..., 7, and the gate of the transistor Qb _k is connected to the readout circuit through the variable-threshold circuit The input G _rdij of the circuit, the new threshold value of the threshold-variable PMOS transistor Qb _k is tb _k ; when the transistor Qb _k is turned on, the voltage drop between the source and the drain is 0; G _rdij is connected to the output of the read bit line of the memory cell circuit, and the transistor The source of Qb _k is connected to the power supply V _dc , and the voltage of V _dc is selected to be equal to the maximum logic level V _Dinj (7) and V _Douj (7) of the write circuit input and read circuit output; use 6 diodes Db _n , n =2, 3, ..., 7, the conduction voltage of the diode Db _n is V _Don ; the positive pole and the negative pole of Db _n are respectively connected to the drain of the variable threshold PMOS transistor Qb _n-1 and the drain of the tube Qb _n ; The drain of the threshold-type PMOS transistor Qb ₇ is connected to the ground through the constant current source _Ij , and the drain of the transistor Qb ₇ is connected to the constant current source _Ij so that the current flowing through the conduction diode remains at the same fixed value, and the drain of the transistor Qb ₇ forms The output D _outj of readout circuit _; Choose tb _k to _{be the average value (V Grdij ( k} ) +V _Grdij (k-1))/2, that is, select tb _k as the intermediate value of V _Grdij (k) and V _Grdij (k-1), V _Grdij (k)>V _Grdij (k-1); read out The characteristics of the signal of the circuit output D _outj and the 8-valued signal written into the circuit input D _inj and DRAM input and output specifications are the same: the difference of each adjacent logic level of the input D _inj is equal, and the output D _outj of each phase The difference between adjacent logic levels is equal, and the step voltage of the input D _inj and the output D _outj are the same, and the step voltage is V _Don , which satisfies V _Dinj (m)-V _Dinj (m-1)=V _Doutj (m)-V _Doutj (m-1)=V _Don , m=1, 2, 3,..., 7, V _Dinj (m) and V _Doutj (m) are respectively the logic values of the input circuit input and the output logic value of the readout circuit m Logical level; the readout circuit input G _rdij is an irregular 8-value signal from the memory unit circuit output, and the irregular 8-value signal is exactly compared to the standard of the DRAM input and output, the write circuit input and the readout circuit output The 8-valued signal of the equal ladder is inconsistent with the logic level amplitude; the output D _outj of the readout circuit is a standardized 8-valued signal of the equal ladder, that is, the readout circuit converts the non-standard 8-valued signal G _rdij to If it is replaced with a standard equal-level 8-value signal D _outj , the 8-value readout circuit is also called an 8-value readout correction circuit.

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