CN103345936A - Write-in circuits and read-out circuits of arbitrary-K-value DRAM and eight-value DRAM - Google Patents

Abstract

The invention relates to write-in circuits and read-out circuits of an arbitrary-K-value DRAM and an eight-value DRAM. The write-in circuits and the read-out circuits have same structure characteristics, and the write-in circuits are each designed to provide a multi-value signal increased by delta than write-in circuit input; an output waveform of a memory cell is considered to be smaller than an input waveform or be of an unequal step shape, the read-out circuits are each designed for correction, and an irregular multi-value signal is converted into a regular (equal step) multi-value signal. The write-in circuits and the read-out circuits both have good quantified shaping effects; when a change of a Cj voltage is not greater than an upper new threshold or a lower new threshold, original multi-value information can be easily recovered, so the write-in circuits and the read-out circuits have anti-jamming capability and multi-value information recovery capability. The write-in circuits and the read-out circuits are mainly applied to the fields of VLSI and other digital IC technologies, such as an FPGA, a CPLD, a semi-custom or a full-custom ASIC, a memorizer and the like.

Description

K value and 8 is worth write circuit and the sensing circuit of DRAM arbitrarily

Technical field

The present invention be directed to application number: 201110097206.7 divide an application belongs to the digital integrated circuit field, specifically write circuit and the sensing circuit of a kind of any K value and 8 value DRAM.

Background technology

Along with the develop rapidly of MOS integrated circuit technique, integrated scale is increasing, and integrated level is more and more higher, and some shortcomings appear in VLSI (VLSI (very large scale integrated circuit)): 1. at first on the VLSI substrate, wiring but takies the silicon area more than 70%; In programmable logic device (PLD) (as FPGA and CPLD), also need there be a large amount of interconnectors able to programme (to comprise the switch that is connected able to programme, as fuse-type switch, anti-fuse-type switch, floating boom programmed element etc.), each logic function block or I/O are coupled together, finish the circuit of specific function, wiring (comprising that programming connects switch) has accounted for the very big cost of material.The proportion that reduces wiring cost becomes important problems.2. from information transmission aspect, adopt multi-valued signal can reduce the line number; To every line transmitting digital information, binary signal is to carry minimum a kind of of quantity of information, and multi-valued signal carries and contains much information in binary signal.3. from information storage aspect, adopt multi-valued signal can improve information storage density, particularly utilize metal-oxide-semiconductor grid capacitance storage information (being used for dynamic RAM DRAM), because same capacitance stores quantity of information is many-valued bigger than two-value, many-valued DRAM can improve information storage density greatly than two-value DRAM.The development of present many-valued device is extensively carried out, and Toshiba matches by the CMOS technology of 70nm and the many-valued technology of 2bit/ unit with Sandisk company, at 146mm ²Chip on realized the memory capacity of 8Gbit; Toshiba and U.S. SanDisk have delivered the 16gbitNAND flash memory by adopting the many-valued technology in 43nm technology and 2bit/ unit to realize.The 8Gbit product of Samsung exploitation adopts the CMOS technology of 63nm and the many-valued technology of 2bit/ unit.Succeed in developing and the commercialization of 4 value storeies is important steps of many-valued research, but needs the switching threshold V of control or change pipe _Tn, changing threshold method is to use multistage ion implantation technique in semiconductor fabrication process, or controls methods such as the amount of electrons control threshold value of the grid storage of swimming.Still find no succeeding in developing more than the DRAM of 4 values.

Semiconductor memory can be divided into read only memory ROM and random access memory ram.And RAM is divided into ambipolar and MOS type two classes.Bipolar RAM operating rate height, but the manufacturing process complexity, power consumption is big, integrated level is low, is mainly used in the occasion of high speed operation.MOS type RAM is divided into two kinds of static RAM SRAM and dynamic RAM DRAM (Dynamic Random Access Memory) again.The principle of DRAM storage information is based on the charge-storage effect of metal-oxide-semiconductor grid capacitance.Since the capacity very little (only being several pico farads usually) of grid memory capacitance, and leakage current can not definitely equal zero, so the limited time that electric charge is preserved; In order in time to replenish the dropout of electric charge to avoid storing of missing, must replenish electric charge regularly for the grid memory capacitance, usually this operation is called and refreshes or regenerate, must be aided with the refresh control circuit of necessity during DRAM work.DRAM is by big rectangle memory cell array and the supportive logical circuit that is used for to the array read and write, and the compositions such as refresh circuit of keeping integrity of data stored.The simplest available single tube dynamic storage cell in DRAM.Storage unit is to line up matrix type structure by row, column, deciphers respectively with two decoding schemes.X-direction decoding is called row decoding, and its output line is called the word line, and it chooses all storage unit of delegation in the storage matrix.Y-direction decoding is called column decoding again, and its output line is called bit line., reads the single tube dynamic storage cell capacitor C of memory capacitance on the bit line because reading as destructiveness at every turn _BElectric charge is provided, the memory capacitance electric charge is reduced, need to recover immediately, be connected to sensitivity recovery/sensor amplifier at every bit line, used after sensitivity recovery/sensor amplifier, in each sense data, finished the recovery to the original institute of storage unit deposit data.(namely a word has the n position generally DRAM to be designed to word length n position, as 4,8 or N position), address decoder is translated each word line to be exported when effective, there be n (as 4,8 or N) storage unit is simultaneously selected, makes these selected storage unit carry out read-write operation through the read/write control circuit, the input and output of DRAM read-write control circuit control data message.The control signal of outer bound pair storer has read signal R _D, write signal W _RWith chip selection signal C _SEtc..The figure place of the inputoutput data of DRAM has 1, and 2,4 or N position.Except the multidigit input and output, reduce the number of device pin when improving integrated level, the mode that big capacity DRAM usually adopts 1 input, 1 output and address timesharing to import has input buffer, output buffer and output latch etc. accordingly.

Prior art and existing problems:

1. to the multi-valued signal in the memory capacitance that is stored in DRAM, sense data is that difficult (two-value data is by the having and do not have and decide of the electric charge of memory capacitance, and is easy to read; Multi-valued signal is read and will be distinguished magnitude, and decay and distortion may appear in multi-valued signal in transmission, conventional amplifier forms serious distortion easily to multi-valued signal, can not get the input and output such as multi-valued signal such as ladder such as grade of DRAM standard, conventional sensor amplifier method can not be read multi-valued signal, can not realize the storage unit circuit of any K value and 8 value DRAM, still find no succeeding in developing more than the DRAM of 4 values.For overcoming this difficulty, can not must consider the many-valued write circuit and the many-valued sensing circuit that match with many-valued storage unit simultaneously by the many-valued storage unit of the simple consideration of classic method.To 4 of word lengths, 8 or N bit data, then corresponding write circuit and sensing circuit have 4,8 or N.Write circuit and sensing circuit with the standard that requires to obtain DRAM etc. the many-valued input/output signal of ladder be prerequisite, many-valued DRAM storage unit circuit, write circuit and sensing circuit should design this three kinds of circuit by a total inventive concept, these three kinds of circuit are closely related, but three kinds of circuit quantities have nothing in common with each other (integral body that can not form a kind of circuit) when practical, can overcome by a total inventive concept design and read the difficulty that is stored in electric capacity multi-valued signal data.

2. in realizing multivalued circuit, prior art control metal-oxide-semiconductor threshold value has very big shortcoming: 1. control the amplitude limited (because ion implantation concentration is limited) of threshold value, unlatching resolution is low; And control the performance that threshold amplitude regular meeting changes metal-oxide-semiconductor in the technology, and for example the sharp increase that causes cutting off electric current is returned in the reduction of threshold voltage, and the adjustment of threshold voltage is to performance and influential, the stable V of stability of pipe _TnExtremely important.To many-valued memory, the amount of electrons of injecting the grid that swims is continually varying, needs the control of very fine ground, and each threshold voltage level does not still reach quasi-stationary state.Therefore the voltage-type multivalued circuit of practicality is not more than 4 value circuit at present, and more multivalued circuit is used difficulty.2. can only control the amplitude of threshold value, can not change metal-oxide-semiconductor and open character (being＜t conducting as change 〉=t conducting), and multivalued gate must have two kinds of metal-oxide-semiconductors of opening character, just can make the combinational circuit structure the simplest, for example many-valued not gate, many-valued door and the circuit structure of many-valued follower of moving to right should be identical, threshold voltage and open different in kind just.Yet only control the technology of threshold amplitude at present, make above-mentioned multivalued gate structural difference very big, complex structure influences its realization.3. need to increase ion and inject extra operation, can only in semiconductor fabrication process, control threshold value, both increased process complexity, can not control threshold value by the user in the back again, or non-programmable to threshold users.

K value DRAM (K＞2) custom is commonly referred to as many-valued DRAM, but at the design stores element circuit, write with sensing circuit in, circuit structure is normal relevant with K, at this moment it is comparatively convenient to write K value (address K value DRAM etc.) exactly, and some content introductions, unstructuredness are described or often can continue to use custom with the irrelevant noun of K value and call (as multi-valued signal, multivalued gate).

Summary of the invention

The present invention seeks to disclose write circuit and the sensing circuit of a kind of any K value and 8 value DRAM.

Above-mentioned purpose realizes by following technical scheme:

1. the write circuit of a kind of any K value DRAM of the present invention is achieved in that this write circuit as shown in Figure 4, in the write circuit of described K value DRAM, establishes K=3,4,5, Adopt K-1=L variable threshold type PMOS pipe Qa _k, k=1,2,3 ..., L, pipe Qa _kGrid be connected to the input D of write circuit through the variable threshold circuit _Inj, variable threshold type PMOS manages Qa _kNew threshold value be ta _k, pipe Qa _kDuring conducting between source drain pressure drop be 0; Pipe Qa _kSource electrode meet power supply V _Dd, choose V _DdVoltage ratio write circuit input and the largest logical level V that exports of sensing circuit _Dinj(L) and V _Douj(L) high Δ, Δ are DC level skews downward between voltage follower F input and output; Adopt L-1 diode Da _n, n=2,3 ..., L, diode Da _nForward voltage be V _DonDa _nPositive pole and negative pole be connected respectively to variable threshold type PMOS pipe Qa _N-1Drain electrode and the pipe Qa _nDrain electrode; Pipe Qa _LDrain electrode through constant current source I _jGround connection, pipe Qa _LDrain electrode meet constant current source I _jMake the electric current of the conducting diode of flowing through keep same fixed value, at pipe Qa _LDrain electrode form the output G of write circuit _Wrij, write circuit output G _WrijReceive the write bit line input of storage unit circuit; Choose ta _kBe write circuit input D _InjThe adjacent logic levels V of K value signal _Dinj(k) and V _Dinj(k-1) mean value (V _Dinj(k)+V _Dinj(k-1))/2, i.e. ta _kBe V _Dinj(k) and V _Dinj(k-1) intermediate value, V _Dinj(k)＞V _Dinj(k-1); Write circuit input D _InjK value signal and sensing circuit output D _OutjAnd the characteristic of the K value signal that waits ladder of the standard of DRAM input and output is identical: input D _InjThe difference of each adjacent logic levels equates, output D _OutjThe difference of each adjacent logic levels equates, and input D _InjWith output D _OutThe stepped-up voltage of j is identical, and stepped-up voltage is V _Don, also namely satisfy V _Dinj(m)-V _Dinj(m-1)=V _Doutj(m)-V _Doutj(m-1)=V _Don, m=1,2,3 ..., L, V _Dinj(m) and V _Doutj(m) be respectively that write circuit input and sensing circuit output logic value are the logic level of m; The output G of write circuit _WrijThan the high Δ of K value signal of write circuit input, 0 level still is 0 except 0 level, and this K value write circuit is called the K value again and writes attack circuit.

2. the sensing circuit of a kind of any K value DRAM of the present invention is achieved in that sensing circuit as shown in Figure 5, the sensing circuit of this any K value DRAM forms according to the same structure feature of the write circuit of above-mentioned 1 described any K value DRAM, in the sensing circuit of described K value DRAM, if K=3,4,5, Adopt K-1=L variable threshold type PMOS pipe Qb _k, k=1,2,3 ..., L, pipe Qb _kGrid be connected to the input G of sensing circuit through the variable threshold circuit _Rdij, variable threshold type PMOS manages Qb _kNew threshold value be tb _k, pipe Qb _kDuring conducting between source drain pressure drop be 0; G _RdijReceive the sense bit line output of storage unit circuit, pipe Qb _kSource electrode meet power supply V _Dc, choose V _DcVoltage equal the largest logical level V that write circuit input and sensing circuit are exported _Dinj(L) and V _Douj(L) (be V _Dc=V _Dinj(L)=V _Douj(L)); Adopt L-1 diode Db _n, n=2,3 ..., L, diode Db _nForward voltage be V _DonDb _nPositive pole and negative pole be connected variable threshold type PMOS pipe Qb respectively _N-1Drain electrode and the pipe Qb _nDrain electrode; Variable threshold type PMOS manages Qb _LDrain electrode through constant current source I _jGround connection, pipe Qb _LDrain electrode meet constant current source I _jMake the electric current of the conducting diode of flowing through keep same fixed value, at pipe Qb _LDrain electrode form the output D of sensing circuit _OutjChoose tb _kBe sensing circuit input G _RdijThe adjacent logic levels V of K value signal _Grdij(k) and V _Grdij(k-1) mean value (V _Grdij(k)+V _Grdij(k-1))/2, i.e. tb _kBe V _Grdij(k) and V _Grdij(k-1) intermediate value, V _Grdij(k)＞V _Grdij(k-1); Sensing circuit output D _OutjSignal and write circuit input D _InjAnd the characteristic of the K value signal that waits ladder of the standard of DRAM input and output is identical: input D _InjThe difference of each adjacent logic levels equates, output D _OutjThe difference of each adjacent logic levels equates, and input D _InjWith output D _OutjStepped-up voltage identical, stepped-up voltage is V _Don, also namely satisfy V _Dinj(m)-V _Dinj(m-1)=V _Doutj(m)-V _Doutj(m-1)=V _Don, m=1,2,3 ..., L, V _Dinj(m) and V _Doutj(m) be respectively that write circuit input and sensing circuit output logic value are the logic level of m; Sensing circuit input G _RdijBe the nonstandard K value signal from storage unit circuit output, described nonstandard K value signal be exactly contrast DRAM input and output and write circuit input and sensing circuit output standard etc. the K value signal of ladder be that the logic level amplitude is inconsistent; Sensing circuit output D _OutjBe the K value signal that waits ladder of standard, namely sensing circuit is with nonstandard K value signal input G _RdijBe converted to the K value signal output D that waits ladder of standard _Outj, this K value sensing circuit is called the K value again and reads correcting circuit.

Annotate: the storage unit circuit of a kind of any K value DRAM of the present invention is achieved in that as shown in Figure 1 the storage unit circuit of described K value DRAM is by voltage follower F, the grid memory capacitance C of F _jWith two cmos transmission gate G ₁And G ₂Form, use capacitor C _jStorage K value signal, voltage follower F comprise NMOS pipe Q _M1With NPN pipe Q _M2, pipe Q _M1Grid connect capacitor C _jAn end C _Mij, i.e. C _MijBe the input of voltage follower F, C _jOther end ground connection, the pipe Q _M1Source electrode take over Q _M2Grid and resistance R _M1, R _M1Other end ground connection, the pipe Q _M2Emitter-base bandgap grading F _OlijThrough constant current source I _jGround connection, Q _M2Emitter-base bandgap grading meets constant current source I _jMake pipe Q _M2The emitter-base bandgap grading load be constant current source, the pipe Q _M2Emitter-base bandgap grading F _OlijBe the output of F, pipe Q _M1Drain electrode and the pipe Q _M2Collector all meet power supply V _Dd, choose V _DdVoltage ratio write circuit input and the high Δ of maximal value of the K value logic level of sensing circuit output, Δ is that DC level downward between voltage follower F input and output is offset; Transmission gate G ₁Input meet write bit line G _Wrij, transmission gate G ₁Output meet the input C of F _Mij, transmission gate G ₁Control input connect and write pulse w _Ri, transmission gate G ₂Input meet the output F of F _Olij, transmission gate G ₂Output meet sense bit line G _Rdij, transmission gate G ₂Control input meet read pulse r _Di, write pulse w _RiWith read pulse r _DiControl circuit from DRAM; Write pulse w _RiCome then transmission gate G ₁Conducting is with write bit line G _WrijThe K value signal be sent to memory capacitance C _j, capacitor C _jReceive write bit line G _WrijThe K value signal, capacitor C _jThe K value signal be exactly F input C _MijThe K value signal; Write pulse w _RiFuture then, transmission gate G ₁End memory capacitance C _jWith the external world be direct current open circuit, capacitor C _jThe K value signal of storage remains unchanged, and namely has memory function; Read pulse r _DiCome then transmission gate G ₂Conducting is exported F with F _OlijThe K value signal be sent to sense bit line G _RdijWrite bit line G _WrijWith sense bit line G _RdijEach input and output of storage unit circuit naturally; Write circuit output and sensing circuit input are received in the storage unit circuit input and output separately; The K value signal of F output must be the K value signal corresponding with the F input signal, and the F input/output information is identical, i.e. the no information dropout of F output, and the no information dropout of F output requires C _jThe K value signal of storage is the K value signal that increases, and the described K value signal that increases is exactly the signal of the high Δ of K value signal imported than write circuit except 0 level, and wherein 0 level still is 0; C _jThe K value signal that increases of storage is the output from write circuit, namely offers C _jThe write circuit output of storage signal also is the K value signal that increases; C _jThe K value signal that increases of storage is sent to sense bit line G through F _Rdij, at G _RdijThe nonstandard K value signal of last formation, also be that storage unit circuit output is nonstandard K value signal, described nonstandard K value signal be exactly contrast DRAM input and output and write circuit input and sensing circuit output standard etc. the K value signal of ladder be that the logic level amplitude is inconsistent; The sensing circuit input signal is from storage unit circuit output G _RdijNonstandard K value signal, sensing circuit output is that storage unit circuit is exported the K value signal that waits ladder that nonstandard K value signal is proofreaied and correct the standard that draws, and the K value signal that waits ladder of the standard that this correction draws is as the correction of storage unit circuit storage information is read.

In described K value DRAM storage unit circuit, constant current source I _jCan be by resistance R _jReplace.

The present invention also has following technical characterictic:

(1) according to the write circuit of above-mentioned 1 described a kind of any K value DRAM, gets K=8, draw the write circuit of 8 value DRAM, as shown in Figure 2, wherein adopt 7 variable threshold type PMOS pipe Qa _k, k=1,2,3 ..., 7, pipe Qa _kGrid be connected to the input D of write circuit through the variable threshold circuit _Inj, variable threshold type PMOS manages Qa _kNew threshold value be ta _k, pipe Qa _kDuring conducting between source drain pressure drop be 0; Pipe Qa _kSource electrode meet power supply V _Dd, choose V _DdVoltage ratio write circuit input and the largest logical level V that exports of sensing circuit _Dinj(7) and V _Douj(7) high Δ, Δ are DC level skews downward between the input and output of voltage follower F; Adopt 6 diode Da _n, n=2,3 ..., 7, diode Da _nForward voltage be V _DonDa _nPositive pole and negative pole be connected respectively to variable threshold type PMOS pipe Qa _N-1Drain electrode and the pipe Qa _nDrain electrode; Pipe Qa ₇Drain electrode through constant current source I _jGround connection, pipe Qa ₇Drain electrode meet constant current source I _jMake the electric current of the conducting diode of flowing through keep same fixed value, at pipe Qa ₇Drain electrode form the output G of write circuit _Wrij, write circuit output G _WrijReceive the write bit line input of storage unit circuit; Choose ta _kBe write circuit input D _InjThe adjacent logic levels V of 8 value signals _Dinj(k) and V _Dinj(k-1) mean value (V _Dinj(k)+V _Dinj(k-1))/2, namely choose ta _kBe V _Dinj(k) and V _Dinj(k-1) intermediate value, V _Dinj(k)＞V _Dinj(k-1); Write circuit input D _Inj8 value signals and sensing circuit output D _OutjAnd the characteristic of 8 value signals that wait ladder of the standard of DRAM input and output is identical: input D _InjThe difference of each adjacent logic levels equates, output D _OutjThe difference of each adjacent logic levels equates, and input D _InjWith output D _OutjStepped-up voltage identical, stepped-up voltage is V _Don, also namely satisfy V _Dinj(m)-V _Dinj(m-1)=V _Doutj(m)-V _Doutj(m-1)=V _Don, m=1,2,3 ..., 7, V _Dinj(m) and V _Doutj(m) be respectively that write circuit input and sensing circuit output logic value are the logic level of m; Write circuit output G _WrijThan the high Δ of 8 value signals of write circuit input, 0 level still is 0 except 0 level, and this 8 value write circuit is called 8 values again and writes attack circuit.

(2) get K=8 in the sensing circuit according to above-mentioned 2 described any K value DRAM, draw the sensing circuit of 8 value DRAM, as shown in Figure 3, the sensing circuit of this 8 value DRAM forms according to the same structure feature of the write circuit of above-mentioned (1) described 8 value DRAM, wherein adopts 7 variable threshold type PMOS pipe Qb _k, k=1,2,3 ..., 7, pipe Qb _kGrid be connected to the input G of sensing circuit through the variable threshold circuit _Rdij, variable threshold type PMOS manages Qb _kNew threshold value be tb _kPipe Qb _kDuring conducting between source drain pressure drop be 0; G _RdijReceive the sense bit line output of storage unit circuit, pipe Qb _kSource electrode meet power supply V _Dc, choose V _DcVoltage equal the largest logical level V that write circuit input and sensing circuit are exported _Dinj(7) and V _Douj(7); Adopt 6 diode Db _n, n=2,3 ..., 7, diode Db _nForward voltage be V _DonDb _nPositive pole and negative pole be connected variable threshold type PMOS pipe Qb respectively _N-1Drain electrode and the pipe Qb _nDrain electrode; Variable threshold type PMOS manages Qb ₇Drain electrode through constant current source I _jGround connection, pipe Qb ₇Drain electrode meet constant current source I _jMake the electric current of the conducting diode of flowing through keep same fixed value, at pipe Qb ₇Drain electrode form the output D of sensing circuit _OutjChoose tb _kBe sensing circuit input G _RdijThe adjacent logic levels V of 8 value signals _Grdij(k) and V _Grdij(k-1) mean value (V _Grdij(k)+V _Grdij(k-1))/2, namely choose tb _kBe V _Grdij(k) and V _Grdij(k-1) intermediate value, V _Grdij(k)＞V _Grdij(k-1); Sensing circuit output D _OutjSignal and write circuit input D _InjAnd the characteristic of 8 value signals that wait ladder of the standard of DRAM input and output is identical: input D _InjThe difference of each adjacent logic levels equates, output D _OutjThe difference of each adjacent logic levels equates, and input D _InjWith output D _OutjStepped-up voltage identical, stepped-up voltage is V _Don, namely satisfy V _Dinj(m)-V _Dinj(m-1)=V _Doutj(m)-V _Doutj(m-1)=V _Don, m=1,2,3 ..., 7, V _Dinj(m) and V _Doutj(m) be respectively that write circuit input and sensing circuit output logic value are the logic level of m; Sensing circuit input G _RdijBe nonstandard 8 value signals from storage unit circuit output, described nonstandard 8 value signals be exactly contrast DRAM input and output and write circuit input and sensing circuit output standard etc. 8 value signals of ladder be that the logic level amplitude is inconsistent; Sensing circuit output D _OutjBe 8 value signals that wait ladder of standard, namely sensing circuit is with nonstandard 8 value signal G _RdijBe converted to the 8 value signal D that wait ladder of standard _Outj, this 8 value sensing circuit is called 8 values again and reads correcting circuit.

Annotate: draw as follows with write circuit and the corresponding 8 value storage unit circuits of sensing circuit of 8 value DRAM; In the storage unit circuit of any K value DRAM, get K=8, choose power supply V _DdThe input of voltage ratio write circuit and the output logic value of sensing circuit be 7 the high Δ of logic level, Δ is DC level skew downward between the F input and output, draw the storage unit circuit of 8 value DRAM, show as Fig. 1, this 8 value DRAM storage unit circuit is by voltage follower F, the grid memory capacitance C of F _jWith two cmos transmission gate G ₁And G ₂Form, use capacitor C _jStore 8 value signals, voltage follower F comprises NMOS pipe Q _M1With NPN pipe Q _M2, pipe Q _M1Grid connect capacitor C _jAn end C _Mij, i.e. C _MijBe the input of voltage follower F, C _jOther end ground connection, the pipe Q _M1Source electrode take over Q _M2Grid and resistance R _M1, R _M1Other end ground connection, the pipe Q _M2Emitter-base bandgap grading F _OlijThrough constant current source I _jGround connection, Q _M2Emitter-base bandgap grading meets constant current source I _jMake pipe Q _M2The emitter-base bandgap grading load be constant current source, the pipe Q _M2Emitter-base bandgap grading F _OlijBe the output of F, pipe Q _M1Drain electrode and the pipe Q _M2Collector all meet power supply V _DdTransmission gate G ₁Input meet write bit line G _Wrij, transmission gate G ₁Output meet the input C of F _Mij, transmission gate G ₁Control input connect and write pulse w _Ri, transmission gate G ₂Input meet the output F of F _Olij, transmission gate G ₂Output meet sense bit line G _Rdij, transmission gate G ₂Control input meet read pulse r _Di, write pulse w _RiWith read pulse r _DiControl circuit from DRAM; Write pulse w _RiCome then transmission gate G ₁Conducting is with write bit line G _Wrij8 value signals be sent to memory capacitance C _j, capacitor C _jReceive G _Wrij8 value signals, capacitor C _j8 value signals be exactly F input C _Mij8 value signals; Write pulse w _RiFuture then, transmission gate G ₁End memory capacitance C _jWith the external world be direct current open circuit, capacitor C _j8 value signals of storage remain unchanged, and namely have memory function; Read pulse r _DiCome then transmission gate G ₂Conducting is exported F with F _Olij8 value signals be sent to sense bit line G _RdijWrite bit line G _WrijWith sense bit line G _RdijEach input and output of storage unit circuit naturally; Write circuit output and sensing circuit input are received in the storage unit circuit input and output separately; 8 value signals of voltage follower F output must be 8 value signals corresponding with the F input, and the F input/output information is identical, i.e. the no information dropout of F output, and the no information dropout of F output requires C _j8 value signals of storage are 8 value signals that increase, and described 8 value signals that increase are exactly the signal of the high Δ of 8 value signals imported than write circuit except 0 level, and wherein 0 level still is 0; The input signal of storage unit circuit is the output from write circuit, and the signal that write circuit output offers the storage unit circuit input is 8 value signals that increase; Increase 8 value signals and be sent to sense bit line G through F _RdijBe nonstandard 8 value signals, also be that storage unit circuit output is nonstandard 8 value signals, described nonstandard 8 value signals be exactly contrast DRAM input and output and write circuit input and sensing circuit output standard etc. 8 value signals of ladder be that the logic level amplitude is inconsistent; The sensing circuit input signal is nonstandard 8 value signals from storage unit circuit output, sensing circuit output is that storage unit circuit is exported 8 value signals that wait ladder that nonstandard 8 value signals are proofreaied and correct the standard that draws, and 8 value signals that wait ladder of the standard that this correction draws are as the correction of storage unit circuit storage information is read.

The concrete description of contents of the present invention is as follows:

(A) storage unit circuit of the present invention, the advantage of write circuit and sensing circuit.1. the advantage of storage unit circuit: circuit structure is simple and cost is extremely low.Since K＞2, each capacitor C _jStorage K value information is bigger than the quantity of information of storage two value informations, and obviously the more big cell stores quantity of information of K is more many, and C _jBe the metal-oxide-semiconductor grid capacitance, cost is extremely low, and in addition, storage unit circuit is only used G ₁And G ₂Form with F, circuit structure is simple, and is very favourable to many-valued DRAM; Generally require DRAM canned data amount The more the better, namely require the quantity of storage unit circuit to be the bigger the better, require each capacitor C _jThe canned data amount is The more the better, and it is more good less to require circuit structure simply to make to account for silicon area, and storage unit circuit of the present invention meets this requirement; 2. the advantage of sensing circuit: have good quantification shaping operation, namely have the former multilevel information ability of recovery, this ability is used for anti-interference and refreshes.With sinusoidal wave continuous signal input G _RdijThe output D that behind sensing circuit, draws _OutjCurve is discontinuous (proofreading and correct the ladder that waits for standard) multi-valued signal, shows that sensing circuit has the good similar 4 houses 5 quantification shaping operations of going into, as input G _RdijVoltage rises or descends (as electric leakage and disturbing effect) when not crossing up and down two new threshold values, exports D _OutjStill be the multilevel information (recovery prime information) that waits ladder of standard, namely have the former multilevel information ability of recovery, this ability is used for improving interference free performance and refreshing; 3. the advantage of write circuit: have good quantification shaping operation (the 5 quantification effects of going into of similar 4 houses), draw the stable multilevel information that increases that meets the demands; Sinusoidal wave continuous signal input D _InjThe output G that after write circuit, draws _WrijCurve is discontinuous multilevel information (multilevel information that increases), as input D _InjVoltage rises or descends (as disturbing effect) when not crossing up and down two new threshold values, exports G _WrijStill recover former (increasing) multilevel information, namely have the former multilevel information ability that increases of recovery, this ability also can be used for anti-interference and refreshes.Recover former multilevel information and refresh all at information.The very big and used silicon area of DRAM memory space is little just to be necessarily required: storage unit circuit quantity is very big, and the quantity of write circuit and sensing circuit is few as far as possible; Their quantity does not wait.Many-valued DRAM storage unit (comprising conventional two-value DRAM storage unit) is to line up matrix type structure by row, column, and the row decoding output line is all storage unit that word line (row is selected line) is chosen delegation in the storage matrix (a word line).To word length n position (as 4,8 or N position), row address decoder translates each word line and exports when effective, there be n (as 4,8 or N) selected simultaneously (cmos transmission gate by this unit makes the multilevel information of its storage connect with outer to storage unit, carry out message exchange), there are n root write bit line and sense bit line to connect a storage unit on selected this separately, be connected to write circuit at every write bit line, be connected to sensing circuit on the every sense bit line, make these selected storage unit through sensing circuit and write circuit, carry out read-write operation by read/write control circuit etc.Many-valued storage unit circuit, many-valued sensing circuit and many-valued write circuit are the ten minutes important components, arbitrarily the storage unit circuit of K value and 8 value DRAM keeps very simply structure, only writes with reading circuit structure big or small differently with the K value, and its advantage is very significant.Except the multidigit input and output, in order to improve the number that integrated level reduces device pin simultaneously, the mode that big capacity DRAM usually adopts 1 input, 1 output and address timesharing to import, this moment, storage unit still kept lining up matrix type structure by row, column, and partly wait to finish data serial input string line output task by DRAM input buffering, output buffering (annotate: the DRAM input and output refer to the input and output of DRAM data) and address input buffer part and control circuit, sometimes in addition the address also available serial import.If storage unit circuit, write circuit and sensing circuit are classified as an integrated circuit, then be cost high with unpractical, storage unit circuit in the practicality, the quantity of write circuit and sensing circuit differs widely; Storage unit circuit, write circuit and sensing circuit are quantitatively spatially inequality, and they are the three kinds of circuit that are closely related by a unified design of total inventive concept by information characteristics.

(B) three kinds of circuit focus on information characteristics, i.e. storage unit circuit, and write circuit and sensing circuit focus on information: the information storage, information writes with information and reads.Storage unit circuit institute canned data does not have information dropout and requires: what write circuit was delivered to the storage unit circuit input is the multilevel information that increases.Storage unit circuit is exported nonstandard multilevel information requirement: it is the multilevel information output that waits ladder of standard that sensing circuit is proofreaied and correct nonstandard multilevel information.Storage unit circuit also is to focus on information characteristics, and storage unit circuit has the multilevel information storage, and multilevel information receives and multilevel information sends three information characteristics: 1. information receives: write bit line G _WrijMultilevel information be sent to memory capacitance C _j, make capacitor C _jReceive multilevel information C _Mij2. information storage: G ₁Capacitor C when ending _jBe almost infinity with extraneous direct current resistance, use capacitor C _jCan well store multi-valued signal; 3. information is sent: transmission gate G ₂Conducting, the multilevel information of voltage follower F output is sent to sense bit line G _RdijStorage unit circuit, write circuit has identical important information feature with sensing circuit: the storage unit circuit input is consistent with the information characteristics of write circuit output, and they all are the multilevel informations that increases; Storage unit circuit output is consistent with the information characteristics of sensing circuit input, and they all are nonstandard multilevel informations; The write circuit input is consistent with the information characteristics of sensing circuit output, they all are the multilevel informations such as ladder such as grade (annotate: the multilevel information such as ladder such as grade of this standard is consistent with the information characteristics of DRAM input and output, and the DRAM input and output are exactly the input and output of DRAM data) of standard.

(C) by total inventive concept two kinds of write circuits that are closely related of unified design and sensing circuit, the sensing circuit of K value DRAM is identical with the architectural feature of the write circuit of any K value DRAM arbitrarily, contrast Fig. 4 and Fig. 5, or contrast Fig. 2 and Fig. 3, find out immediately: the architectural feature of write circuit and sensing circuit is identical, and (the variable threshold type PMOS pipe of two circuit is identical with the pipe number of diode, connected mode between each pipe is mutually equal), but the parameter difference, the function difference.

By any K value DRAM storage unit, write the identical information feature with sensing circuit, used in a design total thinking is expressed as follows:

The DRAM input and output are multi-valued signals of standard, if thinking routinely, capacitor C _jThe multi-valued signal that directly receives the standard of DRAM input is also preserved, i.e. capacitor C _jWhat store is the multi-valued signal of standard, C _jThe multi-valued signal of the standard of storage is through voltage follower F, and the situation that just has drop-out in the output of F takes place, and therefore conventional thinking is unavailable.Change the design of thinking now, for the situation of drop-out does not take place in the output that guarantees F, the F input is inevitable inequality with the information characteristics of standard, can use the multi-valued signal that increases instead and be sent to capacitor C _j(being the F input), this multi-valued signal that increases requires to satisfy: can guarantee that F output does not have the situation generation of drop-out, and can guarantee that F is exported nonstandard multi-valued signal and proofread and correct and be the multi-valued signal of standard, read as information correction, make and to see from the outside to read and be still correct multi-valued signal, show through sensing circuit and can read multi-valued signal with the standard of DRAM input and output identical characteristics, namely sensing circuit is proofreaied and correct nonstandard multi-valued signal and is the multi-valued signal of standard; This shows, by above-mentioned information characteristics, and write circuit input and sensing circuit to export be that the requirement of multi-valued signal of standard designs write circuit and sensing circuit, then the reading difficulty has just overcome.

Description of drawings

Fig. 1. a kind of any K value of being correlated with for the present invention and the storage unit circuit figure of 8 value DRAM;

Fig. 2. be the write circuit figure of a kind of 8 value DRAM of the present invention;

Fig. 3. be the sensing circuit figure of a kind of 8 value DRAM of the present invention;

Fig. 4. be the write circuit figure of a kind of K value DRAM of the present invention;

Fig. 5. be the sensing circuit figure of a kind of K value DRAM of the present invention;

Fig. 6. the first kind of PMOS that is correlated with for the present invention manages variable threshold circuit diagram and variable threshold type PMOS pipe graphical diagram;

Fig. 7. the second kind of PMOS that is correlated with for the present invention manages variable threshold circuit diagram and variable threshold type PMOS pipe graphical diagram;

Fig. 8. for using V among Fig. 6 _DcReplace V _DdFirst kind of PMOS pipe variable threshold circuit diagram and variable threshold type PMOS pipe graphical diagram;

Fig. 9. for using V among Fig. 7 _DcReplace V _DdSecond kind of PMOS pipe variable threshold circuit diagram and variable threshold type PMOS pipe graphical diagram;

Figure 10. be existing a kind of many accurate mirror-image constant flow source circuit diagrams of output and graphical diagram;

Figure 11. for the storage unit circuit of write circuit of the present invention and sensing circuit and relevant 8 value DRAM, at w _RiAnd r _DiW under acting on successively _Ri, r _Di, D _Inj, G _Wrij, C _Mij, F _Olij, G _RdijAnd D _OutjPriority discrete oscillogram up and down;

Figure 12. be the write circuit input D of the present invention 8 value DRAM _InjWith sensing circuit output D _OutjAt w _RiAnd r _DiOscillogram under acting on successively;

Figure 13. be the write circuit input D of the present invention 8 value DRAM _InjWith output G _WrijAt w _RiOscillogram under the effect;

Figure 14. be the sensing circuit input G of the present invention 8 value DRAM _RdijWith output D _OutjAt r _DiOscillogram under the effect;

Figure 15. be the input C of the voltage follower F of the storage unit circuit of the present invention 8 value DRAM _MijWith output F _OlijW is being arranged _RiMake the oscillogram of time spent;

Figure 16. for the storage unit circuit of write circuit of the present invention and sensing circuit and relevant 8 value DRAM, at w _RiAnd r _DiD under acting on successively _Inj, G _Wrij, C _Mij, F _Olij, G _RdijAnd D _OutjNot discrete oscillogram up and down;

Figure 17. for the present invention 8 is worth the write circuit of DRAM at w _Ri=0 transmission gate G ₁Import D when ending and with write circuit _InjWrite circuit input D when changing sine wave into _InjWith write circuit output G _WrijOscillogram;

Figure 18. for the present invention 8 is worth the sensing circuit of DRAM at r _Di=0 transmission gate G ₂Import G when ending and with sensing circuit _RdijSensing circuit input G when changing sine wave into _RdijWith sensing circuit output D _OutjOscillogram;

Figure 19. be circuit and the graphical diagram of cmos transmission gate commonly used.

Embodiment

The present invention is further illustrated for following mask body:

Embodiment 1: the explanation of storage unit circuit informational function.

Storage unit circuit has the multilevel information storage, and multilevel information receives and multilevel information sends three informational functions: 1. information receives: found out by Fig. 1, write pulse w _RiCome then transmission gate G ₁Conducting is with write bit line G _WrijMultilevel information be sent to memory capacitance C _j, make capacitor C _jReceive multilevel information C _MijCapacitor C _jReception is a charge and discharge process, is that capacitor C is depended in charging or discharge _jFormer canned data and the existing information that receives discharge and recharge time constant and are C _jElectric capacity is relevant, C _jUsually only be several pico farads, can not be big again; 2. information storage: write pulse w _RiFuture then, transmission gate G ₁End, found out by Fig. 1, memory capacitance C _jOnly with NMOS pipe Q _M1Grid and cmos transmission gate G ₁Output link to each other pipe Q _M1The grid input resistance approach open circuit, G ₁Also approach open circuit, capacitor C at this moment when ending _jBe almost infinity with extraneous direct current resistance, use capacitor C _jCan well store multi-valued signal; 3. information is sent: found out read pulse r by Fig. 1 _DiCome then transmission gate G ₂Conducting, the multilevel information that voltage follower F is exported is sent to sense bit line G _Rdij, both made capacitor C _jFaint electric leakage and F imperfection are arranged, influence F output and be sent to sense bit line G _RdijMultilevel information, but sensing circuit still have the ability to be proofreaied and correct the multilevel information for correct standard.

Attention: transmission gate G ₁When ending, require C in theory _jWith the external world be direct current open circuit, namely direct current resistance be infinity, in fact C _jWith the external world be high resistant (almost not having DC channel), still actual have faint electric leakage, a C _jThe multi-valued signal of storage can only keep certain hour, so all DRAM need add a refresh circuit in addition, and periodic refreshing makes it recover the former information of depositing.

Voltage follower F is very important in the storage unit circuit, but if the improper use of F input information, then actual F output has the situation of losing multilevel information to take place, and uses capacitor C _j(F input) storage multilevel information is that cost is extremely low, conventional DRAM capacitor C _jStore two value informations, the quantity of information of two value informations is minimum, and the quantity of information of multilevel information is used capacitor C than the height of two-value _jThe storage multilevel information is more to one's profit certainly than storage two value informations.F output has the reason of losing the multilevel information generation to be described below: if capacitor C _jReceive a desired voltage follower F _AInput, desired voltage follower F _AThe voltage amplification factor perseverance be 1, no direct current offset, then F _AOutput voltage and capacitor C _jVoltage is identical, i.e. F _AOutput and capacitor C _jThe multilevel information of storage is identical.Do not have the desired voltage follower in the reality, the voltage amplification factor of virtual voltage follower (F among the present invention) is less than 1, and the direct current offset Δ is arranged, and works as capacitor C _jOn voltage during less than Δ (be 1 as logical value, its logic level=V _Don＜Δ), F is output as 0, i.e. C _jThe storage signal logical value is not 0, and F output signal logical value is 0; For overcoming the shortcoming of direct current offset, avoid F output information to lose, what write circuit offered the storage unit circuit input is the multi-valued signal that increases Δ, being the multi-valued signal of non-standard and the multi-valued signal that increases Δ is exported behind F, is the multi-valued signal that waits ladder of standard with this correction with sensing circuit further.Consider input D _InjWith output D _OutjStepped-up voltage identical, stepped-up voltage equals the forward voltage V of diode _Don, input D _InjWith output D _OutjThe largest logical level equal V _DonL (LV doubly _Don), so supply voltage V _DdThan the high Δ of above-mentioned largest logical level, Δ is calculated or is surveyed out by F easily, C _jUsually only be several pico farads.

Cmos transmission gate shows as Figure 19 in the storage unit circuit, and namely Figure 19 is circuit and the graphical diagram of cmos transmission gate commonly used, and cmos transmission gate (is NMOS pipe Q by a P raceway groove and a N channel enhancement MOSFET _G1With PMOS pipe Q _G2) be formed in parallel, it (is NMOS pipe Q that this cmos transmission gate itself has a CMOS phase inverter _G4With PMOS pipe Q _G3).The cmos transmission gate circuit is simple, but the transmitted in both directions signal is commonly used for analog switch.

Embodiment 2: the proof that the write circuit of any K value and 8 value DRAM meets design requirement.

The write circuit of K value DRAM is shown as Fig. 4 arbitrarily, needs proof to meet design requirement: as write circuit input D _InjLogical value is 0,1,2,3,4 ..., when L-2, L-1, L, write circuit output G _WrijLogical value still is followed successively by 0,1,2,3,4 ..., L-2, L-1, L; But G _WrijLogical value counterlogic level V _Gwrij(n) except 0 level, compare D _InjLogical value counterlogic level V _Dinj(n) (n=1～L), 0 level still is 0 to high Δ, i.e. V _Gwrij(0)=V _Dinj(0)=0V, V _Gwrij(1)=V _Dinj(1)+Δ, V _Gwrij(2)=V _Dinj(2)+Δ ..., V _Gwrij(L-1)=V _Dinj(L-1)+Δ, V _Gwrij(L)=V _Dinj(L)+and Δ, V _Dinj(k)＞V _Dinj(k-1); Ta _kAdjacent logic levels V for the write circuit input _Dinj(k) and V _Dinj(k-1) intermediate value satisfies V _Dinj(k-1)＜ta _k＜V _Dinj(k), k=1,2,3,4 ..., L-2, L-1, L, namely satisfy inequality 0＜ta ₁＜V _Dinj(1)＜ta ₂＜V _Dinj(2)＜ta ₃＜V _Dinj(3)＜ta ₄＜...＜ta _L-2＜V _Dinj(L-2)＜ta _L-1＜V _Dinj(L-1)＜ta _L＜V _Dinj(L); Because pipe Qa _kForward voltage is 0V (or nearly 0V), pipe Qa _kForward voltage is managed Qa exactly _kPressure drop during conducting between source electrode and drain electrode, pipe Qa _kThe conducting electric current is got less value (as 30 μ A), also is constant current source I _jElectric current is got less value (as 30 μ A), note V _DinjAnd V _GwrijThe write circuit of respectively doing for oneself input D _InjWith output G _WrijVoltage (instantaneous value), diode turn-on voltage V _DonEqual to import V _DinjThe stepped-up voltage of K value signal, also be V _DonEqual V _DinjThe poor V of each adjacent logic levels _Dinj(m)-V _Dinj(m-1), so V _Dinj(m)=mV _Don, supply voltage V _DdThan the high Δ of maximal value of the K value logic level of the output of the input of write circuit and sensing circuit, i.e. V _Dd=V _Doutj(L)+Δ=V _Dinj(L)+Δ=LV _Don+ Δ.

The input/output relation proof of write circuit is as follows: according to above-mentioned inequality 0＜ta ₁＜V _Dinj(1)＜ta ₂＜V _Dinj(2)＜ta ₃＜V _Dinj(3)＜ta ₄＜...＜ta _L-2＜V _Dinj(L-2)＜ta _L-1＜V _Dinj(L-1)＜ta _L＜V _Dinj(L), found out by Fig. 4: 1. work as D _InjWhen importing 0 level, V _Dinj(0)＜ta ₁, all manage Qa ₁～Qa _LAll end the write circuit output voltage V _Gwrij=V _Dinj(0)=and 0V, 2. work as D _InjWhen importing 1 level, ta ₁＜V _Dinj(1)＜ta ₂, pipe Qa ₁Conducting, pipe Qa ₂～Qa _LEnd, (L-1) individual diode Da ₂～Da _LConducting, V _Gwrij=V _Dd-(L-1) V _Don=LV _DonThe V of+Δ-(L-1) _Don=V _Don+ Δ=V _Dinj(1)+and Δ, 3. work as D _InjWhen importing 2 level, ta ₂＜V _Dinj(2)＜ta ₃, pipe Qa ₁And Qa ₂Conducting, pipe Qa ₃～Qa _LEnd, (L-2) individual diode Da ₃～Da _LConducting, V _Gwrij=V _Dd-(L-2) V _Don=LV _DonThe V of+Δ-(L-2) _Don=2V _Don+ Δ=V _Dinj(2)+and Δ, 4. work as D _InjWhen importing 3 level, ta ₃＜V _Dinj(3)＜ta ₄, pipe Qa ₁～Qa ₃Conducting, pipe Qa ₄～Qa _LEnd, (L-3) individual diode Da ₄～Da _LConducting, V _Gwrij=V _Dd-(L-3) V _Don=LV _DonThe V of+Δ-(L-3) _Don=3V _Don+ Δ=V _Dinj(3)+Δ ... 5. work as D _InjDuring input L-2 level, ta _L-2＜V _Dinj(L-2)＜ta _L-1, pipe Qa ₁～Qa _L-2Conducting, pipe Qa _L-1And Qa _LEnd 2 diode Da _L-1And Da _LConducting, V _Gwrij=V _Dd-2V _Don=LV _Don+ Δ-2V _Don=(L-2) V _Don+ Δ=V _Dinj(L-2)+and Δ, 6. work as D _InjDuring input L-1 level, ta _L-1＜V _Dinj(L-1)＜ta _L, pipe Qa ₁～Qa _L-1Conducting, pipe Qa _LEnd 1 diode Da _LConducting, V _Gwrij=V _Dd-V _Don=LV _Don+ Δ-V _Don=(L-1) V _Don+ Δ=V _Dinj(L-1)+and Δ, 7. work as D _InjDuring input L level, ta _L＜V _Dinj(L), pipe Qa ₁～Qa _LConducting, V _Gwrij=V _Dd=LV _Don+ Δ=LV _Don+ Δ=V _Dinj(L)+Δ.Draw the output G of write circuit thus _WrijThan the high Δ of K value signal of write circuit input, 0 level still is 0 except 0 level, output G _WrijBe the K value signal that increases, overcome the deficiency that the DC level shifted by delta is arranged between the input and output of voltage follower F in the storage unit circuit.Pspice computer simulation waveform in the accompanying drawing also confirms its correctness.Used diode is silicon diode, and the conducting electric current is got smaller value, also is constant current source I _jElectric current is got less value, and Δ is easy to be calculated or surveyed out by F.Δ also desirable big slightly value, the output G of gained thus in the practicality _WrijBe Δ big slightly increase signal, the signal that increases that Δ is big slightly draws actual G through F _RdijThe unconventional K value signal of input, but do not influence the result, this is because sensing circuit can be with any unconventional non-K value signal G that waits ladder _RdijBe converted to the K value signal D that waits ladder of standard _Outj, this moment is as long as sensing circuit is pressed actual G _RdijThe unconventional K value signal (corresponding Δ is big slightly) of input designs and gets final product.

Get K=8 in the write circuit of K value DRAM arbitrarily, then draw the write circuit of 8 value DRAM, show as Fig. 2, prove that with quadrat method the write circuit of 8 value DRAM meets design requirement.Figure 10 is existing a kind of many output accurate mirror current source (constant current source) circuit diagrams and graphical diagram, for reducing power consumption and improving performance etc., its constant current source I _jElectric current is got smaller value.

Embodiment 3: the proof that the sensing circuit of any K value and 8 value DRAM meets design requirement.

The sensing circuit of K value DRAM shows as Fig. 5 arbitrarily, needs proof to meet design requirement: as the input G of sensing circuit _RdijLogical value is 0,1,2,3,4 ..., when L-2, L-1, L, the input D of sensing circuit _OutjLogical value still is followed successively by 0,1,2,3,4 ..., L-2, L-1, L; G _Rdij, D _InjAnd D _OutjLogical value counterlogic level is followed successively by V _Grdij(n), V _Dinj(n) and V _Doutj(n) (n=0～L), wherein import G _RdijBe the K value signal of non-standard, require output D _OutjBe the K value signal that waits ladder of standard, i.e. V _Doutj(0)=V _Dinj(0)=0V, V _Doutj(1)=V _Dinj(1)=V _Don, V _Doutj(2)=V _Dinj(2)=2V _Don, V _Doutj(3)=V _Dinj(3)=3V _Don... V _Doutj(L-2)=V _Dinj(L-2)=(L-2) V _Don, V _Doutj(L-1)=V _Dinj(L-1)=(L-1) V _Don, V _Doutj(L)=V _Dinj(L)=LV _DonTb _kBe input G _RdijThe adjacent logic levels V of unconventional K value signal _Grdij(k) and V _Grdij(k-1) intermediate value satisfies V _Grdij(k-1)＜tb _k＜V _Grdij(k), k=1,2,3,4 ..., L-2, L-1, L, namely satisfy inequality 0＜tb ₁V _Grdij(1)＜tb ₂＜V _Grdij(2)＜tb ₃＜V _Grdij(3)＜tb ₄＜...＜tb _L-2＜V _Grdij(L-2)＜tb _L-1＜V _Grdij(L-1)＜tb _L＜V _Grdij(L); Consider pipe Qb _kForward voltage is 0V (or nearly 0V), pipe Qb _kForward voltage is managed Qb exactly _kPressure drop during conducting between source electrode and drain electrode, pipe Qb _kThe conducting electric current is got less value (as 30 μ A), i.e. constant current source I _jElectric current is got less value (as 30 μ A), note V _GrdijAnd V _DoutjThe sensing circuit of respectively doing for oneself input G _RdijWith output D _OutjVoltage (instantaneous value), diode turn-on voltage V _DonEqual to export D _OutjThe stepped-up voltage of K value signal of standard, also be V _DonEqual to export D _OutjThe poor V of each adjacent logic levels _Doutj(m)-V _Doutj(m-1), so V _Doutj(m)=mV _Don, supply voltage V _DcLargest logical level V etc. the output of the input of write circuit and sensing circuit _Dinj(L) and V _Doutj(L), V _Dc=V _Doutj(L)=LV _Don

The input/output relation proof of sensing circuit is as follows: according to above-mentioned inequality 0＜tb ₁＜V _Grdij(1)＜tb ₂＜V _Grdij(2)＜tb ₃＜V _Grdij(3)＜tb ₄＜... tb _L-2＜V _Grdij(L-2)＜tb _L-1＜V _Grdij(L-1)＜tb _L＜V _Grdij(L), found out by Fig. 5: 1. work as G _RdijWhen importing 0 level, V _Grdij(0)=and 0V, V _Grdij(0)＜tb ₁, all manage Qb ₁～Qb _LAll end the output voltage V of sensing circuit _Doutj2.=0V works as G _RdijWhen importing 1 level, tb ₁＜V _Grdij(1)＜tb ₂, pipe Qb ₁Conducting, pipe Qb ₂～Qb _LEnd, (L-1) individual diode Db ₂～Db _LConducting, V _Doutj=V _Dc-(L-1) V _Don=LV _Don-(L-1) V _Don=V _Don=V _Doutj(1), 3. works as G _RdijWhen importing 2 level, tb ₂＜V _Grdij(2)＜tb ₃, pipe Qb ₁And Qb ₂Conducting, pipe Qb ₃～Qb _LEnd, (L-2) individual diode Db ₃～Db _LConducting, V _Doutj=V _Dc-(L-2) V _Don=LV _Don-(L-2) V _Don=2V _Don=V _Doutj(2), 4. work as G _RdijWhen importing 3 level, satisfy tb ₃＜V _Grdij(3)＜tb ₄, then manage Qb ₁～Qb ₃Conducting, pipe Qb ₄～Qb _LEnd, (L-3) individual diode Db is arranged ₄～Db _LConducting, V _Doutj=V _Dc-(L-3) V _Don=LV _DonThe V of+Δ-(L-3) _Don=3V _Don=V _Doutj(3) ... 5. work as G _RdijDuring input L-2 level, tb _L-2＜V _Grdij(L-2)＜tb _L-1, pipe Qb ₁～Qb _L-2Conducting, pipe Qb _L-1And Qb _LEnd 2 diode Db _L-1And Db _LConducting, V _Doutj=V _Dc-2V _Don=LV _Don-2V _Don=(L-2) V _Don=V _Doutj(L-2), 6. work as G _RdijDuring input L-1 level, tb _L-1＜V _Grdij(L-1)＜tb _L, pipe Qb ₁～Qb _L-1Conducting, pipe Qb _LEnd 1 diode Db _LConducting, V _Doutj=V _Dc-V _Don=LV _Don-V _Don=(L-1) V _Don=V _Doutj(L-1), 7. work as G _RdijDuring input L level, tb _L＜V _Grdij(L), pipe Qb ₁～Qb _LConducting, V _Doutj=V _Dc=LV _Don=V _Doutj(L).Draw thus: although sensing circuit input G _WrijBe the K value signal of non-standard, and sensing circuit output D _OutjBut be the value signal such as K such as ladder such as grade of standard, namely sensing circuit is with unconventional K value signal G _RdijBe converted to standard the K value signal D that waits ladder _OutjPspice computer simulation waveform in the accompanying drawing also confirms its correctness, and ladder K value signal D such as continuous wave (Figure 18) can be converted to _OutjUsed diode is silicon diode, and the conducting electric current is got smaller value.

Get K=8 in the sensing circuit of K value DRAM arbitrarily, then draw the sensing circuit of 8 value DRAM, show as Fig. 3, prove that with quadrat method the sensing circuit of 8 value DRAM meets design requirement.Figure 10 is existing a kind of many output accurate mirror current source (constant current source) circuit diagrams and graphical diagram, for reducing power consumption and improving performance etc., its constant current source I _jElectric current is got smaller value.

The explanation of embodiment 4:PMOS pipe variable threshold circuit (being called for short the variable threshold circuit).

First kind of PMOS pipe variable threshold circuit (being called for short first kind of variable threshold circuit) shows that it manages Q by NMOS as the empty frame in Fig. 6 left side ₃, PMOS manages Q ₄And resistance R ₃Form pipe Q ₃Grid meet input voltage V _x, pipe Q ₄Grid meet reference voltage V _Ref, pipe Q ₃Drain electrode be this circuit output V _Out1, output V _Out1Accept control PMOS pipe Q _T1Change reference voltage V _Ref, make Q _T1New threshold value change (amplify, dwindle, change and open character and improve unlatching resolution); Meet the pipe Q of PMOS pipe variable threshold circuit _T1Be called variable threshold type PMOS pipe.If V _Dd＞V _d〉=V _Tn+ | V _Tp|, V _Dd-V _d〉=| V _Tp|+V _Tn, note V _Extn1=V _Ref+ V _Tn+ | V _Tp|, V _RefBe reference voltage, NMOS and PMOS pipe threshold voltage are respectively V _Tn＞0 and V _Tp＜0.Pipe Q ₃And Q ₄Grid the source potential difference is respectively V _Gs3And V _Gs4, because Q ₃And Q ₄Two source electrodes join Q ₃Drain electrode through resistance R ₃Meet power supply V _Dd, Q ₄Grounded drain, only work as Q ₃And Q ₄The poor V of two grid voltages _G3-V _G4〉=V _Tn+ | V _Tp| the time, pipe Q ₃And Q ₄Just conducting simultaneously, otherwise end simultaneously.Because of V _G3=V _x, V _G4=V _Ref, draw thus: 1. work as V _x-V _Ref=V _G3-V _G4〉=V _Tn+ | V _Tp|, i.e. input voltage V _x〉=V _Ref+ V _Tn+ | V _Tp|=V _Extn1The time, pipe Q ₃And Q ₄Conducting, resistance R ₃On voltage V _Out1For very low, make Q _T1Conducting; 2. work as V _x＜V _Extn1The time, Q ₃And Q ₄End V _Out1=V _Dd, make Q _T1End; Show behind this variable threshold circuit, make Q _T1Become V _x〉=V _Extn1The time conducting, or variable threshold type PMOS pipe Q _T1New threshold value t size become V _Extn1, i.e. t=V _Extn1, change reference voltage V _Ref, t is changed, open character and change (Q _T1Become V _xConducting during 〉=t).Because of V _Dd〉=V _Ref〉=0, t=V _Extn1Minimum value is V _Tn+ | V _Tp|, first kind of PMOS pipe variable threshold circuit can not realize that t is less than V _Tn+ | V _Tp| new threshold value, less t also need realize with second kind of PMOS pipe variable threshold circuit.

Second kind of PMOS pipe variable threshold circuit (being called for short second kind of variable threshold circuit) shows that as the empty frame in Fig. 7 left side its structure (comprises NMOS pipe Q by first kind of PMOS pipe variable threshold circuit ₃, PMOS manages Q ₄And resistance R ₃) add a CMOS phase inverter and (comprise PMOS pipe Q ₅With NMOS pipe Q ₆) form, wherein manage Q ₄Grid meet input voltage V _x, pipe Q ₃Grid meet reference voltage V _Ref, pipe Q ₃Drain electrode meet CMOS phase inverter input (pipe Q ₅With pipe Q ₆Grid), CMOS phase inverter output (pipe Q ₅With pipe Q ₆Drain electrode) be this circuit output V _Out0, output V _Out0Accept control PMOS pipe Q _T0Change reference voltage V _Ref, make Q _T0New threshold value change (amplify, dwindle, change and open character and improve unlatching resolution); Meet the pipe Q of PMOS pipe variable threshold circuit _T0Be called variable threshold type PMOS pipe.If V _Dd＞V _d〉=V _Tn+ | V _Tp|, V _Dd-V _d〉=| V _Tp|+V _Tn, note V _Extn0=V _Ref-V _Tn-| V _Tp|, NMOS and PMOS pipe variable threshold threshold voltage are respectively V _Tn＞0 and V _Tp＜0.Pipe Q ₃And Q ₄Grid the source potential difference is respectively V _Gs3And V _Gs4, the same reason is only worked as Q ₃And Q ₄The poor V of two grid voltages _G3-V _G4〉=V _Tn+ | V _Tp| the time, pipe Q ₃And Q ₄Just conducting simultaneously, otherwise V _G3-V _G4＜V _Tn+ | V _Tp|, pipe Q ₃And Q ₄End simultaneously.Because of V _G3=V _Ref, V _G4=V _x, draw thus: 1. work as V _Ref-V _x=V _G3-V _G4＜V _Tn+ | V _Tp|, pipe Q ₃And Q ₄End, i.e. input voltage V _x＞V _Ref-V _Tn-| V _Tp|=V _Extn0The time, pipe Q ₃And Q ₄End pipe Q ₃Drain electrode (be CMOS phase inverter input) be V _DdSo, pipe Q ₅End and pipe Q ₆Conducting, CMOS phase inverter output V _Out0=V _d, make Q _T0Conducting; 2. work as V _x〉=V _Extn0The time, Q ₃And Q ₄Conducting, pipe Q ₃Drain electrode (be CMOS phase inverter input) for very low, so manage Q ₆End and pipe Q ₅Conducting, CMOS phase inverter output V _Out0=V _Dd, make Q _T0End.Show behind the variable threshold circuit, make Q _T0Become V _x〉=V _Extn0The time conducting, i.e. t=V _Extn0T=V wherein _Extn0=V _Ref-V _Tn-| V _Tp| can be less than V _Tn+ | V _Tp|, show variable threshold type PMOS pipe Q _T0New threshold value t size become V _Extn0, i.e. t=V _Extn0Change reference voltage V _Ref, t is changed, open character and change (Q _T0Become V _xConducting during 〉=t).Because of V _Dd〉=V _Ref〉=0, new threshold value t minimum value is 0, and maximal value is V _Dd-V _Tn-| V _Tp|.

Change reference voltage V _Ref, t is changed, first kind of PMOS pipe variable threshold circuit diagram 6 (t=V _Extn1=V _Ref+ V _Tn+ | V _Tp|) can not realize less than V _Tn+ | V _Tp| new threshold value t, second kind of PMOS pipe variable threshold circuit diagram, 7 (t=V _Extn0=V _Ref-V _Tn-| V _Tp|) can not realize greater than V _Dd-V _Tn-| V _Tp| new threshold value t, often need be used with two kinds of PMOS pipe variable threshold circuit.With the V among Fig. 6 and Fig. 7 _DdChange V into _Dc, then drawing Fig. 8 and Fig. 9 respectively, Fig. 8 can not realize less than V _Tn+ | V _Tp| new threshold value t, Fig. 9 can not realize greater than V _Dc-V _Tn-| V _Tp| new threshold value t, also often need be used with these two kinds of PMOS pipe variable threshold circuit.R among Fig. 6 and Fig. 7 (comprising Fig. 8 and Fig. 9) ₃Available constant current source I ₃Replace (current direction Q ₃Drain electrode).

For obtaining the different reference voltage V of a sequence _Ref(because sequence variable threshold type PMOS pipe has new threshold value ta separately _kOr tb _k, need with different reference voltage V _RefObtain required new threshold value by two kinds of PMOS pipe variable threshold circuit), can be used on the bleeder circuit that (by common method) between direct supply and ground connect a plurality of resistance series connection realizes, the bleeder circuit that also can be used on direct supply and the indirect a plurality of diodes in ground (or field-effect diode) series connection is realized (wherein according to circumstances needing also can connect a resistance), a plurality of diode cathodes are the same with the connection of battery series connection commonly used with the negative pole connection, as k diode D ₁～D _k, D ₁Positive pole connects direct supply, D ₁Negative pole meets D ₂Positive pole, D ₂Negative pole meets D ₃Positive pole ..., D _K-2Negative pole meets D _K-1Positive pole,, D _K-1Negative pole meets D _kPositive pole, D _kMinus earth (or by R ground connection) is realized, because the different reference voltage V of sequence _RefAll be to output to the metal-oxide-semiconductor grid, output DC stream is almost 0, so implement easily.Current source I described in the present invention shows as Figure 10, is a kind of accurate mirror current source of many outputs of ground connection commonly used.

Embodiment 5: to the explanation of Pspice computer simulation waveform Figure 11～16 of Fig. 1～3.

Write pulse w _RiWith read pulse r _DiControl circuit from DRAM (is considered the word line output W of address decoder _i, read/write control, the sheet choosing refreshes etc.), at r _DiAnd w _RiEffect under, the Pspice computer simulation is carried out in Fig. 1～3, draw various analog waveforms and show as Figure 11～16, annotate: w among the figure _Ri, r _Di, D _Inj, G _Wrij, C _Mij, F _Olij, G _RdijAnd D _Outj8 waveforms be written as V (wri) separately in each figure horizontal ordinate bottom, V (rdi), V (Dinj), V (Gwrij), V (Cmij), V (Folij), V (Grdij), 8 forms that have V of V (Doutj) namely are written as w respectively in the bracket of V back _Ri, r _Di, D _Inj, G _Wrij, C _Mij, F _Olij, G _RdijAnd D _Outj(wherein subscript changes non-down target normal font into, i.e. wri, rdi, Dinj, Gwrij, Cmij, Folij, Grdij and Doutj, this is that the Pspice simulation drawing is represented mode), below all oscillogram horizontal ordinate bottoms all write out by similar expression mode, describe no longer one by one.Figure 11 is the storage unit circuit of the present invention 8 value DRAM, and write circuit and sensing circuit are at w _RiAnd r _DiD under acting on successively _Inj, G _Wrij, C _Mij, F _Olij, G _RdijAnd D _OutjPriority discrete oscillogram up and down, be followed successively by w by Figure 11 order from top to bottom _Ri, r _Di, D _Inj, G _Wrij, C _Mij, F _Olij, G _RdijAnd D _Outj8 waveforms, Figure 12 is at w _RiAnd r _DiEffect under, D _InjAnd D _Outj2 waveforms, among the figure with w _RiAnd r _DiTen times of reduced height, and be placed on the foot (r of figure _DiAt the bottommost of figure, w _RiAt r _DiThe top), as can be seen from Figure 12, the input D of the write circuit of DRAM _InjThe output D of curve and sensing circuit _OutjCurve is the multi-valued signal that waits ladder, with the D of logical value _InjAnd D _OutjLogic level equate, satisfy described requirement, D _OutjBe at r _Di(seeing the bottommost of figure) then changes.Figure 13 is at w _RiUnder the effect of (seeing the bottommost of figure), the input D of 8 value DRAM write circuits _InjWith output G _Wrij2 waveforms, as can be seen from Figure 13, the input D _InjCurve is the multi-valued signal (being following curve relatively) that waits ladder, output G _WrijCurve is the multi-valued signal (being the top non-curve that waits ladder relatively) that increases, with the D of logical value _InjAnd G _WrijLogic level (except 0 level equates) be unequal, overcome the deficiency that downward DC level shifted by delta is arranged between the input and output of voltage follower F in the storage unit circuit thus.Figure 14 is at r _DiUnder the effect of (seeing the bottommost of figure), the input G of 8 value DRAM sensing circuits _RdijWith output D _Outj2 waveforms, as can be seen from Figure 14, the input G _RdijCurve is that less (relatively low curve is with D for ladder _InjLadder is inequality) multi-valued signal, with the D of logical value _InjAnd G _RdijLogic level be unequal, output D _OutjCurve (higher relatively curve) is and D _InjThe multi-valued signal that waits ladder that ladder is identical, namely sensing circuit is with unconventional multi-valued signal G _RdijBe converted to the multi-valued signal D that waits ladder of standard _Outj, overcome voltage follower F voltage amplification factor in the storage unit circuit thus less than 1 deficiency.Figure 15 is at w _RiUnder the effect of (seeing the bottommost of figure), the input C of the voltage follower F of 8 value DRAM storage unit circuits _MijWith output F _Olij2 waveforms, as can be seen from Figure 15, the input C _MijCurve is the multi-valued signal (being last surface curve relatively, the non-ladder that waits) that increases, and output F _OlijCurve (surface curve under being relatively) is to input C _MijCurve has downward level shift, and amplitude dwindles, and shows in the storage unit circuit that voltage follower F has downward level shift and voltage amplification factor less than 1.Figure 16 is the storage unit circuit of the present invention 8 value DRAM, and write circuit and sensing circuit are at w _RiAnd r _Di(r _DiAt the bottommost of figure, w _RiAt r _DiThe top) successively the effect under D _Inj, G _Wrij, C _Mij, F _Olij, G _RdijAnd D _OutjNot discrete oscillogram up and down, namely be equivalent to Figure 13, the merging of 6 curves among Figure 14 and Figure 15.

Embodiment 6: the explanation of the Pspice computer simulation waveform of Figure 17 and Figure 18.

Main Pspice analog waveform is finished in embodiment 5, consider the situation when write circuit and sensing circuit are input as sine wave respectively separately now, write reference with the sensing circuit advantage as further understanding, annotate: in order to separate with above-mentioned simulation region, the write circuit during input sine wave is imported D during this Pspice simulation _InjWith sensing circuit output D _OutjUse symbol IND separately instead _iAnd OUTD _i(remain separately at write circuit input D _InjWith sensing circuit output D _OutjOn 2, i.e. symbol difference, input and output point of each expression is identical, still is called write circuit during explanation and imports D _InjWith sensing circuit output D _Outj), so the input of the write circuit in 17 D _InjWith the sensing circuit output D among Figure 18 _OutjPspice analog waveform figure horizontal ordinate bottom be written as V (INDi) and V (OUTDi) separately, and G _Wrij, G _RdijFollowing and aforementioned identical V (Gwrij), the V (Grdij) of still being written as successively of Pspice analog waveform figure horizontal ordinate.Figure 17 is worth the write circuit of DRAM at w for the present invention 8 _Ri=0 transmission gate G ₁By the time and the input D _InjInput D during for sine wave _InjWith output G _WrijOscillogram, as can be seen from Figure 17, sinusoidal wave continuous signal input D _InjThe output G that curve draws after write circuit _WrijCurve is discontinuous multi-valued signal (increasing effect but have), shows that write circuit has good quantification shaping operation (the 5 quantification effects of going into of similar 4 houses), as input D _InjVoltage rises or descends when not crossing up and down two new threshold values, exports G _WrijStill can recover former multilevel information, namely have the former multilevel information ability of recovery, this ability also can be used for refreshing.Figure 18 is worth the sensing circuit of DRAM at r for the present invention 8 _Di=0 transmission gate G ₂By the time and the input G _RdijInput G during for sine wave _RdijWith output D _OutjOscillogram.As can be seen from Figure 18, sinusoidal wave continuous signal input G _RdijThe output D that curve draws behind sensing circuit _OutjCurve is discontinuous (proofreading and correct to waiting ladder) multi-valued signal, shows that sensing circuit has good quantification shaping operation (the 5 quantification effects of going into of similar 4 houses), as input G _RdijVoltage rises or descends when not crossing up and down two new threshold values, exports D _OutjStill can recover former multilevel information, namely have the former multilevel information ability of recovery, this ability also can be used for refreshing.Recover former multilevel information ability for improving interference free performance, increasing, alleviate and refresh task, can suitably strengthen the numerical value of the memory capacitance of storage unit.In addition, the sensing circuit input also is the grid of metal-oxide-semiconductor, has the information memory action equally, recovers former multilevel information ability for improving interference free performance, increasing, and alleviates and refreshes task, and its grid input capacitance is also with slightly greatly favourable.

Embodiment 7: choose ta _kAnd tb _kThe explanation of numerical value.

Theoretical proof above-mentioned (1) and (2) only require that satisfying following inequality gets final product: proving that (1) is only required satisfies 0＜ta ₁＜V _Dinj(1)＜ta ₂＜V _Dinj(2)＜ta ₃＜V _Dinj(3)＜ta ₄＜...＜ta _L-2＜V _Dinj(L-2)＜ta _L-1＜V _Dinj(L-1)＜ta _L＜V _Dinj(L), proving that (2) are only required satisfies 0＜tb ₁＜V _Grdij(1)＜tb ₂＜V _Grdij(2)＜tb ₃＜V _Grdij(3)＜tb ₄＜...＜tb _L-2＜V _Grdij(L-2)＜tb _L-1＜V _Grdij(L-1)＜tb _L＜V _Grdij(L); Find out from proof procedure, the arbitrary value between the new desirable adjacent logic levels of threshold value in theory, in fact, and one. by the anti-interference requirement, preferably get the mean value that approaches or equal adjacent logic levels, the present invention just is based on that anti-interference requires to design; Two. by the refresh performance requirement, preferably get the mean value a little more than adjacent logic levels, make to allow discharge charge more, but take into account the anti-interference requirement, suitable deviation average is can not deviation average very big; Three. when input voltage equals new threshold value, output is in the zone of transition between adjacent logic levels, the size of zone of transition depends on that the unlatching resolution of new threshold value is (on the mathematics ' when input 〉=new threshold value, then manage conducting ', only be desirable, reality do not contain=), this unlatching resolution is preferably, but does not reach mathematical desirable requirement.

Embodiment 8: use resistance R _jReplace constant current source I _jExplanation.

' constant current source I _jBe taken as resistance R _j' namely " in (4) described K value DRAM storage unit circuit, constant current source I _jBe taken as resistance R _j", refer in K value DRAM storage unit circuit and ' use resistance R _jReplace constant current source I _j', resistance R just _jOne termination emitter-base bandgap grading F _Olij, resistance R _jOther end ground connection has been managed Q since like this _M2And resistance R _jConstitute emitter follower.Because emitter-base bandgap grading F _OlijThrough constant current source I _jGround connection is constant current source I just _jOne termination emitter-base bandgap grading F _Olij, constant current source I _jOther end ground connection is managed Q this moment _M2With constant current source I _jConstitute emitter follower; In other words, exactly change ' pipe Q _M2Emitter-base bandgap grading F _OlijThrough constant current source I _jGround connection ' be ' pipe Q _M2Emitter-base bandgap grading F _OlijThrough resistance R _jGround connection ', the former uses constant current source I _jQ then _M2Emitter current constant, the latter uses resistance R _jQ then _M2Emitter current non-constant, but this two (meet I _jWith meet R _j) all be the emitter follower structure of using always.Annotate: pipe Q _M1Source electrode connecting resistance R _M1(R _M1Other end ground connection), namely constitute source follower (common drain amplifying circuit).Source follower and emitter follower are the circuit of using always, similar with emitter follower (triode common collector amplifying circuit), field effect transistor source follower (common drain amplifying circuit) does not have the voltage amplification effect, its voltage gain is less than 1, output voltage is identical with input voltage phase, the input resistance height, output resistance is low, can do the impedance conversion and use.The input resistance of source follower is high, is fit to connect memory capacitance C _j(it is minimum to leak electricity), the input resistance of emitter follower is low, uncomfortable splice grafting memory capacitance C _j(electric leakage is big), but the output resistance of source follower is than the output resistance height of emitter follower, load capacity is poor, for increasing load capacity, the output of source follower can be connect the input of emitter follower, with the output of the emitter-base bandgap grading output as voltage follower, its output loading capability is just strengthened greatly.

Claims (4)

1. the write circuit of any K value DRAM is characterized in that: in the write circuit of described K value DRAM, establish K=3, and 4,5, Adopt K-1=L variable threshold type PMOS pipe Qa _k, k=1,2,3 ..., L, pipe Qa _kGrid be connected to the input D of write circuit through the variable threshold circuit _Inj, variable threshold type PMOS manages Qa _kNew threshold value be ta _k, pipe Qa _kDuring conducting between source drain pressure drop be 0; Pipe Qa _kSource electrode meet power supply V _Dd, choose V _DdVoltage ratio write circuit input and the largest logical level V that exports of sensing circuit _Dinj(L) and V _Douj(L) high Δ, Δ are DC level skews downward between voltage follower F input and output; Adopt L-1 diode Da _n, n=2,3 ..., L, diode Da _nForward voltage be V _DonDa _nPositive pole and negative pole be connected respectively to variable threshold type PMOS pipe Qa _N-1Drain electrode and the pipe Qa _nDrain electrode; Pipe Qa _LDrain electrode through constant current source I _jGround connection, pipe Qa _LDrain electrode meet constant current source I _jMake the electric current of the conducting diode of flowing through keep same fixed value, at pipe Qa _LDrain electrode form the output G of write circuit _Wrij, write circuit output G _WrijReceive the write bit line input of storage unit circuit; Choose ta _kBe write circuit input D _InjThe adjacent logic levels V of K value signal _Dinj(k) and V _Dinj(k-1) mean value (V _Dinj(k)+V _Dinj(k-1))/2, i.e. ta _kBe V _Dinj(k) and V _Dinj(k-1) intermediate value, V _Dinj(k)＞V _Dinj(k-1); Write circuit input D _InjK value signal and sensing circuit output D _OutjAnd the characteristic of the K value signal that waits ladder of the standard of DRAM input and output is identical: input D _InjThe difference of each adjacent logic levels equates, output D _OutjThe difference of each adjacent logic levels equates, and input D _InjWith output D _OutjStepped-up voltage identical, stepped-up voltage is V _Don, also namely satisfy V _Dinj(m)-V _Dinj(m-1)=V _Doutj(m)-V _Doutj(m-1)=V _Don, m=1,2,3 ..., L, V _Dinj(m) and V _Doutj(m) be respectively that write circuit input and sensing circuit output logic value are the logic level of m; The output G of write circuit _WrijThan the high Δ of K value signal of write circuit input, 0 level still is 0 except 0 level, and this K value write circuit is called the K value again and writes attack circuit.

2. the sensing circuit of any K value DRAM that forms according to the same structure feature of the write circuit of the described any K value DRAM of claim 1 is characterized in that: in the sensing circuit of described K value DRAM, establish K=3, and 4,5, Adopt K-1=L variable threshold type PMOS pipe Qb _k, k=1,2,3 ..., L, pipe Qb _kGrid be connected to the input G of sensing circuit through the variable threshold circuit _Rdij, variable threshold type PMOS manages Qb _kNew threshold value be tb _k, pipe Qb _kDuring conducting between source drain pressure drop be 0; G _RdijReceive the sense bit line output of storage unit circuit, pipe Qb _kSource electrode meet power supply V _Dc, choose V _DcVoltage equal the largest logical level V that write circuit input and sensing circuit are exported _Dinj(L) and V _Douj(L); Adopt L-1 diode Db _n, n=2,3 ..., L, diode Db _nForward voltage be V _DonDb _nPositive pole and negative pole be connected variable threshold type PMOS pipe Qb respectively _N-1Drain electrode and the pipe Qb _nDrain electrode; Variable threshold type PMOS manages Qb _LDrain electrode through constant current source I _jGround connection, pipe Qb _LDrain electrode meet constant current source I _jMake the electric current of the conducting diode of flowing through keep same fixed value, at pipe Qb _LDrain electrode form the output D of sensing circuit _OutjChoose tb _kBe sensing circuit input G _RdijThe adjacent logic levels V of K value signal _Grdij(k) and V _Grdij(k-1) mean value (V _Grdij(k)+V _Grdij(k-1))/2, i.e. tb _kBe V _Grdij(k) and V _Grdij(k-1) intermediate value, V _Grdij(k)＞V _Grdij(k-1); Sensing circuit output D _OutjSignal and write circuit input D _InjAnd the characteristic of the K value signal that waits ladder of the standard of DRAM input and output is identical: input D _InjThe difference of each adjacent logic levels equates, output D _OutjThe difference of each adjacent logic levels equates, and input D _InjWith output D _OutjStepped-up voltage identical, stepped-up voltage is V _Don, also namely satisfy V _Dinj(m)-V _Dinj(m-1)=V _Doutj(m)-V _Doutj(m-1)=V _Don, m=1,2,3 ..., L, V _Dinj(m) and V _Doutj(m) be respectively that write circuit input and sensing circuit output logic value are the logic level of m; Sensing circuit input G _RdijBe the nonstandard K value signal from storage unit circuit output, described nonstandard K value signal be exactly contrast DRAM input and output and write circuit input and sensing circuit output standard etc. the K value signal of ladder be that the logic level amplitude is inconsistent; Sensing circuit output D _OutjBe the K value signal that waits ladder of standard, namely sensing circuit is with nonstandard K value signal input G _RdijBe converted to the K value signal output D that waits ladder of standard _Outj, this K value sensing circuit is called the K value again and reads correcting circuit.

3. the write circuit of a kind of any K value DRAM according to claim 1 is characterized in that: get K=8, draw the write circuit of 8 value DRAM, wherein adopt 7 variable threshold type PMOS pipe Qa _k, k=1,2,3 ..., 7, pipe Qa _kGrid be connected to the input D of write circuit through the variable threshold circuit _Inj, variable threshold type PMOS manages Qa _kNew threshold value be ta _k, pipe Qa _kDuring conducting between source drain pressure drop be 0; Pipe Qa _kSource electrode meet power supply V _Dd, choose V _DdVoltage ratio write circuit input and the largest logical level V that exports of sensing circuit _Dinj(7) and V _Douj(7) high Δ, Δ are DC level skews downward between the input and output of voltage follower F; Adopt 6 diode Da _n, n=2,3 ..., 7, diode Da _nForward voltage be V _DonDa _nPositive pole and negative pole be connected respectively to variable threshold type PMOS pipe Qa _N-1Drain electrode and the pipe Qa _nDrain electrode; Pipe Qa ₇Drain electrode through constant current source I _jGround connection, pipe Qa ₇Drain electrode meet constant current source I _jMake the electric current of the conducting diode of flowing through keep same fixed value, at pipe Qa ₇Drain electrode form the output G of write circuit _Wrij, write circuit output G _WrijReceive the write bit line input of storage unit circuit; Choose ta _kBe write circuit input D _InjThe adjacent logic levels V of 8 value signals _Dinj(k) and V _Dinj(k-1) mean value (V _Dinj(k)+V _Dinj(k-1))/2, namely choose ta _kBe V _Dinj(k) and V _Dinj(k-1) intermediate value, V _Dinj(k)＞V _Dinj(k-1); Write circuit input D _Inj8 value signals and sensing circuit output D _OutjAnd the characteristic of 8 value signals that wait ladder of the standard of DRAM input and output is identical: input D _InjThe difference of each adjacent logic levels equates, output D _OutjThe difference of each adjacent logic levels equates, and input D _InjWith output D _OutjStepped-up voltage identical, stepped-up voltage is V _Don, also namely satisfy V _Dinj(m)-V _Dinj(m-1)=V _Doutj(m)-V _Doutj(m-1)=V _Don, m=1,2,3 ..., 7, V _Dinj(m) and V _Doutj(m) be respectively that write circuit input and sensing circuit output logic value are the logic level of m; Write circuit output G _WrijThan the high Δ of 8 value signals of write circuit input, 0 level still is 0 except 0 level, and this 8 value write circuit is called 8 values again and writes attack circuit.

4. the same structure feature of a kind of write circuit according to the described any K value DRAM of claim 1 according to claim 2 and the sensing circuit of any K value DRAM of forming, it is characterized in that: get K=8, draw the sensing circuit of 8 value DRAM, wherein adopt 7 variable threshold type PMOS pipe Qb _k, k=1,2,3 ..., 7, pipe Qb _kGrid be connected to the input G of sensing circuit through the variable threshold circuit _Rdij, variable threshold type PMOS manages Qb _kNew threshold value be tb _kPipe Qb _kDuring conducting between source drain pressure drop be 0; G _RdijReceive the sense bit line output of storage unit circuit, pipe Qb _kSource electrode meet power supply V _Dc, choose V _DcVoltage equal the largest logical level V that write circuit input and sensing circuit are exported _Dinj(7) and V _Douj(7); Adopt 6 diode Db _n, n=2,3 ..., 7, diode Db _nForward voltage be V _DonDb _nPositive pole and negative pole be connected variable threshold type PMOS pipe Qb respectively _N-1Drain electrode and the pipe Qb _nDrain electrode; Variable threshold type PMOS manages Qb ₇Drain electrode through constant current source I _jGround connection, pipe Qb ₇Drain electrode meet constant current source I _jMake the electric current of the conducting diode of flowing through keep same fixed value, at pipe Qb ₇Drain electrode form the output D of sensing circuit _OutjChoose tb _kBe sensing circuit input G _RdijThe adjacent logic levels V of 8 value signals _Grdij(k) and V _Grdij(k-1) mean value (V _Grdij(k)+V _Grdij(k-1))/2, namely choose tb _kBe V _Grdij(k) and V _Grdij(k-1) intermediate value, V _Grdij(k)＞V _Grdij(k-1); Sensing circuit output D _OutjSignal and write circuit input D _InjAnd the characteristic of 8 value signals that wait ladder of the standard of DRAM input and output is identical: input D _InjThe difference of each adjacent logic levels equates, output D _OutjThe difference of each adjacent logic levels equates, and input D _InjWith output D _OutjStepped-up voltage identical, stepped-up voltage is V _Don, namely satisfy V _Dinj(m)-V _Dinj(m-1)=V _Doutj(m)-V _Doutj(m-1)=V _Don, m=1,2,3 ..., 7, V _Dinj(m) and V _Doutj(m) be respectively that write circuit input and sensing circuit output logic value are the logic level of m; Sensing circuit input G _RdijBe nonstandard 8 value signals from storage unit circuit output, described nonstandard 8 value signals be exactly contrast DRAM input and output and write circuit input and sensing circuit output standard etc. 8 value signals of ladder be that the logic level amplitude is inconsistent; Sensing circuit output D _OutjBe 8 value signals that wait ladder of standard, namely sensing circuit is with nonstandard 8 value signal G _RdijBe converted to the 8 value signal D that wait ladder of standard _Outj, this 8 value sensing circuit is called 8 values again and reads correcting circuit.

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