CN103324461B - Four addend binary parallel synchronous addition devices - Google Patents
Four addend binary parallel synchronous addition devices Download PDFInfo
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Abstract
The invention discloses a kind of four addend binary parallel synchronous addition devices, be mainly used in the numerical evaluation that digital arithmetic calculates field, it is made up of identical weights figure place adder circuit, carry synthetic circuit and final one's own department or unit and generation circuit, identical weights figure place adder circuit is for adding up high level or low level number in the original addend of each weights position, and show with continuous print high level at output terminal, simultaneously select one group of conducting in two groups of switches according to its parity, so that for final one's own department or unit with produce circuit and provide two-way power supply; Carry synthetic circuit is introduced single order carry line, second order carry line and is entered 3 lines, and carries out selection by Switch Controller low order carry line and generate them; Final one's own department or unit with generation circuit by carry line, switch selection is carried out to the power supply from identical weights figure place adder circuit and obtain final one's own department or unit and, circuit structure of the present invention is simple, and design regular, hardware spending is few, be easy to expand figure place, and only need the used time of 3 basic gate circuits.
Description
Technical field
The invention belongs to electronic technology field and field of computer architecture, be realize four all bit parallels of scale-of-two addend be added, synchronous produce each weights position carry and final one's own department or unit and adding circuit, can be widely used in the arithmetic and logic unit of all kinds of microprocessor, digital signal processor and some special-purposes.
Background technology
In adder circuit family, two addend totalizers because operand is little, circuit is simple, be easier to the reasons such as realization and paid close attention to, further investigate and widespread use.In disclosed scientific paper and patent, two addend totalizers realize primarily of transistor logic door.Because this gate circuit adopts transistor series structure, thus cause adding circuit concurrent operation weak effect, synchronism is not strong, and along with the increase of addend figure place, its hardware spending and operation time all may rise according to nonlinear relationship, and thus the current two addend binary adders generally used accomplish at most 64, the more totalizer of seniority, as 128 totalizers, cost performance loses practicality.
Present invention applicant discloses one " Universal multi-operand summator " in Chinese patent 201210373908.8, and 2 given addend totalizers can solve the problem.It can complete the computing more than 128 figure places by on-off circuit, and its hardware spending and addend figure place linear, its operation use time only needs 3 the basic gate circuit times fixed, with addend figure place have nothing to do.This circuit really accomplished parallel addition each, synchronous produce each carry and final one's own department or unit and.
Although 2 addend totalizers have lot of advantages, comprise the 2 addend totalizers that patent 201210373908.8 proposes, but it is cumulative to calculate 4 addends with it, that just needs repetitive operation 3 times, needs the time more than 9 basic gate circuits altogether.This runs counter to current research high-speed computer trend.Consider if there are a kind of 4 addend totalizers, it can walk abreast addition four all positions of scale-of-two addend, synchronous produce each weights position carry and final one's own department or unit and, the computing more than 128 figure places is completed within the time being no more than 3 basic gate circuits, and the hardware spending of this totalizer and addend figure place linear, so this totalizer has more advantage than current 2 addend totalizers, and such totalizer has also just had researching value and using value naturally.
The achievement in research of the outer rare 4 addend totalizers of Present Domestic, does not more meet the totalizer of this requirement.Although " Universal multi-operand summator " that disclosed in Chinese patent 201210373908.8 by present invention applicant can extract 4 addend totalizers, can meet parallel addition four all positions of scale-of-two addend, synchronous produce each weights position carry and final one's own department or unit and, and hardware spending and addend figure place linear, but this totalizer calculates the used time needs time of more than 6 basic gate circuits.Obviously, this 4 addend adder designs schemes are unsatisfactory.
Summary of the invention
In order to overcome above-mentioned defect, the invention discloses a kind of four addend binary parallel synchronous addition devices, is the scheme that solution four multidigit binary number parallel synchronous add up.This totalizer is primarily of identical weights figure place adder circuit, carry synthetic circuit and final one's own department or unit and produce circuit composition.Wherein, identical weights figure place adder circuit is the circuit realizing 4 one digit numbers additions.It is made up of two parts circuit, and some is statistical circuit, and another part is that power supply complementation initially adds and circuit.Statistical circuit mainly adds up the number of high level (as " 1 ") or low level (as " 0 ") in the original addend of each weights position, have employed selector switch array, and at output terminal with continuous high level (as " 1 ") and the display of continuous low level (as " 0 ") array configuration.This course of work needs the time of 1 basic gate circuit.Power supply complementary initially adding, controls 2 groups of switches with circuit by the output level of statistical circuit, wherein one group of switch conduction is selected, so that for final one's own department or unit with produce circuit and provide two-way power supply (or being called high level) according to one's own department or units of this 4 original addend in weights position and parity.The output port of this two-way power supply is named as strange power end and even power end respectively.When one's own department or unit and be odd number time, one group of switch conduction, strange power end externally provides power supply, and another group switch disconnects, and even power end is externally in high-impedance state; Otherwise, when one's own department or unit and be even number time, even power end externally provides power supply, and strange power end is externally in high-impedance state.This circuit working process also only needs the time of 1 basic gate circuit.
The result of carry synthetic circuit according to statistical circuit and the information from low level produce single order carry and second order carry, and it is as follows that its carry produces constraint condition:
Suppose 4 n bits be all n position (n be greater than 1 natural number) " 1 ", i.e. maximum number, can be write as 2n-1, then these 4 n figure places and be 4* (2
n-1)=(2
n+2-1)-2-1=
b(1).
Formula (1) illustrates: 4 multidigit binary numbers are added to enter " 11B " to a high position at most, namely produce 2 rank carries, and in other words, the 4 number sums of certain add low order carry, itself and be no more than 7.
Corresponding with " second order carry " and " single order carry ", invention introduces " second order carry line " and " single order carry line ", wherein the low and high level of second order carry line represents corresponding position and whether creates second order carry, single order carry line is more than or equal to " 2 " by the original input number of corresponding position and low order carry value sum and determines, shows that this position creates second order carry or single order carry.Like this, when second order carry line is high level, the high level of single order carry line only illustrates that this position creates carry, does not show necessarily there is single order carry, and when second order carry line is low level, the high level of single order carry line just shows that this position creates single order carry.
Known by defining above, when second order carry line is high level, single order carry line also one is decided to be high level.Consider when 4 summations that are added with low order carry of number sums of certain are more than or equal to 6, namely this position not only produces second order carry and also creates single order carry, in order to judge to create single order carry when whether second order carry line represents this position as the high level of single order carry line during high level, the present invention also introduces a mark line, be named " entering 3 lines ", in fact show whether this position is entered " 3 " to a high position.Like this, when second order carry line and single order carry line are all high level, if entering 3 lines is low level, then this position only produces second order carry, and if to enter 3 lines be high level, then this position not only produces second order carry and also creates single order carry.
The principle of design of carry synthetic circuit of the present invention is as follows: be directed to a certain position, 1. when 4 number sums are " 0 ", puts this position and enters 3 lines and second order carry line is low level, the possible second order carry of low level is transmitted to a high position with single order carry form simultaneously; 2. when 4 number sums are " 1 ", putting this position, to enter 3 lines be low level, and low level is entered 3 line states be transferred to this second order carry line, and simultaneously the possible carry of low level, i.e. the single order carry line state of low level, is transferred on this single order carry line; 3. when 4 number sums are " 2 ", putting this position, to enter 3 lines be low level, and setting single order carry line is high level, selects the second order carry line of low level to generate this second order carry simultaneously; 4. when 4 number sums are " 3 ", putting single order carry line is high level, selects the single order carry line of low level to generate this second order carry simultaneously, then enters 3 lines by low level and decide this position and enter 3 line states; 5. when 4 number sums are " 4 ", put single order carry line and second order carry line is high level, deciding this position by the second order carry line of low level enters 3 line states simultaneously.
According to " single order carry line ", " second order carry line " and " entering 3 lines " that the present invention introduces, adopt form list certain " single order carry line ", " second order carry line ", " entering 3 lines " and finally one's own department or unit and and low level related data between relation.If: alphabetical A represent certain 4 original input numbers and, Y represents its parity, Si represent final one's own department or unit that these 4 original input numbers are added with low order carry and, Ci_2 and Ci_1 represents this second order carry line and single order carry line state respectively, Ci_3 represents that 3 line states are entered in this position, letter b represents may adding of low level and (i.e. its 4 original input numbers and the summation of its low order carry, maximumly be no more than 7) instead of final one's own department or unit and, Ci-1_3, what Ci-1_2 and Ci-1_1 represented low level respectively enters 3 lines, second order carry line and single order carry line state, the results are shown in Table 1.
Table 1 operation relation table
The principle of design of carry synthetic circuit is explained: 1. when 4 number sums are for " 0 " according to table 1, Ci_3=0, Ci_2=0, Ci_1=Ci-1_2, that is, on the one hand, no matter whether low level produces carry, this position all can not produce second order carry, also can not affect into 3 line states, and namely 3 lines are entered and second order carry line is low level in this position; On the other hand, the second order carry of low level is only had to be the single order carry line state that high level just can affect this, so the second order carry transmitting low level will be selected, instead of the single order carry of low level.2. when 4 number sums are " 1 ", Ci_3=0, Ci_2=Ci-1_3, Ci_1=Ci-1_1, that is, on the one hand, no matter whether low level produces carry, it is all low level that 3 line states are entered in this position, and this second order carry be subject to low level enter 3 line states control; On the other hand, no matter whether the second order carry line of low level is high level, as long as the single order carry line of low level is high level, so this position all can produce single order carry, thus selects the single order carry line state of transmission low level.Here considering single order carry line when second order carry line is high level also must be the situation of high level.3. when 4 number sums are " 2 ", Ci_3=0, Ci_2=Ci-1_2, Ci_1=1, this just explanation, 3 lines are entered in this position not to be affected by low order carry, keep low level, and if low level second order carry line is high level, then this second order carry line is high level, otherwise be low level, thus will select the second order carry transmitting low level.Why arranging this single order carry line is high level, is not only to illustrate that the several sum in this position 4 creates carry, or in order to ensure that the situation that the several sum in this position 4 is more than or equal to " 2 " is not masked because of low level no-carry.4. when 4 number sums are " 3 ", Ci_3=Ci-1_3, Ci_2=Ci-1_1, Ci_1=1, that is, on the one hand enter 3 lines by low level and determine that 3 line states are entered in this position, and to arrange single order carry line be high level, on the other hand, no matter whether the second order carry of low level is high level, as long as the single order carry line of low level is high level, namely low level creates carry, so this position all can produce second order carry, thus selects the single order carry line of low level to generate this second order carry.5., when 4 number sums are " 4 ", Ci_3=Ci-1_2, Ci_2=1, Ci_1=1, that is, one side directly arranges single order carry line and second order carry line is high level, on the other hand, decides this position enter 3 line states by the second order carry of low level.
The design of this carry synthetic circuit has three large features: one, adopt on-off circuit completely, because resistance is huge when switch has a disconnection, during conducting, via resistance is very little and conduct electricity the feature such as rapid; Two, between low level and " entering 3 lines ", " second order carry line " and " single order carry line " this three line of a high position, both a low bit line and more than 2 high bit line conductings had simultaneously been there will not be, also there will not be a high bit line and the conducting simultaneously of the low bit line of two or more, and formed on the switching channels leading to high-order " entering 3 lines ", " second order carry line " and " single order carry line ", each passage only has at most a way switch conducting, without feedback and crosstalk between the high-low-position carry guaranteeing circuit; Three, carry synthetic circuit only takies the time of a basic gate circuit.
Final one's own department or unit and generation circuit are made up of two groups of on-off circuits and a pull down resistor.These two groups of on-off circuits are defined as even control circuit respectively and post control circuit, the merged final one's own department or unit as this of its output terminal and output, and provide low level by the pull down resistor connected.The final one's own department or unit of each and generation circuit are all controlled by enter 3 lines, second order carry line and single order carry line from low order carry synthetic circuit, to select out-put supply complementation initially to add and the strange power output signal of circuit or even power output signal.This circuit also only takies the time of a basic gate circuit.
Provide final one's own department or unit according to table 1 and produce the design concept of circuit.As Y=1, power supply complementation initially adds provides power supply with the strange power end of circuit, even control circuit work, and posting control circuit is high-impedance state, if now Ci-1_3, three's high level number sum of Ci-1_2 and Ci-1_1 is even number, then have a way switch path conducting in even control circuit, have selected power supply complementation initially add with circuit post power supply export, Si exports high level, otherwise without any way switch path conducting in even control circuit, Si is defined as low level by pull down resistor; As Y=0, power supply complementation initially adds provides power supply with the even power end of circuit, and post control circuit work, even control circuit is high-impedance state, if now Ci-1_3, three's high level number sum of Ci-1_2 and Ci-1_1 for posting number, is then posted in control circuit and is had a way switch path conducting, have selected power supply complementation and initially adds the even power supply output with circuit, Si exports high level, otherwise post without any way switch path conducting in control circuit, Si is defined as low level by pull down resistor.
In the present invention, statistical circuit takies a basic gate circuit time, and power supply complementation initially adds and starts with circuit and carry synthetic circuit simultaneously, takies a basic gate circuit time altogether, final one's own department or unit and produce circuit and also only take a basic gate circuit time.Consider that the present invention uses on-off circuit, on it, the information transmission time is short more than the Time Created of switch conduction, like this, once related switch is simultaneously open in the carry synthetic circuit of all positions, the information transmission time from lowest order to most significant digit can be ignored, therefore, totalizer of the present invention only needs the used time of 3 basic gate circuits, has nothing to do in limited range with addend figure place.
Based on foregoing invention description of contents and the illustrative examples that provides of accompanying drawing subsequently, compared with prior art, circuit structure of the present invention is regular, low in energy consumption, and the used time is few, only need 3 the basic gate circuit times fixed, have nothing to do with addend figure place, hardware spending is low, linear with addend figure place, be easy to expansion, the adding circuit of more than 128 can be accomplished meeting under cost performance requires.
By reading content of the present invention, combining innovation etc. pointed in the description of the drawings below and claims, those skilled in the art can have clearer understanding and understanding to above-mentioned content relevant with other of the present invention and target, some advantages of the present invention and new application may be there is do not provide at this, but still wish to be included in the limited range of following claims.
In order to more comprehensively, systematically understand content of the present invention, be described in further detail below in conjunction with accompanying drawing.
Accompanying drawing illustrates:
Fig. 1 is theory diagram of the present invention;
Fig. 2 is the illustrative examples schematic diagram expanding four addend binary parallel synchronous addition devices of the present invention;
Fig. 3 present invention is directed at a certain position to be input to the illustrative circuitry embodiment schematic diagram adding and export with result from addend;
Fig. 4 is the illustrative examples schematic diagram of non-expansion four addend binary parallel synchronous addition device of the present invention.
Embodiment:
Below in conjunction with accompanying drawing, illustrative examples of the present invention is described in detail.Described by note that hereafter is illustrative examples of the present invention, and should not be limited to these embodiments and following description when understanding of the present invention.
Fig. 1 is theory diagram of the present invention, and it forms primarily of multiple unit 110,120 and 130.Wherein unit 110 is exactly identical weights figure place adder circuit, can add up the number of " 1 " in original input number, and determines the on off operating mode of two-way power supply according to result parity; Unit 120 is exactly carry synthetic circuit, can carry out selection conducting by the statistics of unit 110 to the information from low level, to produce single order carry, second order carry and to enter 3 line information; Unit 130 be exactly final one's own department or unit and produce circuit, according to the carry information from low level, the two-way power supply that unit 110 provides can be selected, thus produce final one's own department or unit and.
Fig. 2 gives the schematic diagram of Fig. 1, using 4 16 figure place totalizers as illustrative examples of the present invention.In order to the course of work of unit 110,120 and 130 in more clear description Fig. 2, we choose the unit 110,120 and 130 of any weights position, and are marked in figure 3 in detail.Can find out, unit 110 is made up of unit 111 and unit 112 again.
Unit 111 is exactly statistical circuit, is made up of selector switch array, is mainly used in the number of adding up " 1 " in original input number.When 4 inputs Ai_0, Ai_1, Ai_2 and Ai_3 are low level, all selector switch select contact, left side (or claiming low-pressure side contact), output terminal Yi_2, Mi_1, Yi_1 and Mi_0 all output low levels; When 4 inputs Ai_0, Ai_1, Ai_2 and Ai_3 are high level, all selector switch select contact, right side (or claiming contact, high-pressure side), and output terminal Yi_2, Mi_1, Yi_1 and Mi_0 export high level; When 4 inputs Ai_0, Ai_1, Ai_2 and Ai_3 are any high and low level combinations, the selector switch that high level controls selects contact, right side, the selector switch of low level control selects contact, left side, and output terminal Mi_0, Yi_1, Mi_1 and Yi_2 will export the number of " 1 " in addend with the form of continuous high level.If Yi_2 and Mi_1 is low level, Yi_1 and Mi_0 is high level, illustrates in Ai_0, Ai_1, Ai_2 and Ai_3 have 2 high level.
Unit 112 is exactly that power supply complementation initially adds and circuit, selects to export two-way power supply, to be supplied to unit 130 according to the parity of these 4 original input number sums.When 4 number sums are " 1 ", only input end Mi_0 is high level, K switch 1+ and K2-conducting (wherein, "+" and "-" in switch symbols represents that this switch is high level conducting or low level conducting, identical below), Yi_0 holds, i.e. strange power end, exports high level, backward end/Yi_0, namely even power end, presents high-impedance state; When 4 number sums are " 3 ", input end Mi_1, Yi_1 and Mi_0 are high level, K switch 3+ and K4-conducting, and Yi_0 end exports high level, and/Yi_0 end presents high-impedance state; When 4 number sums are " 0 ", all input end Yi_2, Mi_1, Yi_1 and Mi_0 are low level, K switch 7-conducting, and/Yi_0 end exports high level, and Yi_0 end presents high-impedance state; When 4 number sums are " 2 ", only input end Yi_1 and Mi_0 is high level, K switch 5+, K6-conducting, and/Yi_0 end exports high level, and Yi_0 end presents high-impedance state; When 4 number sums are " 4 ", all input ends are all high level, K switch 8+ conducting, and/Yi_0 end exports high level, and Yi_0 end presents high-impedance state.Visible, when 4 number sums are odd number, Yi_0 end exports high level, is input to unit 130, and/Yi_0 end presents high-impedance state; When 4 number sums are even number, backward end/Yi_0 exports high level, is input to unit 130, Yi_0 end and presents high-impedance state.
Unit 120 is selected single order carry line Ci-1_1, the second order carry line Ci-1_2 of low level according to the value of input end Yi_2, Mi_1, Yi_1 and Mi_0 and enters 3 line Ci-1_3 generate this single order carry, second order carry and enter the value of 3 lines, or utilize pull down resistor R1, R3 and R2 limit single order carry line, second order carry line respectively and enter 3 lines for low level, its course of work is as follows:
(1) when Yi_2, Mi_1, Yi_1 and Mi_0 are low level (illustrating that original input number sum is 0), low level single order carry on this carry without impact, as long as and low level second order carry line is high level, this position will produce single order carry, but second order carry can not be produced, thus Mi_0 gauge tap K20-conducting, this single order carry line and the conducting of low level second order carry line, Simultaneous Switching K9+, K10+, K12+, K14+, K17+, K18+, K19+ and K21+ disconnect, this second order carry line and enter 3 lines and be defined as low level by pull down resistor.
(2) when Yi_2, Mi_1 and Yi_1 are low level, when Mi_0 is high level (illustrating that original input number sum is 1), as long as low level produces carry, no matter be low level second order carry, or low level single order carry, all will be transmitted to a high position with single order carry value by this position, thus Yi_1 and Mi_0 control K22-and K21+ conducting respectively, low level single order carry line and this single order carry line conducting.In addition, if low level enters 3, namely entering 3 lines is high level, then this position also can produce second order carry, so the controlled conducting processed of K16-, K15-, K13-and K12+, enters by low level the state that 3 lines determine second order carry line.Cut-off switch K9+, K10+, K14+, K17+, K18+, K19+ and K20-, enter 3 lines and be defined as low level by pull down resistor simultaneously.
(3) when Yi_2 and Mi_1 is low level, when Yi_1 and Mi_0 is high level (illustrating that original input number sum is 2), if low level second order carry line is high level, will be transmitted to a high position with second order carry by this position, otherwise, this second order carry line will be low level, thus by Yi_2, Mi_1 and Yi_1 gauge tap K16-, K15-and K14+ conducting respectively, to select second order carry line.In addition, Yi_1 gauge tap K19+ conducting, to force single order carry line to be high level.Meanwhile, K switch 9+, K10+, K13-, K17+, K18+, K20-and K22-disconnect, and enter 3 lines and are defined as low level by pull down resistor.
(4) when Yi_2 is low level, Mi_1 is that (now Yi_1 and Mi_0 is also high level to high level, illustrate that original input number sum is 3) time, no matter whether low level second order carry line is high level, as long as single order carry line is high level, namely necessarily there is carry in low level, and so this position all can produce second order carry, thus by Yi_2 and Mi_1 gauge tap K16-and K17+ conducting respectively, to select single order carry line.In addition, Yi_1 gauge tap K19+ conducting, to force single order carry line to be high level.Meanwhile, Yi_2 and Mi_1 gauge tap K11-and K10+ conducting, enter 3 lines by low level and determine that this enters the state of 3 lines.
(5) when Yi_2 is that (now Mi_1, Yi_1 and Mi_0 are also high level to high level, illustrate that original input number sum is 4) time, no matter whether low level produces carry, this second order carry line and single order carry line are all high level, thus by Yi_2 and Yi_1 gauge tap K18+ and K19+ conducting respectively.In addition, no matter low level enters 3 line states, as long as low level second order carry line is high level, it is just high level that 3 lines are entered in this position, so Yi_2 gauge tap K9+ conducting, to transmit low level second order carry line state.
Above-mentioned analytic explanation, no matter any in five kinds of situations, at the single order carry line of low level, second order carry line with enter 3 lines and this single order carry line, second order carry line and enter neither to exist between 3 lines the situation that a low bit line communicates with multiple high bit line simultaneously, there is not the situation that a high bit line communicates with multiple low bit line simultaneously yet, and formed on the switching channels entering 3 lines, second order carry line and single order carry line leading to a high position, each passage only has at most a way switch conducting.This has just cut off single order carry line, the second order carry line of coordination and has entered 3 lines by on-off circuit generation interference mutually, ensure that circuit normally works.
Unit 130 is made up of unit 131 and 132 again, by single order carry line Ci-1_1, the second order carry line Ci-1_2 of low level with enter output level Yi_0 and the/Yi_0 that 3 line Ci-1_3 select transmission units 112.
Unit 131 is exactly post control circuit, meets the designing requirement of Y=0 in table 1.Unit 132 is exactly even control circuit, meets the designing requirement of Y=1 in table 1.As Y=0, namely A=0, or A=2, or A=4, now ,/Yi_0 is switched on power by unit 112 breaker in middle, and Yi_0 is high-impedance state.If the high level number sum of Ci-1_1, Ci-1_2 and Ci-1_3 is odd number, then K switch 26-and K25+ conducting, or K switch 28+ conducting, unit 132 is without impact, Si exports high level, otherwise K switch 26-and K25+ branch road, and K switch 28+ branch road disconnects simultaneously, unit 132 is without impact, and Si is forced to low level by pull down resistor R4.Remark additionally here, according to table 1 and the present invention's spirit, in the probable value of Ci-1_1, Ci-1_2 and Ci-1_3, do not have that Ci-1_1 is low level and Ci-1_2 is the combination of high level, also do not have that Ci-1_2 is low level and Ci-1_3 is the combination of high level.As Y=1, namely A=1 or A=3, now, Yi_0 is switched on power by unit 112 breaker in middle, and/Yi_0 is high-impedance state.If the high level number sum of Ci-1_1, Ci-1_2 and Ci-1_3 is even number, then K switch 24+ and the conducting of K23-branch road, or the conducting of K switch 27-branch road, unit 131 is without impact, Si exports high level, otherwise K switch 24+ and K23-branch road, and K switch 27-branch road disconnects simultaneously, unit 131 is without impact, and Si is forced to low level by pull down resistor R4.
From Fig. 2 and Fig. 3, when 4 addend A0_0 ~ A15_0, A0_1 ~ A15_1, A0_2 ~ A15_2 and A0_3 ~ A15_3 are applied to each weights bit location 111 simultaneously, the concurrent working of all unit 111, and after a basic gate circuit time, synchronism output result.These output signals are synchronously applied to the unit 112 and 120 of corresponding positions.Their concurrent workings, after a basic gate circuit time, the corresponding result of synchronism output, wherein all unit 120 are at single order carry line, second order carry line with enter on 3 lines to export corresponding carry value, and all unit 112 are held and backward end/Yi_0 output high level or present high-impedance state at its Yi_0.Finally, the output signal of all unit 112 and 120 is synchronously applied to corresponding positions unit 130, so all unit 131 and 132 start concurrent working, also after a basic gate circuit time, final one's own department or unit of synchronism output corresponding positions and.Visible, 4 16 figure places of the present invention are cumulative only needs 3 basic gate circuit times, and equally, 4 addends for more seniority are added, and also only need 3 basic gate circuit times.In addition, the present invention approximately needs 48n switch (wherein in unit 111,1 selector switch is equivalent to 2 switches) for 4 n figure place adder circuits.
Fig. 2 is four addend binary parallel synchronous addition devices of the present invention can illustrative examples under expansion state.This totalizer has identical unit 110,120 and 130 due to each, is thus easy to expand addition number figure place, implements 4 addend adder designs of not isotopic number, also can use multiple so identical totalizer not increasing series connection in situation consuming time.When carrying out low Bits Expanding, input end C-1_1, C-1_2 and C-1_3 of low level can be used for being connected to high-order single order carry line, the second order carry line of another four addends totalizer respectively and enter 3 lines; When not needing to carry out low level expansion, C-1_1, C-1_2 and C-1_3 connect low level; When carrying out high Bits Expanding, control end CTR1 and CTR2 connects low level, S17 and S16 is exactly high-order second order carry line and single order carry line, can be used for connecting second order carry line, the single order carry line of another four addends totalizer lowest order and enter 3 lines together with C15_3; When not needing to carry out high position expansion, control end CTR1 is connected to S17, and CTR2 is connected to C15_3.Now, S17 and S16 is high-order second order carry and the single order carry output of 4 16 figure place totalizers respectively.Here need illustrate, the switch that CTR1 with CTR2 controls enabling time point with consuming time in consistent with unit 130, also, this part additionally can't increase the consuming time of four addend binary parallel synchronous addition devices.In addition, according to the present invention's spirit, the switch that CTR1 controls guarantees that single order carry can not be forced high level when second order carry is high level, and the switch that CTR2 controls then is guaranteed both to have produced when second order carry also produces single order carry in a high position to demonstrate single order carry value.
Fig. 4 is the illustrative examples of four addend binary parallel synchronous addition devices of the present invention under non-expansion condition.This is also 4 addend 16 binary adders, and the part different from Fig. 2 is at lowest order, secondary low level circuit, and the carry of most significant digit forms circuit.Because do not need to expand, so Fig. 4 circuit lowest order does not have input end C-1_1, C-1_2 and C-1_3, decrease backward end/Y0_0 and form circuit, and unit 130, the single order carry line state that a switch obtains this is controlled by means of only Y0_1, control by Y0_2 the second order carry value that a switch obtains this, and directly form final one's own department or unit, this position and S0 by port Y0_0; Secondary low level compared with its high position because its low level to delete all switches entering 3 lines with low level and be associated without entering 3 lines; Formed in circuit in the carry of most significant digit, directly with second order carry line with enter 3 lines and respectively control a switch, to obtain single order carry value and the second order carry value of most significant digit.
In figs. 2,3 and 4, in unit 111, selector switch and other unit breaker in middle can be made with different materials, as long as via resistance is very little and conduct electricity the feature such as rapid when meeting resistance huge, conducting when disconnecting, and applied environment etc., namely such switch can be used in the present invention, such as atom switch, quantum switch, photon switch, transistor switch and electric switch etc.
Although the present invention is description four addend multidigit binary parallel synchronous addition device, but it be also applicable to four numbers subtract each other, with, Xiang Huo, and two number to be multiplied etc. in a variety of computing circuit, as long as institute's stripping unit of the present invention and switch are carried out reasonable combination and amendment just can realize the function that a lot of the present invention do not mentioned.
Although describe the present invention by describing illustrative examples of the present invention, should be understood that, the people being proficient in this area still can carry out the various amendments in pro forma and details to the present invention, and does not depart from the spirit and scope of the present invention.
Claims (9)
1. four addend binary parallel synchronous addition devices, is characterized in that, described totalizer is primarily of identical weights figure place adder circuit, carry synthetic circuit, final one's own department or unit and produce circuit composition;
Identical weights figure place adder circuit is the circuit realizing 4 one digit numbers additions, and it is made up of two parts circuit, and a part is statistical circuit, and another part is that power supply complementation initially adds and circuit;
Statistical circuit mainly adds up the number of high level " 1 " or low level " 0 " in the original addend of each weights position, and at output terminal with continuous high level " 1 " and the display of continuous low level " 0 " array configuration;
Power supply complementary initially adding, controls 2 groups of switches with circuit by the output level of statistical circuit, wherein one group of switch conduction is selected, so that for final one's own department or unit with produce circuit and provide power supply (or being called high level) according to one's own department or units of this 4 original addend in weights position and parity;
The principle of design of carry synthetic circuit is: be directed to a certain position, 1. when 4 number sums are " 0 ", puts this position and enters 3 lines and second order carry line is low level, the possible second order carry of low level is transmitted to a high position with single order carry form simultaneously; 2. when 4 number sums are " 1 ", putting this position, to enter 3 lines be low level, and low level is entered 3 line states be transferred to this second order carry line, and simultaneously the possible carry of low level, i.e. the single order carry line state of low level, is transferred on this single order carry line; 3. when 4 number sums are " 2 ", putting this position, to enter 3 lines be low level, and setting single order carry line is high level, selects the second order carry line of low level to generate this second order carry simultaneously; 4. when 4 number sums are " 3 ", putting single order carry line is high level, selects the single order carry line of low level to generate this second order carry simultaneously, then enters 3 lines by low level and decide this position and enter 3 line states; 5. when 4 number sums are " 4 ", put single order carry line and second order carry line is high level, deciding this position by the second order carry line of low level enters 3 line states simultaneously;
Final one's own department or unit and produce circuit by even control circuit, post control circuit and a pull down resistor forms; The final one's own department or unit of each and generation circuit are all controlled by enter 3 lines, second order carry line and single order carry line from low order carry synthetic circuit, to select out-put supply complementation initially to add and the strange power output signal of circuit or even power output signal.
2. four addend binary parallel synchronous addition devices according to claim 1, is characterized in that: described statistical circuit have employed selector switch array, input the number of " 1 " or " 0 " in data at output terminal with the display of the form of continuous high level.
3. four addend binary parallel synchronous addition devices according to claim 1, is characterized in that: described power supply complementation initially add with circuit according to one's own department or unit and parity, utilize on-off circuit externally to select to provide a road power supply and a road high-impedance state; When one's own department or unit and be odd number time, one group of switch conduction, strange power end externally provides power supply, and another group switch disconnects, and even power end is externally in high-impedance state; Otherwise, when one's own department or unit and be even number time, even power end externally provides power supply, and strange power end is externally in high-impedance state.
4. four addend binary parallel synchronous addition devices according to claim 1, it is characterized in that: described carry synthetic circuit introduces single order carry line, second order carry line and enter 3 lines, wherein the low and high level of second order carry line represents corresponding position and whether creates second order carry, single order carry line is more than or equal to " 2 " by the original input number of corresponding position and low order carry value sum and determines, show that this position creates second order carry or single order carry, entering 3 lines is show whether corresponding position enters 3 to a high position, also be distinguish the single order carry line when second order carry line is high level whether to represent this position and create single order carry.
5. four addend binary parallel synchronous addition devices according to claim 1 or 4, it is characterized in that: between carry synthetic circuit low level and high-order " entering 3 lines ", " second order carry line " and " single order carry line " this three line, both a low bit line and more than 2 high bit line conductings had simultaneously been there will not be, also there will not be a high bit line and the conducting simultaneously of the low bit line of two or more, and formed on the switching channels leading to high-order " entering 3 lines ", " second order carry line " and " single order carry line ", each passage only has at most a way switch conducting.
6. four addend binary parallel synchronous addition devices according to claim 1, it is characterized in that: even control circuit and the merged final one's own department or unit as corresponding position of output terminal and the output of posting control circuit of described final one's own department or unit and generation circuit, and provide low level by the pull down resistor connected; When one's own department or unit and be odd number time, power supply complementation initially adds provides power supply with the strange power end of circuit, even control circuit work, posting control circuit is high-impedance state, if now low level " enters 3 lines ", three's high level number sum of " second order carry line " and " single order carry line " is even number, then has a way switch path conducting in even control circuit, final one's own department or unit and be high level, otherwise, without any way switch path conducting in even control circuit, final one's own department or unit and be defined as low level by pull down resistor; When one's own department or unit and be even number time, power supply complementation initially adds provides power supply with the even power end of circuit, post control circuit work, even control circuit is high-impedance state, if now low level " enters 3 lines ", three's high level number sum of " second order carry line " and " single order carry line " is odd number, then posts in control circuit and has a way switch path conducting, final one's own department or unit and be high level, otherwise, post without any way switch path conducting in control circuit, final one's own department or unit and be defined as low level by pull down resistor.
7. four addend binary parallel synchronous addition devices according to claim 1, it is characterized in that: described statistical circuit takies a basic gate circuit time, power supply complementation initially adds and starts with circuit and carry synthetic circuit simultaneously, take a basic gate circuit time altogether, final one's own department or unit and generation circuit also only take a basic gate circuit time.
8. four addend binary parallel synchronous addition devices according to claim 1, is characterized in that: the described totalizer used time is the time of 3 basic gate circuits, and hardware spending is low, linear with addend figure place.
9. four addend binary parallel synchronous addition devices according to claim 1, is characterized in that: described totalizer be also applicable to four numbers subtract each other, with, Xiang Huo, and in two several a variety of computing circuits such as to be multiplied.
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