CN103298247A - Circuit board and manufacturing method thereof - Google Patents
Circuit board and manufacturing method thereof Download PDFInfo
- Publication number
- CN103298247A CN103298247A CN2012100430299A CN201210043029A CN103298247A CN 103298247 A CN103298247 A CN 103298247A CN 2012100430299 A CN2012100430299 A CN 2012100430299A CN 201210043029 A CN201210043029 A CN 201210043029A CN 103298247 A CN103298247 A CN 103298247A
- Authority
- CN
- China
- Prior art keywords
- internal layer
- layer circuit
- circuit
- insulating barrier
- low residual
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 127
- 229910052802 copper Inorganic materials 0.000 claims abstract description 69
- 239000010949 copper Substances 0.000 claims abstract description 69
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 230000004888 barrier function Effects 0.000 claims description 58
- 239000011889 copper foil Substances 0.000 claims description 58
- 238000003825 pressing Methods 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000002360 preparation method Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09881—Coating only between conductors, i.e. flush with the conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09909—Special local insulating pattern, e.g. as dam around component
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
A circuit board comprises an inner circuit substrate, a first rubber layer and a first external circuit, wherein the inner circuit substrate, the first rubber layer and the first external circuit are stacked in sequence, the inner circuit substrate comprises an insulating layer, a first inner circuit formed on one surface of the insulating layer and a first low residual copper area, and the area, covered by the first inner circuit, of the insulating layer is smaller than that of the first low residual copper area by 60% within the first low residual copper area. The circuit board further comprises a first filled layer, wherein the first filled layer is formed between the inner circuit substrate and the first rubber layer and only located on the first inner circuit within the first low residual copper area and on the insulating layer exposed from the gap of the first inner circuit. The invention further provides a manufacturing method of the circuit board.
Description
Technical field
The present invention relates to the circuit board making field, relate in particular to a kind of circuit board and preparation method thereof.
Background technology
Printed circuit board (PCB) has obtained using widely because having the packaging density advantages of higher.Application about circuit board sees also document Takahashi, A. Ooki, N. Nagai, A. Akahoshi, H. Mukoh, A. Wajima, M. Res. Lab, High density multilayer printed circuit board for HITAC M-880, IEEE Trans. on Components, Packaging, and Manufacturing Technology, 1992,15 (4): 418-425.
In the manufacturing process of circuit board, adopt the internal layer circuit of substrate manufacture circuit board usually earlier, be formed with pressing glue-line and Copper Foil on the substrate of internal layer circuit then, the Copper Foil with pressing is made into outer-layer circuit again.Yet in the manufacturing process of circuit board, the thickness of the glue-line between the adjacent conductive layer has requirement.Internal layer circuit has the bigger zone of distribution density and the less zone (the less zone of residual copper rate) of internal layer circuit distribution density, expose the surface of the insulating barrier of substrate owing to the most of etched removal of the Copper Foil in the less zone of residual copper rate, like this, when glue-line being pressed to these zones, need more glue to flow to these less zones of residual copper rate, thereby make that the thickness of the glue-line that forms after the pressing is less, can not meet the demands.
Summary of the invention
Therefore, be necessary to provide a kind of circuit board and preparation method thereof, cause the problem that thickness can not meet the demands after the glue-line pressing owing to the residual copper rate of internal layer circuit is lower with effective solution.
Below will a kind of circuit board and preparation method thereof be described with embodiment.
A kind of circuit board, it comprises the internal layer circuit substrate that stacks gradually, first glue-line and first outer-layer circuit, described internal layer circuit substrate comprises insulating barrier and is formed at first internal layer circuit on a surface of insulating barrier, described internal layer circuit substrate comprises the first low residual copper zone, in the described first low residual copper zone, hanged down residual copper region area 60% by the area of the described first internal layer circuit covered dielectric layer less than first, described circuit board also has first packed layer, described first packed layer is formed between internal layer circuit substrate and first glue-line, and described first packed layer only is formed at the space from first internal layer circuit in the described first low residual copper zone and exposes on the insulating barrier or first internal layer circuit reaches and exposes on the insulating barrier from the space between first internal layer circuit.
A kind of manufacture method of circuit board comprises step: substrate is provided, and described substrate comprises insulating barrier and is formed at first copper foil layer of surface of insulating layer; Described first copper foil layer is made formation first internal layer circuit, obtain the internal layer circuit substrate, described internal layer circuit substrate comprises the first low residual copper zone, and in the described first low residual copper zone, the area of the first internal layer circuit covered dielectric layer is less than the first low residual copper region area 60%; Only in the described first low residual copper zone, expose on the insulating barrier from the space of second internal layer circuit or first internal layer circuit and expose insulating barrier from the space of first internal layer circuit and form first packed layer; At first internal layer circuit of internal layer circuit substrate and surperficial pressing first glue-line and first outer copper foil of first packed layer; And with described first outer copper foil making formation, first outer-layer circuit.
A kind of manufacture method of circuit board, comprise step: make the internal layer circuit substrate, described internal layer circuit substrate comprises insulating barrier, be formed at lip-deep first internal layer circuit of insulating barrier and second internal layer circuit that is formed on another apparent surface of insulating barrier, described internal layer circuit substrate comprises the first low residual copper zone and the second low residual copper zone, in the described first low residual copper zone, the area of the first internal layer circuit covered dielectric layer is less than the first low residual copper region area 60%, in the described second low residual copper zone, the area of the second internal layer circuit covered dielectric layer is less than the second low residual copper region area 60%; Only in the described first low residual copper zone, expose on the insulating barrier from the space of first internal layer circuit or first internal layer circuit and expose insulating barrier from the space of first internal layer circuit and form first packed layer, only in the described second low residual copper zone, expose on the insulating barrier from the space of second internal layer circuit or second internal layer circuit and expose insulating barrier from the space of second internal layer circuit and form second packed layer; At first internal layer circuit of internal layer circuit substrate and surperficial pressing first glue-line and first outer copper foil of first packed layer, at second internal layer circuit of internal layer circuit substrate and surperficial pressing second glue-line and second outer copper foil of second packed layer; And with described first outer copper foil making formation, first outer-layer circuit, described second outer copper foil is made formation second outer-layer circuit.
Compared with prior art, circuit board that the technical program provides and preparation method thereof, in the lower zone of the residual copper rate of internal layer circuit, form and internal layer circuit thickness packed layer about equally, like this, in the process of follow-up pressing glue-line, the problem that can avoid the thickness of the glue-line that causes owing to the solation quantity not sufficient not meet the demands, thus improve the making yield of circuit board.
Description of drawings
Fig. 1 is the generalized section of the substrate that provides of the technical program embodiment.
Fig. 2 is the generalized section after the substrate manufacture of Fig. 1 forms the internal layer circuit substrate.
Fig. 3 is the floor map of the internal layer circuit substrate of Fig. 2.
Fig. 4 is the generalized section after the internal layer circuit substrate of Fig. 2 forms first packed layer and second packed layer.
Fig. 5 is the generalized section behind internal layer circuit substrate pressing first glue-line, first outer copper foil, second glue-line and second outer copper foil of Fig. 3.
Fig. 6 is the schematic diagram that Fig. 5 makes the circuit board of formation.
The main element symbol description
| Circuit board | 100 |
| |
110 |
| |
111 |
| First |
112 |
| Second |
113 |
| First |
114 |
| Second |
115 |
| The internal |
120 |
| The first low |
121 |
| The second low |
122 |
| First packed |
131 |
| Second packed |
132 |
| First glue- |
141 |
| Second glue- |
142 |
| First |
151 |
| Second |
152 |
| First outer-layer circuit | 161 |
| Second outer-layer circuit | 162 |
Following embodiment will further specify the present invention in conjunction with above-mentioned accompanying drawing.
Embodiment
Present embodiment illustrates that with the manufacture method of four-layer circuit board the circuit board manufacturing method that present embodiment provides comprises the steps:
The first step sees also Fig. 1, and a substrate 110 is provided.
Second step saw also Fig. 2 and Fig. 3, first copper foil layer 112 was made forming first internal layer circuit 114, second copper foil layer 113 was made forming second internal layer circuit 115, obtained internal layer circuit substrate 120.
First internal layer circuit 114 and second internal layer circuit 115 all can adopt image transfer technology and etch process to make.Internal layer circuit substrate 120 comprises the 121 and second low residual copper zone 122, the first low residual copper zone.In the first low residual copper zone 121, etching forms the area of remaining first copper foil layer 112 in first internal layer circuit, 114 backs less than 60% of the first low residual copper zone, 121 former first copper foil layer, 112 areas, namely when etching forms first internal layer circuit 114, in the first low residual copper zone, 121 inner area ratios greater than 40% first copper foil layer, 112 etched removals.In the second low residual copper zone 122, etching forms the area of remaining second copper foil layer 113 in second internal layer circuit, 115 backs less than 60% of the second low residual copper zone, 122 former second copper foil layer, 113 areas, namely when etching forms second internal layer circuit 115, in the second low residual copper zone, 122 inner area ratios greater than 40% second copper foil layer, 113 etched removals.
121 and the second low residual copper zone 122, the first low residual copper zone can be separated from each other, also can be overlapped.
The 3rd step saw also Fig. 4, formed first packed layer 131 in first side of hanging down first internal layer circuit 114 in residual copper zone 121, formed second packed layer 132 in second side of hanging down second internal layer circuit 115 in residual copper zone 122.
Before forming first packed layer 131 and second packed layer 132, can further include the surface to first internal layer circuit 114, the surface of the insulating barrier 111 that exposes from the space between first internal layer circuit 114, the surface of second internal layer circuit 115 and between second internal layer circuit 115 the surface of the insulating barrier 111 that exposes of the space step of carrying out alligatoring, to increase insulating barrier 111 that insulating barrier 111 that first packed layer 131 that forms is in contact with it and the adhesion between first internal layer circuit 114 and second packed layer 132 be in contact with it and the adhesion between second internal layer circuit 115.The step of described alligatoring can adopt the mode of black brown to realize.
In the present embodiment, first packed layer 131 and second packed layer 132 all adopt the mode of printing dielectric ink to form.First packed layer 131 protrude from the insulating barrier 111 that exposes from the space between first internal layer circuit 114 the surface height can with the thickness of first copper foil layer 112 about equally.The height on the surface that protrudes from the insulating barrier 111 that exposes from the space between first internal layer circuit 114 of first packed layer 131 also can be slightly larger than the thickness of first copper foil layer 112, and namely first packed layer 131 covers the surface that first internal layer circuit 114 reaches the insulating barrier 111 that exposes from the space between first internal layer circuit 114.First packed layer 131 protrude from the insulating barrier 111 that exposes in the space between first internal layer circuit 114 the surface height should less than the glue-line of first copper foil layer, 112 thickness and follow-up setting by pressing after the glue-line thickness sum that need reach.First packed layer 131 protrudes from the height on the surface of the insulating barrier 111 that exposes in the space between first internal layer circuit 114 also can be less than the thickness of first copper foil layer 112, and namely first packed layer 131 only covers the surface of the insulating barrier 111 that exposes from the space between first internal layer circuit 114.
Second packed layer 132 protrude from the insulating barrier 111 that exposes from the space between second internal layer circuit 115 the surface height can with the thickness of second copper foil layer 113 about equally.The height on the surface that protrudes from the insulating barrier 111 that exposes from the space between second internal layer circuit 115 of second packed layer 132 also can be slightly larger than the thickness of second copper foil layer 113, and namely second packed layer 132 covers the surface that second internal layer circuit 115 reaches the insulating barrier 111 that exposes from the space between second internal layer circuit 115.Second packed layer 132 protrude from the insulating barrier 111 that exposes in the space between second internal layer circuit 115 the surface height should less than the glue-line of second copper foil layer, 113 thickness and follow-up setting by pressing after the glue-line thickness sum that need reach.Second packed layer 132 protrudes from the height on the surface of the insulating barrier 111 that exposes in the space between second internal layer circuit 115 also can be less than the thickness of second copper foil layer 113, and namely second packed layer 132 only covers the surface of the insulating barrier 111 that exposes from the space between second internal layer circuit 115.
The 4th step, see also Fig. 5, at first internal layer circuit 114 of internal layer circuit substrate 120 and surperficial pressing first glue-line 141 and first outer copper foil 151 of first packed layer 131, at second internal layer circuit 115 of internal layer circuit substrate 120 and surperficial pressing second glue-line 142 and second outer copper foil 152 of second packed layer 132.
Before pressing first glue-line 141, first outer copper foil 151, second glue-line 142 and second outer copper foil 152, can further include the surface of surface to first internal layer circuit 114, first packed layer 131, the surface of second internal layer circuit 115 and the step that alligatoring is carried out on second packed layer, 132 surfaces, to increase between first glue-line 141 that forms and first internal layer circuit 114 and first packed layer 131 and the adhesion between second glue-line 142 and second internal layer circuit 115 and second packed layer 132.The step of described alligatoring can adopt the mode of black brown to realize.
Because in previous step, be formed with first packed layer 131 and second packed layer 132 respectively in the 121 and second low residual copper zone 122, the first low residual copper zone, like this, space in first internal layer circuit 114 between the circuit in the less zone of residue Copper Foil is filled, thereby, when carrying out pressing, mobile glue can go to fill these spaces, makes first glue-line 141 after the pressing and the thickness of second glue-line 142 to meet the demands.
The 5th step saw also Fig. 6, first outer copper foil 151 was made forming first outer-layer circuit 161, second outer copper foil 152 was made forming second outer-layer circuit 162, obtained four-layer circuit board 100.
First outer-layer circuit 161 and second outer-layer circuit 162 can be made by image transfer technology and etching technique and be formed.
Be understandable that the circuit board manufacturing method that present embodiment provides is not limited to make four-layer circuit board, it can also be applied to the making of more multi-layered circuit board.Namely on the basis of the circuit board 100 that obtains, according to the mode in the 3rd step to the 5th step, proceed to increase layer and make, thereby obtain more multi-layered circuit board.
See also Fig. 6, the technical program also provides the circuit board 100 that adopts said method to make, and circuit board 100 comprises first outer-layer circuit 161, first glue-line 141, first packed layer 131, internal layer circuit substrate 120, second packed layer 132, second glue-line 142 and second internal layer circuit 115 successively.Internal layer circuit substrate 120 comprises insulating barrier 111 and is formed at 111 liang of lip-deep relatively first internal layer circuits 114 of insulating barrier and second internal layer circuit 115.Internal layer circuit substrate 120 comprises having and forms the residual copper rate in first internal layer circuit, 114 backs less than 60% the first low residual copper zone 121 and form the residual copper rate in second internal layer circuit, 115 backs less than 60% the second low residual copper zone 122.First packed layer 131 is formed at the surface of the insulating barrier 111 that exposes from the space of first internal layer circuit 114 in first internal layer circuit, 114 surfaces of the first low residual copper zone, 121 correspondences and this zone.The thickness of first packed layer 131 be used to form first internal layer circuit 114 Copper Foil thickness about equally.Second packed layer 132 is formed at the surface of the insulating barrier 111 that exposes from the space of second internal layer circuit 115 in second internal layer circuit, 115 surfaces of the second low residual copper zone, 122 correspondences and this zone.The thickness of second packed layer 132 be used to form second internal layer circuit 115 Copper Foil thickness about equally.
Circuit board that the technical program provides and preparation method thereof, in the lower zone of the residual copper rate of internal layer circuit, form and internal layer circuit thickness packed layer about equally, like this, in the process of follow-up pressing glue-line, the problem that can avoid the thickness of the glue-line that causes owing to the solation quantity not sufficient not meet the demands, thus the making yield of circuit board improved.
Be understandable that, for the person of ordinary skill of the art, can make other various corresponding changes and distortion by technical conceive according to the present invention, and all these change the protection range that all should belong to claim of the present invention with distortion.
Claims (10)
1. circuit board, it comprises the internal layer circuit substrate that stacks gradually, first glue-line and first outer-layer circuit, described internal layer circuit substrate comprises insulating barrier and is formed at first internal layer circuit on a surface of insulating barrier, described internal layer circuit substrate comprises the first low residual copper zone, in the described first low residual copper zone, hanged down residual copper region area 60% by the area of the described first internal layer circuit covered dielectric layer less than first, it is characterized in that, described circuit board also has first packed layer, described first packed layer is formed between internal layer circuit substrate and first glue-line, and described first packed layer only is formed at the space from first internal layer circuit in the described first low residual copper zone and exposes on the insulating barrier or be formed at first internal layer circuit and reach and expose on the insulating barrier from the space between first internal layer circuit.
2. circuit board as claimed in claim 1 is characterized in that, described first packed layer protrudes from from the height of the insulating barrier that exposes between first internal layer circuit and equates with the thickness of first internal layer circuit that is used to form described first internal layer circuit.
3. circuit board as claimed in claim 1, it is characterized in that, described circuit board also comprises second packed layer that is formed at internal layer circuit substrate opposite side, second glue-line and second outer-layer circuit, described internal layer circuit substrate also comprises second internal layer circuit on another surface that is formed at insulating barrier, described internal layer circuit substrate comprises the second low residual copper zone, in the described second low residual copper zone, less than the second low residual copper region area 60%, described second packed layer only is formed at and exposes on the insulating barrier from the space of described second internal layer circuit or be formed at second internal layer circuit in the described second low residual copper zone and expose on the insulating barrier from the space of second internal layer circuit by the area of the described second internal layer circuit covered dielectric layer.
4. the manufacture method of a circuit board comprises step:
Substrate is provided, and described substrate comprises insulating barrier and is formed at first copper foil layer of surface of insulating layer;
Described first copper foil layer is made formation first internal layer circuit, obtain the internal layer circuit substrate, described internal layer circuit substrate comprises the first low residual copper zone, and in the described first low residual copper zone, the area of the first internal layer circuit covered dielectric layer is less than the first low residual copper region area 60%;
Only in the described first low residual copper zone, expose on the insulating barrier from the space of second internal layer circuit or expose insulating barrier at first internal layer circuit and from the space of first internal layer circuit and form first packed layer;
At first internal layer circuit of internal layer circuit substrate and surperficial pressing first glue-line and first outer copper foil of first packed layer; And
Described first outer copper foil is made formation first outer-layer circuit.
5. the manufacture method of circuit board as claimed in claim 4 is characterized in that, described first packed layer adopts the mode of printing-ink to form.
6. the manufacture method of circuit board as claimed in claim 4 is characterized in that, described first packed layer protrudes from from the height of the insulating barrier that exposes between first internal layer circuit and equates with the thickness of first copper foil layer.
7. the manufacture method of circuit board as claimed in claim 4 is characterized in that, before forming described first packed layer, also comprises the step that alligatoring is carried out on the surperficial surface that reaches the insulating barrier that exposes from the space of first internal layer circuit of first internal layer circuit.
8. the manufacture method of circuit board as claimed in claim 4, it is characterized in that, before described first glue-line of pressing and first outer copper foil, comprise that also the surface to first packed layer reaches the step of carrying out alligatoring except the first low extra-regional internal layer circuit substrate surface of residual copper.
9. the manufacture method of a circuit board comprises step:
Make the internal layer circuit substrate, described internal layer circuit substrate comprises insulating barrier, be formed at lip-deep first internal layer circuit of insulating barrier and be formed at second internal layer circuit on another apparent surface of insulating barrier, described internal layer circuit substrate comprises the first low residual copper zone and the second low residual copper zone, in the described first low residual copper zone, the area of the first internal layer circuit covered dielectric layer is less than the first low residual copper region area 60%, in the described second low residual copper zone, the area of the second internal layer circuit covered dielectric layer is less than the second low residual copper region area 60%;
Only in the described first low residual copper zone, expose on the insulating barrier from the space of first internal layer circuit or at first internal layer circuit with expose insulating barrier from the space of first internal layer circuit and form first packed layer, only in the described second low residual copper zone, expose on the insulating barrier from the space of second internal layer circuit or expose insulating barrier at second internal layer circuit and from the space of second internal layer circuit and form second packed layer;
At first internal layer circuit of internal layer circuit substrate and surperficial pressing first glue-line and first outer copper foil of first packed layer, at second internal layer circuit of internal layer circuit substrate and surperficial pressing second glue-line and second outer copper foil of second packed layer; And
Described first outer copper foil is made formation first outer-layer circuit, described second outer copper foil is made forming second outer-layer circuit.
10. the manufacture method of circuit board as claimed in claim 9 is characterized in that, described first packed layer and second packed layer all adopt the mode of printing-ink to form.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100430299A CN103298247A (en) | 2012-02-24 | 2012-02-24 | Circuit board and manufacturing method thereof |
| TW101107685A TW201336367A (en) | 2012-02-24 | 2012-03-07 | Printed circuit board and method for manufacturing same |
| US13/537,073 US20130220683A1 (en) | 2012-02-24 | 2012-06-29 | Printed circuit board and method for manufacturing printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100430299A CN103298247A (en) | 2012-02-24 | 2012-02-24 | Circuit board and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103298247A true CN103298247A (en) | 2013-09-11 |
Family
ID=49001624
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012100430299A Pending CN103298247A (en) | 2012-02-24 | 2012-02-24 | Circuit board and manufacturing method thereof |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20130220683A1 (en) |
| CN (1) | CN103298247A (en) |
| TW (1) | TW201336367A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105451472A (en) * | 2014-08-26 | 2016-03-30 | 深南电路有限公司 | Laminated circuit board processing method and laminated circuit board |
| CN114980511A (en) * | 2021-02-19 | 2022-08-30 | 珠海方正科技高密电子有限公司 | Circuit board manufacturing method and circuit board |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ITMI20120194A1 (en) * | 2012-02-13 | 2013-08-14 | Cedal Equipment Srl | IMPROVEMENTS IN THE MANUFACTURE OF BATTERIES OF MULTILAYER PLASTIC LAMINATES FOR PRINTED CIRCUITS |
| US20160212859A1 (en) * | 2015-01-21 | 2016-07-21 | Gil Bellaiche | Printing electronic circuitry |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4528064A (en) * | 1980-12-08 | 1985-07-09 | Sony Corporation | Method of making multilayer circuit board |
| TW511436B (en) * | 2001-07-03 | 2002-11-21 | Taiwan Tokin Emc Engineering C | Improved print manufacturing method for laminated devices |
| US20070070613A1 (en) * | 2005-09-27 | 2007-03-29 | Samsung Electro-Mechanics Co., Ltd. | Method of manufacturing high density printed circuit boad |
| CN102143652A (en) * | 2010-01-30 | 2011-08-03 | 宏恒胜电子科技（淮安）有限公司 | Circuit board |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5344893A (en) * | 1991-07-23 | 1994-09-06 | Ibiden Co., Ltd. | Epoxy/amino powder resin adhesive for printed circuit board |
| US6010768A (en) * | 1995-11-10 | 2000-01-04 | Ibiden Co., Ltd. | Multilayer printed circuit board, method of producing multilayer printed circuit board and resin filler |
| KR100855530B1 (en) * | 1998-09-03 | 2008-09-01 | 이비덴 가부시키가이샤 | Multilayer printed wiring board and method for manufacturing the same |
| JP2003298232A (en) * | 2002-04-02 | 2003-10-17 | Sony Corp | Multilayer wiring board and method of manufacturing the same |
| KR101148679B1 (en) * | 2010-12-21 | 2012-05-25 | 삼성전기주식회사 | Multilayer printed circuit board and manufacturing method thereof |
-
2012
- 2012-02-24 CN CN2012100430299A patent/CN103298247A/en active Pending
- 2012-03-07 TW TW101107685A patent/TW201336367A/en unknown
- 2012-06-29 US US13/537,073 patent/US20130220683A1/en not_active Abandoned
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4528064A (en) * | 1980-12-08 | 1985-07-09 | Sony Corporation | Method of making multilayer circuit board |
| TW511436B (en) * | 2001-07-03 | 2002-11-21 | Taiwan Tokin Emc Engineering C | Improved print manufacturing method for laminated devices |
| US20070070613A1 (en) * | 2005-09-27 | 2007-03-29 | Samsung Electro-Mechanics Co., Ltd. | Method of manufacturing high density printed circuit boad |
| CN102143652A (en) * | 2010-01-30 | 2011-08-03 | 宏恒胜电子科技（淮安）有限公司 | Circuit board |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105451472A (en) * | 2014-08-26 | 2016-03-30 | 深南电路有限公司 | Laminated circuit board processing method and laminated circuit board |
| CN105451472B (en) * | 2014-08-26 | 2018-10-23 | 深南电路有限公司 | A kind of processing method and stacked wiring board of stacked wiring board |
| CN114980511A (en) * | 2021-02-19 | 2022-08-30 | 珠海方正科技高密电子有限公司 | Circuit board manufacturing method and circuit board |
| CN114980511B (en) * | 2021-02-19 | 2023-05-12 | 珠海方正科技高密电子有限公司 | Circuit board manufacturing method and circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201336367A (en) | 2013-09-01 |
| US20130220683A1 (en) | 2013-08-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103906372B (en) | There is circuit board of embedded element and preparation method thereof | |
| CN103906371B (en) | Circuit board with embedded element and preparation method thereof | |
| CN104349574B (en) | Circuit board and preparation method thereof | |
| CN103796445A (en) | Circuit board with buried element, and manufacturing method thereof | |
| CN104244614A (en) | Multilayer circuit board and manufacturing method thereof | |
| CN103260350B (en) | Blind buried via hole plate compression method | |
| CN103517582A (en) | Multilayer circuit board and manufacturing method thereof | |
| CN104219883A (en) | Circuit board provided with embedded element and manufacturing method thereof | |
| WO2014162478A1 (en) | Component-embedded substrate and manufacturing method for same | |
| CN103857209A (en) | Multi-layer circuit board and manufacture method for the same | |
| CN103391679A (en) | Rigid-flexible printed circuit board and method for manufacturing the same | |
| CN104254213A (en) | Multi-layer circuit board and manufacturing method thereof | |
| CN104427755A (en) | Flexible circuit board and manufacturing method thereof | |
| CN103298247A (en) | Circuit board and manufacturing method thereof | |
| CN103635005A (en) | Rigid-flex circuit substrate, rigid-flex circuit board and manufacturing methods | |
| CN102196668B (en) | Method for manufacturing circuit board | |
| CN103635028B (en) | Embedded type component circuit board and manufacturing method thereof | |
| CN104349592B (en) | Multilayer circuit board and preparation method thereof | |
| CN103313529A (en) | Method for manufacturing rigid-flexible circuit board | |
| CN103635007A (en) | Rigid-flexible circuit substrate, rigid-flexible circuit board and manufacturing method thereof | |
| CN107666782A (en) | Has circuit board of thick copper circuit and preparation method thereof | |
| TWI472273B (en) | Printed circuit board and method for manufacturing same | |
| CN104681532A (en) | Semiconductor package and fabrication method thereof | |
| CN106341945B (en) | A kind of flexible circuit board and preparation method thereof | |
| KR101805074B1 (en) | Preparation method of ceramic multilayer circuit board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130911 |